8N0DV76BG-0000CDI8 [IDT]
Quad-Frequency Programmable VCXO;
| 型号： | 8N0DV76BG-0000CDI8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Quad-Frequency Programmable VCXO 石英晶振 压控振荡器 |
| 文件： | 总20页 (文件大小：294K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Quad-Frequency Programmable
VCXO
IDT8N4QV01 REV G
DATASHEET
General Description
Features
The IDT8N4QV01 is a Quad-Frequency Programmable VCXO with
very flexible frequency and pull-range programming capabilities. The
device uses IDT’s fourth generation FemtoClock® NG technology for
an optimum of high clock frequency and low phase noise
performance. The device accepts 2.5V or 3.3V supply and is
packaged in a small, lead-free (RoHS 6) 10-lead ceramic 5mm x
7mm x 1.55mm package.
ꢀ Fourth generation FemtoClock® NG technology
ꢀ Programmable clock output frequency from 15.476MHz to
866.67MHz and from 975MHz to 1,300MHz
ꢀ Four power-up default frequencies (see part number order codes),
re-programmable by I2C
ꢀ I2C programming interface for the output clock frequency, APR
and internal PLL control registers
Besides the 4 default power-up frequencies set by the FSEL0 and
FSEL1 pins, the IDT8N4QV01 can be programmed via the I2C
interface to any output clock frequency between 15.476MHz to
866.67MHz and from 975MHz to 1,300MHz to a very high degree of
precision with a frequency step size of 435.9Hz ÷N (N is the PLL
output divider). Since the FSEL0 and FSEL1 pins are mapped to 4
independent PLL, P, M and N divider registers (P, MINT, MFRAC and
N), reprogramming those registers to other frequencies under
control of FSEL0 and FSEL1 is supported. The extended
ꢀ Frequency programming resolution is 435.9Hz ÷N
ꢀ Absolute pull-range (APR) programmable from 4.5ppm to
754.5ppm
ꢀ One 2.5V or 3.3V LVDS differential clock output
ꢀ Two control inputs for the power-up default frequency
ꢀ LVCMOS/LVTTL compatible control inputs
ꢀ RMS phase jitter @ 156.25MHz (12kHz - 20MHz): 0.494ps
temperature range supports wireless infrastructure, tele-
communication and networking end equipment requirements.
(typical)
ꢀ RMS phase jitter @ 156.25MHz (1kHz - 40MHz): 0.594ps (typical)
ꢀ 2.5V or 3.3V supply voltage modes
ꢀ -40°C to 85°C ambient operating temperature
ꢀ Lead-free (RoHS 6) packaging
Block Diagram
Pin Assignment
FemtoClock® NG
PFD
Q
nQ
÷P
OSC
&
LPF
÷N
VCO
1950-2600MHz
VC 1
OE 2
8 V
DD
114.285 MHz
7 nQ
6 Q
GND 3
÷MINT, MFRAC
2
A/D
VC
7
7
25
Pulldown
Pulldown
FSEL1
FSEL0
Configuration Register (ROM)
(Frequency, APR, Polarity)
IDT8N4QV01 REV G DATA SHEET
10-lead ceramic 5mm x 7mm x 1.55mm
package body
Pullup
Pullup
SCLK
SDATA
I2C Control
CD Package
Top View
Pullup
OE
IDT8N4QV01GCD REVISION A MARCH 11, 2014
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©2014 Integrated Device Technology, Inc.
IDT8N4QV01 REV G DATA SHEET
QUAD-FREQUENCY PROGRAMMABLE-VCXO
Table 1. Pin Descriptions
Number
Name
Type
Description
VCXO Control Voltage. The control voltage versus frequency characteristics are
set by the ADC_GAIN[5:0] register bits.
1
VC
Input
2
3
OE
Input
Pullup
Output enable pin. See Table 3B for function. LVCMOS/LVTTL interface levels.
Power supply ground.
GND
Power
FSEL0,
FSEL1
Default frequency select pins. See Table 3A for function and Table 8 for the
default frequency order codes. LVCMOS/LVTTL interface levels.
4, 5
Input
Pulldown
6, 7
8
Output
Power
Input
Differential clock output. LVDS interface levels.
Power supply pin.
Q, nQ
VDD
I2C Data Input. LVCMOS/LVTTL interface levels.
I2C Clock Input. LVCMOS/LVTTL interface levels.
9
Pullup
Pullup
SDATA
SCLK
10
Input
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
Test Conditions
FSEL[1:0], SDATA, SCLK
VC
Minimum
Typical
5.5
Maximum
Units
pF
CIN
Input Capacitance
10
pF
RPULLUP
Input Pullup Resistor
50
k
RPULLDOWN
Input Pulldown Resistor
50
k
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IDT8N4QV01 REV G DATA SHEET
QUAD-FREQUENCY PROGRAMMABLE-VCXO
Function Tables
Table 3A. Default Frequency Selection
Input
FSEL1
FSEL0
Operation
0 (default)
0 (default)
Default frequency 0
Default frequency 1
Default frequency 2
Default frequency 3
0
1
1
1
0
1
NOTE: The default frequency is the output frequency after power-up. One of four default frequencies is selected by FSEL[1:0]. See
programming section for details.
Table 3B. OE Configuration
Input
OE
0
Output Enable
Outputs Q, nQ are in high-impedance state.
Outputs are enabled.
1 (default)
NOTE: OE is an asynchronous control.
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QUAD-FREQUENCY PROGRAMMABLE-VCXO
Block Diagram with Programming Registers
Output Divider N
PFD
FemtoClock® NG
VCO
1950-2600MHz
Q
nQ
÷P
OSC
114.285 MHz
÷ N
&
LPF
2
7
Feedback Divider M (25 Bit)
MINT
(7 bits)
MFRAC
(18 bits)
A/D
VC
7
18
7
34
Programming Registers
ADC_GAIN
ADC_POL
1 bit
41
I2C Control
2
I C:
6 bits
6 bits
P0
Def:
1 bit
7
7
MINT0 MFRAC0
N0
2
I C:
2 bits 7 bits
2 bits 7 bits
18 bits
18 bits
7 bits
7 bits
N1
00
Def:
30
30
30
30
34
34
34
34
P1
MINT1 MFRAC1
2
I C:
2 bits 7 bits
2 bits 7 bits
18 bits
18 bits
7 bits
7 bits
N2
01
Def:
P2
MINT2 MFRAC2
34
2
Pullup
Pullup
I C:
2 bits 7 bits
2 bits 7 bits
18 bits
18 bits
7 bits
7 bits
N3
SCLK
10
Def:
SDATA
P3
MINT3 MFRAC3
2
I C:
2 bits 7 bits
2 bits 7 bits
18 bits
18 bits
7 bits
7 bits
11
Def:
Pulldown, Pulldown
Pullup
FSEL[1:0]
OE
Def: Power-up default register setting for I2C registers
ADC_GAINn, ADC_POL, Pn, MINTn, MFRACn and Nn
IDT8N4QV01GCD REVISION A MARCH 11, 2014
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IDT8N4QV01 REV G DATA SHEET
QUAD-FREQUENCY PROGRAMMABLE-VCXO
Principles of Operation
The block diagram consists of the internal 3rd overtone crystal and
oscillator which provide the reference clock fXTAL of either
114.285MHz or 100MHz. The PLL includes the FemtoClock NG VCO
along with the Pre-divider (P), the feedback divider (M) and the post
divider (N). The P, M, and N dividers determine the output frequency
based on the fXTAL reference and must be configured correctly for
proper operation. The feedback divider is fractional supporting a
huge number of output frequencies. The configuration of the
feedback divider to integer-only values results in an improved output
phase noise characteristics at the expense of the range of output
frequencies. In addition, internal registers are used to hold up to four
different factory pre-set P, M, and N configuration settings. These
default pre-sets are stored in the I2C registers at power-up. Each
configuration is selected via the FSEL[1:0] pins and can be read back
using the SCLK and SDATA pins.
As identified previously, the configurations of P, M (MINT & MFRAC)
and N divider settings are stored the I2C register, and the
configuration loaded at power-up is determined by the FSEL[1:0]
pins.
Table 4. Frequency Selection
Input
FSEL1
FSEL0
Selects
Register
0 (def.)
0 (def.)
Frequency 0
Frequency 1
Frequency 2
Frequency 3
P0, MINT0, MFRAC0, N0
P1, MINT1, MFRAC1, N1
P2, MINT2, MFRAC2, N2
P3, MINT3, MFRAC3, N3
0
1
1
1
0
1
The user may choose to operate the device at an output frequency
different than that set by the factory. After power-up, the user may
write new P, N and M settings into one or more of the four
configuration registers and then use the FSEL[1:0] pins to select the
newly programmed configuration. Note that the I2C registers are
volatile and a power supply cycle will reload the pre-set factory
default conditions.
Frequency Configuration
An order code is assigned to each frequency configuration
programmed by the factory (default frequencies). For more
information on the available default frequencies and order codes,
please see the Ordering Information Section in this document. For
available order codes, see the FemtoClock NG Ceramic-Package XO
and VCXO Ordering Product Information document.
If the user does choose to write a different P, M, and N configuration,
it is recommended to write to a configuration which is not currently
selected by FSEL[1:0] and then change to that configuration after the
I2C transaction has completed. Changing the FSEL[1:0] controls
results in an immediate change of the output frequency to the
selected register values. The P, M, and N frequency configurations
support an output frequency range 15.476MHz to 866.67MHz and
975MHz to 1,300MHz.
For more information and guidelines on programming of the device
for custom frequency configurations, the register description, the
pull-range programming and the serial interface description, see the
FemtoClock NG Ceramic 5x7 Module Programming Guide.
The devices use the fractional feedback divider with a delta-sigma
modulator for noise shaping and robust frequency synthesis
capability. The relatively high reference frequency minimizes phase
noise generated by frequency multiplication and allows more efficient
shaping of noise by the delta-sigma modulator.
The output frequency is determined by the 2-bit pre-divider (P), the
feedback divider (M) and the 7-bit post divider (N). The feedback
divider (M) consists of both a 7-bit integer portion (MINT) and an
18-bit fractional portion (MFRAC) and provides the means for
high-resolution frequency generation. The output frequency fOUT is
calculated by:
1
MFRAC + 0.5
(1)
f
= f
------------ MINT + ----------------------------------
OUT
XTAL
P N
18
2
The four configuration registers for the P, M (MINT & MFRAC) and N
dividers which are named Pn, MINTn, MFRACn and Nn with n = 0 to
3. “n” denominates one of the four possible configurations.
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IDT8N4QV01 REV G DATA SHEET
QUAD-FREQUENCY PROGRAMMABLE-VCXO
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC
Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
Inputs, VI
3.63V
-0.5V to VDD + 0.5V
10mA
Outputs, IO (SDATA)
Outputs, IO (LVDS)
Continuous Current
Surge Current
10mA
15mA
Package Thermal Impedance, JA
49.4C/W (0 mps)
-65C to 150C
Storage Temperature, TSTG
DC Electrical Characteristics
Table 5A. Power Supply DC Characteristics, V = 3.3V 5ꢀ, T = -40°C to 85°C
DD A
Symbol
VDD
Parameter
Test Conditions
Minimum
Typical
Maximum
3.465
Units
V
Power Supply Voltage
Power Supply Current
3.135
3.3
IDD
160
mA
Table 5B. Power Supply DC Characteristics, V = 2.5V 5ꢀ, T = -40°C to 85°C
DD A
Symbol
VDD
Parameter
Test Conditions
Minimum
Typical
Maximum
2.625
Units
V
Power Supply Voltage
Power Supply Current
2.375
2.5
IDD
155
mA
IDT8N4QV01GCD REVISION A MARCH 11, 2014
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IDT8N4QV01 REV G DATA SHEET
QUAD-FREQUENCY PROGRAMMABLE-VCXO
Table 5C. LVCMOS/LVTTL DC Characteristic, V = 3.3V 5ꢀ or 2.5V 5ꢀ, T = -40°C to 85°C
DD A
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
VCC +0.3
VCC +0.3
0.5
Units
V
SEL [1:0], OE
SEL [1:0], OE
SEL [1:0]
OE
VCC =3.3V +5ꢀ
VCC =2.5V +5ꢀ
VCC =3.3V +5ꢀ
VCC =3.3V +5ꢀ
VCC =2.5V +5ꢀ
VCC =2.5V +5ꢀ
1.7
1.7
Input High
Voltage
VIH
V
-0.3
-0.3
-0.3
-0.3
V
0.8
V
Input Low
Voltage
VIL
SEL [1:0]
OE
0.5
V
0.8
V
OE
10
µA
SDATA,
SCLK
Input High
Current
VDD = VIN = 3.465V or 2.625V
VDD = VIN = 3.465V or 2.625V
5
µA
IIH
FSEL0,
FSEL1
150
µA
µA
µA
OE
-500
-150
SDATA,
SCLK
VDD = 3.465V or 2.625V,
Input Low
Current
IIL
V
IN = 0V
FSEL0,
FSEL1
VDD = 3.465V or 2.625V,
-5
µA
V
IN = 0V
Table 5D. LVDS DC Characteristics, V = 3.3V 5ꢀ or 2.5V 5ꢀ, T = -40°C to 85°C
DD A
Symbol
VOD
Parameter
Test Conditions
Minimum
Typical
Maximum
454
Units
mV
mV
V
Differential Output Voltage
VOD Magnitude Change
Offset Voltage
247
350
VOD
VOS
50
1.0
1.20
1.375
50
VOS
VOS Magnitude Change
mV
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IDT8N4QV01 REV G DATA SHEET
QUAD-FREQUENCY PROGRAMMABLE-VCXO
AC Electrical Characteristics
Table 6A. VCXO Control Voltage Input (V ) Characterisitics, VDD = 3.3V 5ꢀ or 2.5V 5ꢀ, TA = -40°C to 85°C
C
Symbol
Parameter
Test Conditions
Minimum
Typical
7.57
Maximum
Units
ppm/V
ppm/V
ADC_GAIN[5:0] = 000001
ADC_GAIN[5:0] = 000010
15.15
Oscillator Gain, NOTE 1, 2, 3
2·12.5 ÷ VDD
ADC_GAIN
ADC_GAIN[5:0] = XXXXXX
ppm/V
VDD = 3.3V
ADC_GAIN[5:0] = 111110
ADC_GAIN[5:0] = 111111
ADC_GAIN[5:0] = 000001
ADC_GAIN[5:0] = 000010
469.69
477.27
10
ppm/V
ppm/V
ppm/V
ppm/V
KV
20
Oscillator Gain, NOTE 1, 2, 3
VDD = 2.5V
2·12.5 ÷ VDD
ADC_GAIN
ADC_GAIN[5:0] = XXXXXX
ppm/V
ADC_GAIN[5:0] = 111110
ADC_GAIN[5:0] = 111111
BSL Variation; NOTE 4
Incremental; NOTE 5
620
630
1
ppm/V
ppm/V
ꢀ
-5
+5
LVC
Control Voltage Linearity
-10
5
+10
ꢀ
BW
Modulation Bandwidth
VC Input Impedance
Nominal Control Voltage
100
500
VDD÷2
kHz
k
ZVC
VCNOM
V
Control Voltage Tuning
Range; NOTE 4
VC
0
VDD
V
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: VC = 0V to VDD.
NOTE 2: Nominal oscillator gain: Pull range divided by the control voltage tuning range of 3.3V.
E.g. for ADC_GAIN[6:0] = 00.0001 the pull range is 12.5ppm, resulting in an oscillator gain of 2 * 12.5ppm ÷ 3.3V = 7.57ppm/V.
NOTE 3: For best phase noise performance, use the lowest KV that meets the requirements of the application.
NOTE 4: BSL = Best Straight Line Fit: Variation of the output frequency vs. control voltage VC, in percent. VC ranges from 10ꢀ to 90ꢀ VDD
.
NOTE 5: Incremental slope is defined as the linearity in percent of the raw data (not relative to BSL) from 10ꢀ to 90ꢀ VDD
.
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QUAD-FREQUENCY PROGRAMMABLE-VCXO
Table 6B. AC Characteristics, V = 3.3V 5ꢀ or 2.5V 5ꢀ, T = -40°C to 85°C
DD A
Symbol
Parameter
Test Conditions
Minimum
15.476
975
Typical
Maximum
Units
MHz
MHz
MHz
ppm
ppm
ppm
ppm
ppm
ppm
ppm
ppm
ppm
ps
Output Divider, N = 3 to126
Output Divider, N = 2
866.67
1,300
2600
10
fOUT
Output Frequency Q, nQ
fVCO
fI
VCO Frequency
Initial Accuracy
1980
Measured at 25°C
Option code = A or B
100
50
fS
fA
fT
Temperature Stability
Aging
Option code = E or F
Option code = K or L
20
Frequency drift over 10 year life
Frequency drift over 15 year life
Option code A or B (10 year life)
Option code E or F (10 year life)
Option code K or L (10 year life)
3
5
113
63
Total Stability
33
tjit(cc)
Cycle-to-Cycle Jitter; NOTE 1
Period Jitter; NOTE 1
20
tjit(per)
2.85
4
ps
17MHz fOUT 1300MHz,
NOTE 2,3,4
RMS Phase Jitter (Random)
Fractional PLL feedback and
fXTAL=114.285MHz (0xxx order
codes)
0.475
0.990
0.757
ps
tjit(Ø)
f
OUT 156.25MHz, NOTE 2, 3, 4
OUT 156.25MHz, NOTE 2, 3, 5
0.494
0.594
ps
ps
f
Single-side band phase noise,
100 Hz from Carrier
N(100)
N(1k)
156.25MHz
156.25MHz
156.25MHz
156.25MHz
156.25MHz
156.25MHz
-73.8
-99.8
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
db
Single-side band phase noise,
1kHz from Carrier
Single-side band phase noise,
10kHz from Carrier
N(10k)
N(100k)
N(1M)
N(10M)
PSNR
-126.1
-129.3
-140.3
-144.3
-54
Single-side band phase noise,
100kHz from Carrier
Single-side band phase noise,
1MHz from Carrier
Single-side band phase noise,
10MHz from Carrier
50mV Sinusoidal Noise
1kHz - 50MHz
Power Supply Noise Rejection
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ
100
45
425
55
ps
ꢀ
tOSC
Oscillator Start-Up Time
20
ms
Output Frequency Settling Time
after FSEL0 and FSEL1 Values
are Changed
tSET
470
µs
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions. All AC parameters are characterized with P=1 and pull range 250 ppm.
NOTE: XTAL parameters (initial accuracy, temperature stability, aging and total stability) are guaranteed by manufacturing.
NOTE 1: This parameter is defined in accordance with JEDEC standard 65.
NOTE 2: Please refer to the phase noise plots.
NOTES continued on next page.
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QUAD-FREQUENCY PROGRAMMABLE-VCXO
NOTE 3: Please see the FemtoClock NG Ceramic 5x7 Modules Programming guide for more information on finding the optimum configuration
for phase noise.
NOTE 4: Integration range: 12kHz-20MHz.
NOTE 5: Integration range: 1kHz-40MHz.
Typical Phase Noise at 156.25MHz (12kHz - 20MHz)
Offset Frequency (Hz)
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QUAD-FREQUENCY PROGRAMMABLE-VCXO
Parameter Measurement Information
SCOPE
SCOPE
Q
Q
VDD
VDD
3.3V 5ꢀ
POWER SUPPL
2.5V 5ꢀ
POWER SUPPL
+
Float GND
+
Float GND
nQ
nQ
3.3V LVDS Output Load AC Test Circuit
2.5V LVDS Output Load AC Test Circuit
VOH
VREF
VOL
1σ contains 68.26ꢀ of all measurements
2σ contains 95.4ꢀ of all measurements
3σ contains 99.73ꢀ of all measurements
4σ contains 99.99366ꢀ of all measurements
6σ contains (100-1.973x10-7)ꢀ of all measurements
Histogram
Reference Point
(Trigger Edge)
Mean Period
(First edge after trigger)
RMS Phase Jitter
Period Jitter
nQ
nQ
Q
Q
tPW
tPERIOD
➤
➤
tcycle n
tcycle n+1
➤
➤
tPW
tjit(cc) = tcycle n tcycle n+1
odc =
x 100ꢀ
1000 Cycles
tPERIOD
Output Duty Cycle/Pulse Width/Period
Cycle-to-Cycle Jitter
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Parameter Measurement Information (continued)
VDD
MIN
nQ
80ꢀ
VDD
80ꢀ
VOD
20ꢀ
Correct Frequency
20ꢀ
Output
Q
tF
tR
➤
Not to Scale
tstartup
➤
Output Rise/Fall Time
Start-Up
Differential Output Voltage Setup
Offset Voltage Setup
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QUAD-FREQUENCY PROGRAMMABLE-VCXO
Applications Information
Recommendations for Unused Input Pins
Inputs:
LVCMOS Select Pins
All control pins have internal pulldowns; additional resistance is not
required but can be added for additional protection. A 1k resistor
can be used.
LVDS Driver Termination
For a general LVDS interface, the recommended value for the
termination impedance (ZT) is between 90 and 132. The actual
value should be selected to match the differential impedance (Z0) of
your transmission line. A typical point-to-point LVDS design uses a
100 parallel resistor at the receiver and a 100 differential
transmission-line environment. In order to avoid any
standard termination schematic as shown in Figure 1A can be used
with either type of output structure. Figure 1B, which can also be
used with both output types, is an optional termination with center tap
capacitance to help filter common mode noise. The capacitor value
should be approximately 50pF. If using a non-standard termination, it
is recommended to contact IDT and confirm if the output structure is
current source or voltage source type. In addition, since these
outputs are LVDS compatible, the input receiver’s amplitude and
common-mode input range should be verified for compatibility with
the output.
transmission-line reflection issues, the components should be
surface mounted and must be placed as close to the receiver as
possible. IDT offers a full line of LVDS compliant devices with two
types of output structures: current source and voltage source. The
Z Z
O
T
LVDS
Receiver
LVDS
Driver
Z
T
Figure 1A. Standard Termination
Z
T
Z Z
O
T
LVDS
Receiver
LVDS
Driver
2
Z
C
T
2
Figure 1B. Optional Termination
LVDS Termination
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Power Considerations
This section provides information on power dissipation and junction temperature for the IDT8N4QV01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the IDT8N4QV01 is the sum of the core power plus the power dissipated in the load(s). The following is the
power dissipation for VDD = 3.3V + 5ꢀ = 3.465V, which gives worst case results.
•
Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 160mA = 554.4mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 49.4°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.554W * 49.4°C/W = 112.4°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 7. Thermal Resistance for 10 Lead Ceramic 5mm x 7mm Package, Forced Convection
JA
JA by Velocity
Meters per Second
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
49.4°C/W
44.2°C/W
41°C/W
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Reliability Information
Table 8. vs. Air Flow Table for a 10-lead Ceramic 5mm x 7mm Package
JA
JA vs. Air Flow
Meters per Second
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
49.4°C/W
44.2°C/W
41°C/W
Transistor Count
The transistor count for IDT8N4QV01 is: 47,372
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Package Outline and Package Dimensions
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Ordering Information for FemtoClock NG Ceramic-Package XO and VCXO Products
The programmable VCXO and XO devices support a variety of
devices options such as the output type, number of default frequen-
cies, internal crystal frequency, power supply voltage, ambient
temperature range and the frequency accuracy. The device options,
default frequencies and default VCXO pull range must be specified at
the time of order and are programmed by IDT before the shipment.
The table below specifies the available order codes, including the
device options and default frequency configurations. Example part
number: the order code 8N3QV01FG-0001CDI specifies a
contains a 114.285MHz internal crystal as frequency source,
industrial temperature range, a lead-free (6/6 RoHS) 10-lead ceramic
5mm x 7mm x 1.55mm package and is factory-programmed to the
default frequencies of 100, 122.88, 125 and 156.25MHz and to the
VCXO pull range of min. 100 ppm.
Other default frequencies and order codes are available from IDT on
request. For more information on available default frequencies, see
the FemtoClock NG Ceramic-Package XO and VCXO Ordering
Product Information document.
programmable, quad default-frequency VCXO with a voltage supply
of 2.5V, a LVPECL output, a 50 ppm crystal frequency accuracy,
Part/Order Number
8N X X XXX X X - dddd XX X
X
Shipping Package
8: Tape & Reel
(no letter): Tray
FemtoClock NG
I/O Identifier
Ambient Temperature Range
“I”: Industrial: (TA = -40°C to 85°C)
(no letter) : (TA = 0°C to 70°C)
0: LVCMOS
3: LVPECL
4: LVDS
Package Code
CD: Lead-Free, 6/10-lead ceramic 5mm x 7mm x 1.55mm
Number of Default Frequencies
S: 1: Single
D: 2: Dual
Q: 4: Quad
Default-Frequency and VCXO Pull Range
See document FemtoClock NG Ceramic-Package XO andVCXO
Ordering Product Information.
dddd
f
XTAL (MHz) PLL feedback
Use for
VCXO, XO
XO
Part Number
0000 to 0999
1000 to 1999
2000 to 2999
114.285
Fractional
Integer
OE fct. at
Function #pins
pin
100.000
Fractional
XO
001
003
V01
V03
V75
V76
V85
085
270
271
272
273
XO
XO
10
10
10
10
6
OE@2
OE@1
OE@2
OE@1
OE@2
nOE@2
—
Last digit = L: configuration pre-programmed and not changeable
VCXO
VCXO
VCXO
VCXO
VCXO
XO
Die Revision
G (opt. 207)
6
6
Option Code (Supply Voltage and Frequency-Stability)
6
OE@1
OE@1
OE@2
nOE@2
nOE@1
A: VCC = 3.3V 5ꢀ, 100ppm
B: VCC = 2.5V 5ꢀ, 100ppm
XO
6
XO
6
E: VCC = 3.3V 5ꢀ,
F: VCC = 2.5V 5ꢀ,
K: VCC = 3.3V 5ꢀ,
L: VCC = 2.5V 5ꢀ,
50ppm
50ppm
20ppm
20ppm
XO
6
XO
6
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Table 9. Device Marking
Industrial Temperature Range (TA = -40°C to 85°C)
Commercial Temperature Range (TA = 0°C to 70°C)
IDT8N4xV01yG-
ddddCDI
IDT8N4xV01yG-
ddddCD
x = Number of Default Frequencies, y = Option Code, dddd=Default-Frequency and VCXO Pull Range
Marking
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Revision History Sheet
Rev
Table
Page
Description of Change
Date
A
T9
18
Table 9 Device Marking, corrected marking.
3/6/12
T1
2
8
Deleted “(see table 3C)” from the first table row, description column.
NOTE 2; Deleted “from table 3C”.
A
3/13/14
T6A
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Fax: 408-284-2775
www.IDT.com/go/contactIDT
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document,
including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not
guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the
suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any
license under intellectual property rights of IDT or any third parties.
IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to signifi-
cantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third
party owners.
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