8N0QV01LH-0036CDI8 [IDT]
LVCMOS Output Clock Oscillator;
| 型号： | 8N0QV01LH-0036CDI8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | LVCMOS Output Clock Oscillator 振荡器 |
| 文件： | 总19页 (文件大小：452K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Quad-Frequency
Programmable VCXO
IDT8N0QV01 Rev H
DATASHEET
General Description
Features
The 8N0QV01 is a Quad-Frequency Programmable VCXO with very
flexible frequency and pull-range programming capabilities. The
device uses IDT’s Fourth Generation FemtoClock® NG technology
for an optimum of high clock frequency and low phase noise
performance. The device accepts 2.5V or 3.3V supply and is
packaged in a small, lead-free (RoHS 6) 10-lead ceramic 5mm x
7mm x 1.55mm package.
• Fourth generation FemtoClock® NG technology
• Programmable clock output frequency from
15.476MHz to 260MHz
• Four power-up default frequencies (see part number order codes),
re-programmable by I2C
• I2C programming interface for the output clock frequency, APR
and internal PLL control registers
Besides the four default power-up frequencies set by the FSEL0 and
FSEL1 pins, the 8N0QV01 can be programmed via the I2C interface
to any output clock frequency between 15.476MHz to 260MHz to a
very high degree of precision with a frequency step size of 435.9Hz
÷N (N: PLL post divider). Since the FSEL0 and FSEL1 pins are
mapped to four independent PLL, P, M and N divider registers (P,
MINT, MFRAC and N), reprogramming those registers to other
frequencies under control of FSEL0 and FSEL1 is supported. The
extended temperature range supports wireless infrastructure,
telecommunication and networking end equipment requirements.
• Frequency programming resolution is 435.9Hz ÷N
• Absolute pull-range (APR) programmable from
2.5 to 727.5ppm
• One 2.5V, 3.3V LVCMOS clock output
• Two control inputs for the power-up default frequency
• LVCMOS/LVTTL compatible control inputs
• RMS phase jitter @ 156.25MHz
(12kHz - 20MHz): 0.635ps (typical)
• RMS phase jitter @ 156.25MHz
(1kHz - 40MHz): 0.850ps (typical)
• 2.5V or 3.3V supply voltage modes
• -40°C to 85°C ambient operating temperature
• Lead-free (RoHS 6) packaging
Block Diagram
Pin Assignment
FemtoClock® NG
PFD
÷P
OSC
&
÷N
Q
VCO
10
9
5
LPF
1950-2600MHz
VC
1
8
6
VDD
Q
114.285 MHz
GND
3
÷MINT, MFRAC
4
2
A/D
VC
7
7
25
Pulldown
Pulldown
FSEL1
FSEL0
IDT8N0QV01 Rev H
10-lead ceramic 5mm x 7mm x 1.55mm
package body
Configuration Register (ROM)
(Frequency, APR, Polarity)
Pullup
Pullup
SCLK
SDATA
I2C Control
CD Package
Top View
Pullup
OE
IDT8N0QV01HCD REVISION A MARCH 13, 2014
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©2013 Integrated Device Technology, Inc.
IDT8N0QV01 Rev H Data Sheet
QUAD-FREQUENCY PROGRAMMABLE-VCXO
Block Diagram with Programming Registers
Output Divider N
FemtoClock® NG
VCO
1950-2600MHz
PFD
&
LPF
÷P
OSC
114.285MHz
÷ N
2
7
Feedback Divider M (25 Bit)
MINT
MFRAC
(7 bits)
(18 bits)
A/D
VC
7
18
7
34
Programming Registers
ADC_GAIN
ADC_POL
1 bit
41
I2C Control
2
I C:
Def:
6 bits
6 bits
P0
1 bit
7
7
MINT0 MFRAC0
N0
2
I C:
2 bits 7 bits
2 bits 7 bits
18 bits
18 bits
7 bits
7 bits
N1
00
Def:
30
30
30
30
34
34
34
34
P1
MINT1 MFRAC1
2
I C:
2 bits 7 bits
2 bits 7 bits
18 bits
18 bits
7 bits
7 bits
N2
01
Def:
P2
MINT2 MFRAC2
34
2
Pullup
Pullup
I C:
2 bits 7 bits
2 bits 7 bits
18 bits
18 bits
7 bits
7 bits
N3
SCLK
10
Def:
SDATA
P3
MINT3 MFRAC3
2
I C:
2 bits 7 bits
2 bits 7 bits
18 bits
18 bits
7 bits
7 bits
11
Def:
Pulldown, Pulldown
Pullup
FSEL[1:0]
OE
Def: Power-up default register setting for I2C registers
ADC_GAINn, ADC_POL, Pn, MINTn, MFRACn and Nn
IDT8N0QV01HCD REVISION A MARCH 13, 2014
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©2013 Integrated Device Technology, Inc.
IDT8N0QV01 Rev H Data Sheet
QUAD-FREQUENCY PROGRAMMABLE-VCXO
Pin Description and Characteristics
Table 1. Pin Descriptions
Number
Name
Type
Description
VCXO Control Voltage. The control voltage versus frequency
characteristics are set by the ADC_GAIN[5:0] register bits.
1
VC
Input
Output enable pin. See Table 3B for function. LVCMOS/LVTTL interface
levels.
2
3
OE
Input
Pullup
GND
Power
Power supply ground.
Default frequency select pins. LVCMOS/LVTTL interface levels. Refer to
the FemtoClock NG Ceramic-Package XO and VCXO Ordering Product
Information document for default frequency order codes.
FSEL1,
FSEL0
5, 4
Input
Pulldown
6
7
Output
Clock output. LVCMOS/LVTTL interface levels.
Do not use. Do not connect.
Q
DNU
VDD
8
Power
Input
Input
Positive power supply.
I2C Data Input. LVCMOS/LVTTL interface levels.
I2C Clock Input. LVCMOS/LVTTL interface levels.
9
Pullup
Pullup
SDATA
SCLK
10
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
Test Conditions
FSEL[1:0], SDATA, SCLK, OE
VC
Minimum
Typical
3.5
Maximum
Units
pF
CIN
Input Capacitance
10
pF
Power Dissipation
Capacitance
CPD
VDD = 3.465V or 2.625V
8
pF
RPULLUP
Input Pullup Resistor
50
50
15
19
k
k
RPULLDOWN
Input Pulldown Resistor
VDD = 3.3V
VDD = 2.5V
ROUT
Output Impedance
Q
IDT8N0QV01HCD REVISION A MARCH 13, 2014
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©2013 Integrated Device Technology, Inc.
IDT8N0QV01 Rev H Data Sheet
QUAD-FREQUENCY PROGRAMMABLE-VCXO
Function Tables
Table 3A. Default Frequency Selection
Input
FSEL1
FSEL0
Operation
0 (default)
0 (default)
Default frequency 0.
Default frequency 1.
Default frequency 2.
Default frequency 3.
0
1
1
1
0
1
NOTE: The default frequency is the output frequency after power-up. One of four default frequencies is selected by FSEL[1:0]. See
programming section for details.
Table 3B. OE Configuration
Input
OE
0
Output Enable
Output Q are in high-impedance state.
Outputs are enabled.
1 (default)
NOTE: OE is an asynchronous control.
IDT8N0QV01HCD REVISION A MARCH 13, 2014
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©2013 Integrated Device Technology, Inc.
IDT8N0QV01 Rev H Data Sheet
QUAD-FREQUENCY PROGRAMMABLE-VCXO
The four configuration registers for the P, M (MINT & MFRAC) and N
dividers which are named Pn, MINTn, MFRACn and Nn with n = 0 to
3. “n” denominates one of the four possible configurations.
Principles of Operation
The block diagram consists of the internal 3rd overtone crystal and
oscillator which provide the reference clock fXTAL of 114.285MHz.
The PLL includes the FemtoClock NGVCO along with the pre-divider
(P), the feedback divider (M) and the post divider (N). The P, M, and
N dividers determine the output frequency based on the fXTAL
reference and must be configured correctly for proper operation. The
feedback divider is fractional supporting a huge number of output
frequencies. The configuration of the feedback divider to integer-only
values results in an improved output phase noise characteristics at
the expense of the range of output frequencies. In addition, internal
registers are used to hold up to four different factory pre-set P, M, and
N configuration settings. These default pre-sets are stored in the I2C
registers at power-up. Each configuration is selected via the
FSEL[1:0] pins and can be read back using the SCLK and SDATA
pins.
As identified previously, the configurations of P, M (MINT & MFRAC)
and N divider settings are stored the I2C register, and the
configuration loaded at power-up is determined by the FSEL[1:0]
pins.
Table 4. Frequency Selection
Input
FSEL1
FSEL0
Selects
Register
0 (def.)
0 (def.)
Frequency 0
Frequency 1
Frequency 2
Frequency 3
P0, MINT0, MFRAC0, N0
P1, MINT1, MFRAC1, N1
P2, MINT2, MFRAC2, N2
P3, MINT3, MFRAC3, N3
0
1
1
1
0
1
The user may choose to operate the device at an output frequency
different than that set by the factory. After power-up, the user may
write new P, N and M settings into one or more of the four
configuration registers and then use the FSEL[1:0] pins to select the
newly programmed configuration. Note that the I2C registers are
volatile and a power supply cycle will reload the pre-set factory
default conditions.
Frequency Configuration
An order code is assigned to each frequency and VCXO pull range
configuration programmed by the factory (default frequencies). For
available order codes, see the FemtoClock NG Ceramic-Package XO
and VCXO Ordering Product Information document.
If the user does choose to write a different P, M, and N configuration,
it is recommended to write to a configuration which is not currently
selected by FSEL[1:0] and then change to that configuration after the
I2C transaction has completed. Changing the FSEL[1:0] controls
results in an immediate change of the output frequency to the
selected register values. The P, M, and N frequency configurations
support an output frequency range 15.476MHz to 260MHz.
For more information and guidelines on programming of the device
for custom frequency configurations, programming for a specific
VCXO pull range, the available APR (absolute pull range), the
register description and the serial interface description, see the
FemtoClock NG Ceramic 5x7 Module Programming Guide.
The devices use the fractional feedback divider with a delta-sigma
modulator for noise shaping and robust frequency synthesis
capability. The relatively high reference frequency minimizes phase
noise generated by frequency multiplication and allows more efficient
shaping of noise by the delta-sigma modulator.
The output frequency is determined by the 2-bit pre-divider (P), the
feedback divider (M) and the 7-bit post divider (N). The feedback
divider (M) consists of both a 7-bit integer portion (MINT) and an
18-bit fractional portion (MFRAC) and provides the means for
high-resolution frequency generation. The output frequency fOUT is
calculated by:
1
MFRAC + 0.5
f
= f
------------ MINT + ------------------------------------- (1)
OUT
XTAL
P N
18
2
IDT8N0QV01HCD REVISION A MARCH 13, 2014
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©2013 Integrated Device Technology, Inc.
IDT8N0QV01 Rev H Data Sheet
QUAD-FREQUENCY PROGRAMMABLE-VCXO
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the DC Characteristics or
AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
Inputs, VI
3.6V
-0.5V to VDD + 0.5V
-0.5V to VDD + 0.5V
10mA
Outputs, IO (LVCMOS)
Outputs, IO (SDATA)
Package Thermal Impedance, JA
Storage Temperature, TSTG
49.4°C/W (mps)
-65°C to 150°C
DC Electrical Characteristics
Table 5A. Power Supply DC Characteristics, V = 3.3V 5%, T = -40°C to 85°C
DD
A
Symbol
VDD
Parameter
Test Conditions
Minimum
Typical
3.3
Maximum
3.465
Units
V
Supply Voltage
Power Supply Current
3.135
IDD
No Load, OE = Low
135
150
mA
Table 5B. Power Supply DC Characteristics, V = 2.5V 5%, T = -40°C to 85°C
DD
A
Symbol
VDD
Parameter
Test Conditions
Minimum
Typical
2.5
Maximum
2.625
Units
V
Supply Voltage
Power Supply Current
2.375
IDD
No Load, OE = Low
130
145
mA
IDT8N0QV01HCD REVISION A MARCH 13, 2014
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©2013 Integrated Device Technology, Inc.
IDT8N0QV01 Rev H Data Sheet
QUAD-FREQUENCY PROGRAMMABLE-VCXO
Table 5C. LVCMOS/LVTTL DC Characteristic, V = 3.3V 5% or 2.5V 5%, T = -40°C to 85°C
DD
A
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
OE, SCLK,
SDATA,
FSEL[1:0]
VDD = 3.3V
VDD = 2.5V
2
VDD+ 0.3
V
Input High
Voltage
VIH
1.7
-0.3
-0.3
VDD + 0.3
0.8
V
V
V
OE, SCLK,
SDATA,
FSEL[1:0]
VDD = 3.465V
Input Low
Voltage
VIL
VDD = 2.5V
0.7
OE,
V
DD = VIN = 3.465V or 2.625V
10
5
µA
µA
µA
Input High
Current
IIH
SDATA, SCLK
FSEL0, FSEL1
VDD = VIN = 3.465V or 2.625V
VDD = VIN = 3.465V or 2.625V
VDD = 3.465V or 2.625V,
150
OE
-500
-150
-5
µA
µA
µA
VIN = 0V
Input Low
Current
VDD = 3.465V or 2.625V,
IIL
SDATA, SCLK
FSEL0, FSEL1
VIN = 0V
VDD = 3.465V or 2.625V,
VIN = 0V
Output
High
Voltage
VDD = 3.465V
VDD = 2.625
2.4
1.7
V
V
VOH
Q
Q
OutputLow
Voltage
VOL
V
DD = 3.6V or 2.625
0.4
V
IDT8N0QV01HCD REVISION A MARCH 13, 2014
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©2013 Integrated Device Technology, Inc.
IDT8N0QV01 Rev H Data Sheet
QUAD-FREQUENCY PROGRAMMABLE-VCXO
AC Electrical Characteristics
Table 6A. AC Characteristics, V = 3.3V 5% or 2.5V 5%, T = -40°C to 85°C
DD
A
Symbol
fOUT
fI
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
MHz
ppm
ppm
ppm
ppm
ppm
ppm
ppm
ppm
ppm
ps
Output Frequency Q, nQ
Initial Accuracy
P = 1, N = 10...126
Measured at 25°C at Final Test
Option code = A or B
Option code = E or F
15.476
260
10
100
50
20
3
fS
fA
fT
Temperature Stability
Aging
Option code = K or L
Frequency drift over 10 year life
Frequency drift over 15 year life
Option code A or B (10 year life)
Option code E or F (10 year life)
Option code K or L (10 year life)
VDD = 3.3V
5
113
63
33
32
40
5
Total Stability
15
18
2.6
4
tjit(cc)
Cycle-to-Cycle Jitter; NOTE 1
Period Jitter; NOTE 1
VDD = 2.5V
ps
VDD = 3.3V
ps
tjit(per)
VDD = 2.5V
7
ps
17MHz fout 260MHz, Integration
Range: 12kHz - 20MHz, NOTE 3
0.70
0.64
0.85
-75
1.20
0.92
1.00
ps
156.25MHz, Integration Range:
12kHz - 20MHz; NOTE 2
tjit(Ø)
RMS Phase Jitter (Random)
ps
156.25MHz, Integration Range:
1kHz - 40MHz
ps
Single-side band phase noise,
100Hz from Carrier
N(100)
N(1k)
156.25MHz
156.25MHz
156.25MHz
156.25MHz
156.25MHz
156.25MHz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Single-side band phase noise,
1kHz from Carrier
-98
Single-side band phase noise,
10kHz from Carrier
N(10k)
N(100k)
N(1M)
N(10M)
-118
-127
-139
-143
Single-side band phase noise,
100kHz from Carrier
Single-side band phase noise,
1MHz from Carrier
Single-side band phase noise,
10MHz from Carrier
VDD = 3.3V, 20% to 80%
VDD = 2.5V, 20% to 80%
150
150
45
425
500
50
700
800
55
ps
ps
%
t
R / tF
Output Rise/Fall Time
odc
Output Duty Cycle
tOSC
Oscillator Start-Up Time
20
ms
Output frequency settling time after
FSEL0 and FSEL1 values are
changed
tSET
1
ms
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: All AC parameters are characterized with P = 1.
NOTES continued on next page.
IDT8N0QV01HCD REVISION A MARCH 13, 2014
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©2013 Integrated Device Technology, Inc.
IDT8N0QV01 Rev H Data Sheet
QUAD-FREQUENCY PROGRAMMABLE-VCXO
NOTE: Please see the FemtoClock Ceramic 5x7 Modules Programming Guide for more information on PLL feedback modes and the optimum
configuration for phase noise.
NOTE 1: This parameter is defined in accordance with JEDEC standard 65.
NOTE 2: Please refer to the phase noise plots.
NOTE 3: Applies to output frequencies: 17MHz, 19.44MHz, 25MHz, 33.33MHz, 75MHz, 77.76MHz, 100MHz, 106.25MHz, 122.88MHz,
125MHz, 150MHz, 155.52MHz, 156.25MHz, 161.132MHz, 175MHz, 187.5MHz, 200MHz, 212.5MHz, 250MHz and 260MHz.
Table 6B. VCXO Control Voltage Input (V ) Characterisitics,
C
Symbol
Parameter
Test Conditions
VDD = 3.3V
Minimum
Typical
Maximum Units
7.57
10
477.27
630
ppm/V
ppm/V
%
KV
Oscillator Gain, NOTE 1, 2, 3
VDD = 2.5V
LVC
Control Voltage Linearity; NOTE 4
Modulation Bandwidth
BSL Variation
-5
0.4
100
+5
BW
kHz
k
ZVC
VC Input Impedance
500
VCNOM
Nominal Control Voltage
VDD/2
V
Control Voltage Tuning Range;
NOTE 4
VDD = 3.3V 5% or 2.5V 5%,
TA = -40°C to 85°C
VC
0
VDD
V
NOTE 1: VC = 0V to VDD. Oscillator gain is programmed by IDT. Gain = (25 · n) ÷ VCC and is in the range of n=1 to n = 63.
NOTE 2: Nominal oscillator gain: Please refer to the FemtoClock NG Ceramic 5x7 Module Programming Guide document.
NOTE 3: For best phase noise performance, use the lowest KV that meets the requirements of the application.
NOTE 4: BSL = Best Straight Line Fit: Variation of the output frequency vs. control voltage VC, in percent. VC ranges from 10% to 90% VDD
.
IDT8N0QV01HCD REVISION A MARCH 13, 2014
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©2013 Integrated Device Technology, Inc.
IDT8N0QV01 Rev H Data Sheet
QUAD-FREQUENCY PROGRAMMABLE-VCXO
Typical Phase Noise at 156.25MHz (12kHz - 20MHz)
Offset Frequency (Hz)
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©2013 Integrated Device Technology, Inc.
IDT8N0QV01 Rev H Data Sheet
QUAD-FREQUENCY PROGRAMMABLE-VCXO
Parameter Measurement Information
1.65V 5%
1.25V 5%
SCOPE
SCOPE
VDD
VDD
Q
Q
LVCMOS
LVCMOS
GND
GND
-1.25V 5%
-1.65V 5%
3.3V LVCMOS Output Load Test Circuit
2.5V LVCMOS Output Load Test Circuit
80%
80%
tR
20%
20%
Q
tF
RMS Phase Jitter
Output Rise/Fall Time
Q
Q
➤
➤
tcycle n
tcycle n+1
➤
➤
tjit(cc) = tcycle n tcycle n+1
1000 Cycles
Output Duty Cycle/Pulse Width/Period
Cycle-to-Cycle Jitter
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©2013 Integrated Device Technology, Inc.
IDT8N0QV01 Rev H Data Sheet
QUAD-FREQUENCY PROGRAMMABLE-VCXO
Parameter Measurement Information, continued
VOH
VREF
VOL
1σ contains 68.26% of all measurements
2σ contains 95.4% of all measurements
3σ contains 99.73% of all measurements
4σ contains 99.99366% of all measurements
6σ contains (100-1.973x10-7)% of all measurements
Histogram
Reference Point
(Trigger Edge)
Mean Period
(First edge after trigger)
Period Jitter
Applications Information
Recommendations for Unused Input Pins
Inputs:
LVCMOS Select Pins
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional protection.
A 1k resistor can be used.
IDT8N0QV01HCD REVISION A MARCH 13, 2014
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©2013 Integrated Device Technology, Inc.
IDT8N0QV01 Rev H Data Sheet
QUAD-FREQUENCY PROGRAMMABLE-VCXO
Schematic Example
Figure 1 shows an example 8N0QV01application schematic in which
the device is operated at VDD = +3.3V. The schematic example
focuses on functional connections and is intended as an example
only and may not represent the exact user configuration. Refer to the
pin description and functional tables in the datasheet to ensure the
logic control inputs are properly set. For example OE and FSEL[1:0]
can be configured from an FPGA instead of set with pull up and pull
down resistors as shown.
achieve the best possible filtering, it is recommended that the
placement of the filter components be on the device side of the PCB
as close to the power pins as possible. If space is limited, the 0.1µF
capacitor on the VDD pin must be placed on the device side with
direct return to the ground plane though vias. The remaining filter
components can be on the opposite side of the PCB.
Power supply filter component recommendations are a general
guideline to be used for reducing external noise from coupling into
the devices. The filter performance is designed for a wide range of
noise frequencies. This low-pass filter starts to attenuate noise at
approximately 10kHz. If a specific frequency noise component is
known, such as switching power supplies frequencies, it is
recommended that component values be adjusted and if required,
additional filtering be added. Additionally, good general design
practices for power plane voltage stability suggests adding bulk
capacitance in the local area of all devices.
The 8N0QV01 is not a self contained part; it requires pairing with a
PLL. The two connections necessary to be made to the PLL are VC,
the analog control voltage that sets the center frequency of the
VCXO, and Q, which is the oscillator output. VC is the analog output
of the PLL low pass loop filter that serves to remove noise from the
phase detector error output.
As with any high speed analog circuitry, the power supply pins are
vulnerable to random noise, so to achieve optimum jitter performance
isolation of the VDD pin from the power supply is required. In order to
Figure 1. IDT8N0QV01 Schematic Example
IDT8N0QV01HCD REVISION A MARCH 13, 2014
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©2013 Integrated Device Technology, Inc.
IDT8N0QV01 Rev H Data Sheet
QUAD-FREQUENCY PROGRAMMABLE-VCXO
Power Considerations
This section provides information on power dissipation and junction temperature for the IDT8N0QV01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the IDT8N0QV01 is the sum of the core power plus the power dissipation in the load(s). The following is the
power dissipation for VDD = 3.3V +5% = 3.465V, which gives worst case results.
•
Power (core)MAX = VDD_MAX * IDD = 3.465V * 150mA = 519.8mW
Total Static Power:
= Power (core)MAX = 519.8mW
Dynamic Power Dissipation at FOUT (max)
Total Power (FOUT_MAX) = [(CPD * N) * Frequency * (VDD)2] = [(8pF *1) * 260MHz * (3.465V)2] = 24.97mW
Total Power
= Static Power + Dynamic Power Dissipation
= 519.8mW + 24.97mW
= 544.77mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 49.4°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.545W *49.4°C/W = 112°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 7. Thermal Resistance for a 10-lead Ceramic 5mm x 7mm Package, Forced Convection
JA
JA by Velocity
0
Meters per Second
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
49.4°C/W
44.2°C/W
41.0°C/W
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Reliability Information
Table 8. vs. Air Flow Table for a 10-lead Ceramic 5mm x 7mm Package
JA
JA vs. Air Flow
Meters per Second
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
49.4°C/W
44.2°C/W
41.0°C/W
Transistor Count
The transistor count for IDT8N0QV01 is: 47,302
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Package Outline and Package Dimensions
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Table 9. Device Marking
Industrial Temperature Range (TA = -40°C to 85°C)
Commercial Temperature Range (TA = 0°C to 70°C)
IDT8N0QV01yH-
ddddCDI
IDT8N0QV01yH-
ddddCD
Marking
y = Option Code, dddd=Default-Frequency and VCXO Pull Range
NOTE: For available order codes, see the FemtoClock NG Ceramic-Package XO and VCXO Ordering Product Information document.
For more information and guidelines on programming of the device for custom frequency configurations, programming for a specific VCXO pull
range, the available APR (absolute pull range), the register description and the serial interface description, see the FemtoClock NG
Ceramic 5x7 Module Programming Guide.
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Revision History Sheet
Rev
Table
Page
Description of Change
Date
T1
3
first row: deleted '(see Table 3C).'
forth row: replaced description.
6A
6B
8
9
Deleted NOTE 2 from RMS Phase Jitter. Added 'NOTE 2' to 156.25MHz.
Note 2: Added 'Please refer to the FemtoClock NG Ceramic 5x7 Module Programming
Guide document.'
A
3/14/2014
14
Power Considerations. Changed Dynamic Power Dissipation from 2.5mW to 24.97mW
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