8P34S2108NLGI_技术文档

Dual 1:8 LVDS Output 1.8V Fanout Buffer

Features

8P34S2108

Datasheet

Description

▪ Dual 1:8 low skew, low additive jitter LVDS fanout buffers

The 8P34S2108 is a high-performance, low-power, differential

dual 1:8 LVDS output 1.8V fanout buffer. The device is designed

for the fanout of high-frequency, very low additive phase-noise

clock and data signals. Two independent buffer channels are

available, each channel has two low skew outputs. High isolation

between channels minimizes noise coupling. AC characteristics

such as propagation delay are matched between channels.

Guaranteed output-to-output and part-to-part skew characteristics

make the 8P34S2108 ideal for those clock distribution

▪ Matched AC characteristics across both channels

▪ High isolation between channels

▪ Low power consumption

▪ Both differential CLKA, nCLKA and CLKB, nCLKB inputs

accept LVDS, LVPECL and single-ended LVCMOS levels

▪ Maximum input clock frequency: 2GHz

▪ Output amplitudes: 350mV, 500mV (selectable)

▪ Output bank skew: 10ps typical

applications demanding well-defined performance and

repeatability. The device is characterized to operate from a 1.8V

power supply. The integrated bias voltage references enable easy

interfacing AC-coupled signals to the device inputs.

▪ Output skew: 20ps typical

▪ Low additive phase jitter, RMS: 45fs typical

(f_REF= 156.25MHz, 12kHz - 20MHz)

Block Diagram

▪ Full 1.8V supply voltage mode

QA0

nQA0

▪ Device current consumption (I_DD): 280mA typical

▪ Lead-free (RoHS 6), 48-lead VFQFN packaging

▪ -40°C to 85°C ambient operating temperature

▪ Supports case temperature up to 105°C

QA1

nQA1

QA2

VDDA

nQA2

51k

QA3

nQA3

CLKA

nCLKA

QA4

nQA4

51k

QA5

nQA5

QA6

VDDA

Voltage

Reference A

nQA6

VREFA

SELAA

51k

QA7

nQA7

QB0

nQB0

QB1

nQB1

QB2

nQB2

VDDB

51k

QB3

nQB3

CLKB

nCLKB

QB4

nQB4

51k

QB5

nQB5

Voltage

Reference B

VREFB

SELAB

VDDB

QB6

nQB6

51k

QB7

nQB7

8P34S2108 transistor count: 1113

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8P34S2108 Datasheet

Pin Assignments

Figure 1. Pin Assignments for 7mm x 7mm VFQFN Package – Top View

36 35 34 33 32 31 30 29 28 27 26 25

24

23

22

21

20

37

38

39

40

41

V_DDQA

nQA4

QA4

V_DDQB

QB3

nQB3

QB4

nQA3

QA3

nQB4

19 nQA2

QB5 42

8P34S2108

18

17

16

15

14

13

43

44

45

46

47

48

QA2

nQB5

QB6

nQA1

QA1

nQB6

QB7

nQA0

QA0

nQB7

V_DDQB

V_DDQA

1

2

3

4

5

6

7

8

9

10 11 12

Pin Descriptions

Table 1. Pin Descriptions^[a]

Number

Name

Type

Description

1

2

GND

SELAB

CLKB

nCLKB

VREFB

V_DDB

Power

Power supply ground.

Input [PU]

Input [PD]

Input [PD/PU]

Output

Control input. Output amplitude select for channel B.

Non-inverting differential clock/data input for channel B.

3

4

Inverting differential clock/data input for channel B.

5

Bias voltage reference for the CLKB, nCLKB input pairs.

6

Power

Power supply pins for the core and inputs of channel B.

7

V_DDA

Power

Power supply pins for the core and inputs of channel A.

Bias voltage reference for the CLKA, nCLKA input pairs.

8

VREFA

nCLKA

CLKA

SELAA

GND

Output

9

Input [PD/PU]

Input [PD]

Input [PU]

Power

Inverting differential clock/data input.

10

11

12

13

14

15

Non-inverting differential clock/data input.

Control input: Output amplitude select for channel A.

Power supply ground.

V_DDQA

QA0

Power

Power supply pin for the channel A outputs QA[0:7].

Differential output pair A0. LVDS interface levels.

Output

nQA0

Output

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8P34S2108 Datasheet

Table 1. Pin Descriptions^[a]

Number

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

Name

QA1

Type

Description

Output

Power

Output

Power

Output

Differential output pair A1. LVDS interface levels.

Differential output pair A2. LVDS interface levels.

Differential output pair A3. LVDS interface levels.

Differential output pair A4. LVDS interface levels.

Power supply pin for the channel A outputs QA[0:7].

Differential output pair A5. LVDS interface levels.

Differential output pair A6. LVDS interface levels.

Differential output pair A7. LVDS interface levels.

Differential output pair B0. LVDS interface levels.

Differential output pair B1. LVDS interface levels.

Differential output pair B2. LVDS interface levels.

Power supply pin for the channel B outputs QB[0:7].

Differential output pair B3. LVDS interface levels.

Differential output pair B4. LVDS interface levels.

Differential output pair B5. LVDS interface levels.

Differential output pair B6. LVDS interface levels.

nQA1

QA2

nQA2

QA3

nQA3

QA4

nQA4

V_DDQA

QA5

nQA5

QA6

nQA6

QA7

nQA7

QB0

nQB0

QB1

nQB1

QB2

nQB2

V_DDQB

QB3

nQB3

QB4

nQB4

QB5

nQB5

QB6

nQB6

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8P34S2108 Datasheet

Table 1. Pin Descriptions^[a]

Number

46

Name

QB7

Type

Output

Power

Description

Differential output pair B7. LVDS interface levels.

Power supply pin for the channel B outputs QB[0:7].

Exposed pad of package. Connect to ground.

47

nQB7

48

V_DDQB

ePad

GND_EPAD

[a] Pull-up (PU) and pull-down (PD) resistors are indicated in parentheses. Pull-up and pull-down refers to internal input resistors.

See Table 5, DC Input Characteristics, for typical values.

Function Tables

Table 2. SELAA Bank A Output Amplitude Selection Table

SELAA

QA Output Amplitude (mV)

0

350

500

1 (default)

Table 3. SELAB Bank B Output Amplitude Selection Table

SELAB

QB Output Amplitude (mV)

0

350

500

1 (default)

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8P34S2108 Datasheet

Absolute Maximum Ratings

NOTE: The absolute maximum ratings are stress ratings only. Stresses greater than those listed below can cause permanent damage to

the device. Functional operation of the 8P34S2108 at absolute maximum ratings is not implied. Exposure to absolute maximum rating

conditions may affect device reliability.

Table 4. Absolute Maximum Ratings

Item

Rating

[a]

Supply voltage, V_DD

Inputs, V_I

3.6V

-0.5V to 3.6V

Outputs, I_O

Continuous current

Surge current

10mA

15mA

Input sink/source, I_REF

±2mA

Maximum Junction Temperature, T_J,MAX

125°C

Storage Temperature, T_STG

ESD - Human Body Model^[b]

-65°C to 150°C

2000V

ESD - Charged Device Model^[b]

1500V

[a]

V

denotes V

, V

.

DDB

DD

DDA

[b] According to JEDEC JS-001-2012/JESD22-C101E.

DC Electrical Characteristics

Table 5. DC Input Characteristics

Symbol

C_IN

R_PULLDOWN

R_PULLUP

Parameter

Input capacitance

Test Conditions

Minimum

Typical

Maximum

Units

2

pF

k

Input pull-down resistor

Input pull-up resistor

51

Table 6. Power Supply DC Characteristics, V_DDA= V_DDB= V_DDQA= V_DDQB= 1.8V ± 5%, T_A= -40°C to 85°C

Symbol

Parameter

Power supply voltage

Test Conditions

Minimum

Typical

Maximum

Units

V_DDQA,

V_DDQB

1.71

1.8

1.89

V

V_DDQA

V_DDQB

,

Output supply voltage

1.71

1.8

1.89

V

I_{DDA +}

I_{DDB +}

I_{DDQA +}

I_DDQB

500mV amplitude

350mV amplitude

400

280

495

345

mA

QA[0:7], QB[0:7]

outputs terminated

100 between nQx, Qx

Core and output

supply current

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8P34S2108 Datasheet

Table 7. LVCMOS Inputs DC Characteristics, V_DDA= V_DDB= V_DDQA= V_DDQB= 1.8V ± 5%,

T_A= -40°C to 85°C

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

[a]

V_IH

Input high voltage SELAA, SELAB

0.75 · V_DD

-0.3

V_DD^[a]+ 0.3

V

[a]

V_IL

I_IH

I_IL

Input low voltage

Input high current SELAA, SELAB

Input low current

denotes V , V

SELAA, SELAB

0.25 · V_DD

V_IN= V_DD^[a]= 1.89V

10

µA

[a]

SELAA, SELAB V_IN= 0V, V_DD= 1.89V

-150

[a]

V

.

DDB

DD

DDA

Table 8. Differential Inputs Characteristics, V_DDA= V_DDB= V_DDQA= V_DDQB= 1.8V ± 5%, T_A= -40°C to 85°C

Symbol

I_IH

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

Input high current CLKA, nCLKA

CLKB, nCLKB

V_IN= V_DD^[a]= 1.89V

150

µA

[a]

CLKA, CLKB

Input low current

V_IN= 0V, V_DD= 1.89V

-10

-150

0.9

µA

V

I_IL

[a]

nCLKA, nCLKB

V

_IN= 0V, V_DD= 1.89V

VREFA, B Reference voltage^[b]

[a] denotes V , V

[b] VREF[A:B] specification is applicable to the AC-coupled input interfaces shown in Figure 5 and Figure 6.

I_REF= +100µA, V_DD^[a]= 1.8V

1.30

V

.

DDB

DD

DDA

Table 9. LVDS DC Characteristics, V_DDA= V_DDB= V_DDQA= V_DDQB= 1.8V ± 5%, T_A= -40°C to 85°C

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

V_OD

V_OS

V_ODMagnitude Change

V_OSMagnitude Change

50

mV

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8P34S2108 Datasheet

AC Electrical Characteristics

Table 10. AC Electrical Characteristics, V_DDA= V_DDB= V_DDQA= V_DDQB1.8V ± 5%, T_A= -40°C to 85°C ^[a]

Test Conditions

Symbol

f_REF

Parameter

Minimum Typical

Maximum

Units

Input frequency

Input edge rate

2

GHz

V/ns

ps

V/t

t_PD

1.5

Propagation delay^{[b], [c]}CLKA to any QAx, CLKB to any nQBx

Output skew^{[d], [e]}

100

255

20

10

5

400

40

tsk(o)

tsk(b)

tsk(p)

tsk(pp)

ps

Output bank skew^{[e], [f]}

Pulse skew^[g]

Part-to-part skew^{[e], [h]}

25

ps

f_REF= 100MHz

25

ps

200

80

ps

Buffer Additive Phase

Jitter, RMS;

500mV amplitude;

refer to Additive Phase

Jitter

f

_REF= 156.25MHz;

60

45

fs

Integration range: 1kHz – 40MHz

t_JIT

f_REF= 156.25MHz square wave, V_PP= 1V;

Integration range: 12kHz – 20MHz

60

fs

_N(30M) Clock single-side band

30MHz offset from carrier and noise floor

< -160

-59

dBc/Hz

dB

phase noise

f

_QA= 491.52MHz, f_QB= 61.44MHz;

Spurious suppression,

measured between neighboring outputs

t_{JIT, SP}

coupling between

channels

f

_QA= 491.52MHz, f_QB= 15.36MHz;

-59

dB

measured between neighboring outputs

10% to 90%, outputs loaded with 100

20% to 80%, outputs loaded with 100

150

90

400

160

1.2

ps

V

t_R/ t_F

V_PP

V_{PP_DIFF}

Output rise/ fall time

Input voltage

amplitude

CLKA,

CLKB

0.15

0.3

Differential

input voltage

amplitude

CLKA,

CLKB

2.4

V

V_CMR

Common mode

input voltage^[i]

1.1

247

350

V_DD^[j]– (V_PP/2

)

V

SELAA, SELAB = 0,

outputs loaded with 100

350

500

454

650

mV

Differential

output voltage

V_OD

SELAA, SELAB = 1,

outputs loaded with 100

SELAA, SELAB = 0

SELAA, SELAB = 1

0.8

0.7

V

V_OS

Offset voltage

[a] Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device

is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal

equilibrium has been reached under these conditions.

[b] Measured from the differential input crossing point to the differential output crossing point.

[c] Input V_PP= 400mV.

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October 20, 2016

8P34S2108 Datasheet

[d] Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross

points.

[e] This parameter is defined in accordance with JEDEC Standard 65.

[f]

Defined as skew within a bank of outputs at the same voltage and with equal load conditions.

[g] Output pulse skew is the absolute value of the difference of the propagation delay times:  t_PLH- t_PHL.

[h] Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature

and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross

points.

[i]

Common Mode Input Voltage is defined as the cross-point voltage.

denotes V , V

[j]

V

.

DDB

DD

DDA

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October 20, 2016

8P34S2108 Datasheet

Additive Phase Jitter

The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase

Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise

is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value

of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental.

When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the

fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over

the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot.

Figure 2. Additive Phase Jitter. Frequency: 156.25MHz, Integration range: 12kHz to 20MHz = 45fs typical

Offset from Carrier Frequency (Hz)

As with most timing specifications, phase noise measurements have issues relating to the limitations of the measurement equipment. The

noise floor of the equipment can be higher or lower than the noise floor of the device. Additive phase noise is dependent on both the

noise floor of the input source and measurement equipment.

Measured using a Wenzel 156.25MHz Oscillator as the input source.

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October 20, 2016

8P34S2108 Datasheet

Applications Information

Recommendations for Unused Input and Output Pins

Inputs:

CLK/nCLK Inputs

For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for

additional protection, a 1k resistor can be tied from CLK to ground.

Outputs:

LVDS Outputs

All unused LVDS output pairs can be either left floating or terminated with 100 across. If they are left floating there should be no trace

attached.

VREFX

The unused VREFA and VREFB pins can be left floating. We recommend that there is no trace attached.

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October 20, 2016

8P34S2108 Datasheet

Wiring the Differential Input to Accept Single-Ended Levels

Figure 3 shows how a differential input can be wired to accept single ended levels. The reference voltage V₁= V_DD/2 is generated by the

bias resistors R1 and R2. The bypass capacitor (C1) is used to help filter noise on the DC bias. This bias circuit should be located as

close to the input pin as possible. The ratio of R1 and R2 might need to be adjusted to position the V₁in the center of the input voltage

swing. For example, if the input clock swing is 1.8V and V_DD= 1.8V, R1 and R2 value should be adjusted to set V₁at 0.9V. The values

below are for when both the single ended swing and V_DDare at the same voltage. This configuration requires that the sum of the output

impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at

the input will attenuate the signal in half. This can be done in one of two ways. First, R3 and R4 in parallel should equal the transmission

line impedance. For most 50 applications, R3 and R4 can be 100. The values of the resistors can be increased to reduce the loading

for slower and weaker LVCMOS driver. When using single-ended signaling, the noise rejection benefits of differential signaling are

reduced. Even though the differential input can handle full rail LVCMOS signaling, it is recommended that the amplitude be reduced while

maintaining an edge rate faster than 1V/ns. The datasheet specifies a lower differential amplitude, however this only applies to differential

signals. For single-ended applications, the swing can be larger, however V_ILcannot be less than -0.3V and V_IHcannot be more than V_DD

+ 0.3V. Though some of the recommended components might not be used, the pads should be placed in the layout. They can be utilized

for debugging purposes. The datasheet specifications are characterized and guaranteed by using a differential signal.

Figure 3. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels

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October 20, 2016

8P34S2108 Datasheet

1.8V Differential Clock Input Interface

The CLK /nCLK accepts LVDS, LVPECL and other differential signals. The differential input signal must meet both the V_PPand V_CMR

input requirements. Figure 4 to Figure 6 show interface examples for the CLK /nCLK input driven by the most common driver types. The

input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please

consult with the vendor of the driver component to confirm the driver termination requirements.

Figure 4. Differential Input Driven by an LVDS Driver - DC Coupling

Figure 5. Differential Input Driven by an LVDS Driver - AC Coupling

Figure 6. Differential Input Driven by an LVPECL Driver - AC Coupling

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October 20, 2016

8P34S2108 Datasheet

LVDS Driver Termination

For a general LVDS interface, the recommended value for the termination impedance (Z_T) is between 90 and 132. The actual value

should be selected to match the differential impedance (Z₀) of your transmission line. A typical point-to-point LVDS design uses a 100

parallel resistor at the receiver and a 100 differential transmission-line environment. In order to avoid any transmission-line reflection

issues, the components should be surface mounted and must be placed as close to the receiver as possible. IDT offers a full line of LVDS

compliant devices with two types of output structures: current source and voltage source. The standard termination schematic as shown

in Figure 7 can be used with either type of output structure. Figure 8, which can also be used with both output types, is an optional

termination with center tap capacitance to help filter common mode noise. The capacitor value should be approximately 50pF. If using a

non-standard termination, it is recommended to contact IDT and confirm if the output structure is current source or voltage source type. In

addition, since these outputs are LVDS compatible, the input receiver’s amplitude and common-mode input range should be verified for

compatibility with the output.

Figure 7. Standard LVDS Termination

Z_O Z_T

LVDS

Driver

LVDS

Receiver

Z_T

Figure 8. Optional LVDS Termination

Z

T

2

Z_O Z_T

LVDS

Driver

Receiver

C

Z

2

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October 20, 2016

8P34S2108 Datasheet

VFQFN EPAD Thermal Release Path

In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on

the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the

package, as shown in Figure 9. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape

as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed

on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts.

While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a

solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must

be connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are application specific

and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis

and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved

when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is

also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to

avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug

and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern.

Note: These recommendations are to be used as a guideline only. For further information, please refer to the application note on the

Surface Mount Assembly of Amkor’s Thermally/ Electrically Enhance Leadframe Base Package, Amkor Technology.

Figure 9. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)

SOLDER

EXPOSED HEAT SLUG

PIN PAD

GROUND PLANE

LAND PATTERN

(GROUND PAD)

PIN PAD

THERMAL VIA

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October 20, 2016

8P34S2108 Datasheet

Case Temperature Considerations

This device supports applications in a natural convection environment which does not have any thermal conductivity through ambient air.

The printed circuit board (PCB) is typically in a sealed enclosure without any natural or forced air flow and is kept at or below a specific

temperature. The device package design incorporates an exposed pad (ePad) with enhanced thermal parameters which is soldered to

the PCB where most of the heat escapes from the bottom exposed pad. For this type of application, it is recommended to use the

junction-to-board thermal characterization parameter _JB(Psi-JB) to calculate the junction temperature (T_J) and ensure it does not

exceed the maximum allowed junction temperature in the Absolute Maximum Rating table.

The junction-to-board thermal characterization parameter, _JB,is calculated using the following equation:

T_J= T_CB+ _JBx P_D,where

T_J= Junction temperature at steady state condition in (^oC).

T

_CB= Case temperature (Bottom) at steady state condition in (^oC).



_JB= Thermal characterization parameter to report the difference between junction temperature and the temperature of the board

measured at the top surface of the board.

P_D= power dissipation (W) in desired operating configuration.

T

J

T

CB

The ePad provides a low thermal resistance path for heat transfer to the PCB and represents the key pathway to transfer heat away from

the IC to the PCB. It’s critical that the connection of the exposed pad to the PCB is properly constructed to maintain the desired IC case

temperature (T_CB). A good connection ensures that temperature at the exposed pad (T_CB) and the board temperature (T_B) are relatively

the same. An improper connection can lead to increased junction temperature, increased power consumption and decreased electrical

performance. In addition, there could be long-term reliability issues and increased failure rate.

Example Calculation for Junction Temperature (T_J): T_J= T_CB+ _JBx P_D

Package type

Body size (mm)

ePad size (mm)

Thermal Via

48 VFQFN

7 x 7 x 0.8

5.65 x 5.65

5 x 5 Matrix

1.2^oC/W

105^oC



JB

T_CB

P_D

0.9W

For the variables above, the junction temperature is equal to 106.1^oC. Since this is below the maximum junction temperature of 125^oC,

there are no long term reliability concerns. In addition, since the junction temperature at which the device was characterized using forced

convection is 122^oC, this device can function without the degradation of the specified AC or DC parameters.

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October 20, 2016

8P34S2108 Datasheet

Power Considerations

This section provides information on power dissipation and junction temperature for the 8P34S2108.

Equations and example calculations are also provided.

1. Power Dissipation.

The following is the power dissipation for V_DD= 1.8V + 5% = 1.89V, which gives worst case results.

Maximum current at 85°C: V_{DD_MAX}= 495mA.

▪ Power__MAX= V_{DD_MAX}* I_{DD_MAX}= 1.89V * 495mA = 935.55mW

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The

maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that

the bond wire and bond pad temperature remains below 125°C.

The equation for Tj is as follows: Tj = _JA* Pd_total + T_A

Tj = Junction Temperature



_JA= Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

T_A= Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance _JAmust be used. Assuming no air flow

and a multi-layer board, the appropriate value is 22.4°C/W per Table 11 below.

Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:

85°C + 0.93555W * 22.4°C/W = 106.0°C. This is below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the

type of board (multi-layer).

Table 11. Thermal Resistance _JAfor 48-lead VFQFN, Forced Convection

_JA(°C/W) vs. Air Flow (m/s)

Meters per Second

0

1

2

48-lead VFQFN Multi-Layer PCB, JEDEC Standard Test Boards

22.4

18.9

17.4

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October 20, 2016

8P34S2108 Datasheet

Package Drawings

Figure 10. 48-lead VFQFN Package Outline and Dimensions

17

October 20, 2016

8P34S2108 Datasheet

Package Drawings, continued

Figure 11. 48-lead VFQFN Package Outline and Dimensions

18

October 20, 2016

8P34S2108 Datasheet

Marking Diagram

1. Line 1, line 2, and line 3 indicates the part number.

2. Line 4:

▪ “#” indicates stepping.

▪ “YYWW” indicates the date code (YY are the last two digits of the year, and

“WW” is a work week number that the part was assembled.

▪ “$” indicates the mark code.

Ordering Information

Table 12. Ordering Information

Part/Order Number

Marking

Package

Shipping Packaging

Temperature

8P34S2108NLGI

8P34S2108NLGI8

IDT8P34S2108NLGI

Tray

Tape & Reel, Pin 1 Orientation:

EIA-481-C

48-lead VFQFN, Lead-Free

-40°C to 85°C

8P34S2108NLGI/W

IDT8P34S2108NLGI

Tape & Reel, Pin 1 Orientation:

EIA-481-D/E

Table 13. Pin 1 Orientation in Tape and Reel Packaging

Part Number Suffix

Pin 1 Orientation

Illustration

8

Quadrant 1 (EIA-481-C)

/W

Quadrant 2 (EIA-481-D/E)

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October 20, 2016

8P34S2108 Datasheet

Revision History

Revision Date

Description of Change

October 20, 2016

Page 1, Features, added Device current consumption.

Page 9, added Additive Phase Jitter section.

Page 18, added Marking Diagram.

Updated datasheet formatting.

July 28, 2016

July 12, 2016

Features Section - corrected phase jitter bullet spec from <50fs to 45fs.

this is the first release of the 8P34S2108 Datasheet.

Corporate Headquarters

Sales

Tech Support

6024 Silver Creek Valley Road

San Jose, CA 95138 USA

www.IDT.com

1-800-345-7015 or 408-284-8200

Fax: 408-284-2775

www.IDT.com/go/sales

www.IDT.com/go/support

DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance spec-

ifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information

contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied

warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of

IDT or any third parties.

IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be rea-

sonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.

Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property

20

October 20, 2016


型号：	8P34S2108NLGI
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	Dual 1:8 LVDS Output 1.8V Fanout Buffer
文件：	总20页 (文件大小：544K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

8P34S2108NLGI [IDT]

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