8P391208_技术文档

Low Additive Jitter 2:8 Buffer with

Universal Differential Outputs

8P391208

Datasheet

General Description

Features

• Two differential inputs support LVPECL, LVDS, HCSL or LVCMOS

reference clocks

8P391208 is intended to take 1 or 2 reference clocks, select

between them, using a pin selection and generate up to 8 outputs

that are the same as the reference frequency.

• Accepts input frequencies ranging from 1PPS (1Hz) to 700MHz

(up to 1GHz when configured into HCSL output mode at 3.3V)

8P391208 supports two output banks, each with its own power

supply. All outputs in one bank would generate the same output

frequency, and each bank can be individually controlled for output

type or output enable.

• Select which of the two input clocks is to be used as the reference

clock for which bank via pin selection

• Generates 8 differential outputs

• Differential outputs selectable as LVPECL, LVDS, CML or HCSL

• CML mode supports two different voltage swings

The device can operate over the -40°C to +85°C temperature range.

• Differential outputs support frequencies from 1PPS to 700MHz

(up to 1GHz when configured into HCSL output mode at 3.3V)

• Outputs arranged in 2 banks of 4 outputs each

• Each bank supports a separate power supply of 3.3V, 2.5V or

1.8V

• Controlled by 3-level input pins

• Input mux selection control pin

• Control inputs are 3.3V-tolerant for all core voltages

• Output noise floor of -153dBc/Hz @ 156.25MHz

• Core voltage supply of 3.3V, 2.5V or 1.8V

• -40°C to +85°C ambient operating temperature

• Lead-free (RoHS 6) packaging

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September 1, 2016

8P391208 Datasheet

8P391208 Block Diagram

QA0

nQA0

QA1

nQA1

CLK_SEL

QA2

nQA2

QA3

CLK0

nCLK0

nQA3

QB0

nQB0

CLK1

nCLK1

QB1

nQB1

QB2

nQB2

QB3

nQB3

IOA

2

Logic

IOB

2

Pin Assignment

Figure 1: 8P391208 Pin Assignment for 5mm x 5mm 32-pin VFQFN Package

31 30 29 28 27 26 25

32

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

IOB1

QB0

IOA1

QA0

nQB0

QB1

nQA0

QA1

nQB1

V_CCOB

QB2

nQA1

V_CCOA

QA2

nQA2

nQB2

10 11 12 13 14 15 16

9

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September 1, 2016

8P391208 Datasheet

Pin Description and Characteristic Tables

Table 1: Pin Description

Number

Name

Type^[1]

Description

Pullup /

Pulldown

1

IOA1

Input

Controls output functions for Bank A. 3-level input.

Positive differential clock output. Included in Bank A. 

Refer to Output Drivers section for more details.

2

3

4

QA0

nQA0

QA1

Output

Negative differential clock output. Included in Bank A. 

Refer to Output Drivers section for more details.

Positive differential clock output. Included in Bank A. 

Refer to Output Drivers section for more details.

Negative differential clock output. Included in Bank A. 

Refer to Output Drivers section for more details.

5

6

7

nQA1

V_CCOA

QA2

Output

Power

Output

Output voltage supply for Output Bank A.

Positive differential clock output. Included in Bank A. 

Refer to Output Drivers section for more details.

Negative differential clock output. Included in Bank A. 

Refer to Output Drivers section for more details.

8

9

nQA2

QA3

Output

Positive differential clock output. Included in Bank A. 

Refer to Output Drivers section for more details.

Negative differential clock output. Included in Bank A. 

Refer to Output Drivers section for more details.

10

nQA3

11

12

nc

Unused

Power

Unused. Do not connect.

Core Logic voltage supply.

V_CC

Pullup /

Input Clock Selection Control pin. 3-level input. This pin’s function is

13

14

15

CLK_SEL

nc

Input

Unused

Output

Pulldown described in the Input Selection section.

Unused. Do not connect.

Negative differential clock output. Included in Bank B. Refer to 

Output Drivers section for more details.

nQB3

Positive differential clock output. Included in Bank B. Refer to 

Output Drivers section for more details.

16

17

QB3

Output

Negative differential clock output. Included in Bank B. Refer to 

Output Drivers section for more details.

nQB2

Positive differential clock output. Included in Bank B. Refer to 

Output Drivers section for more details.

18

19

20

QB2

V_CCOB

nQB1

Output

Power

Output

Output voltage supply for Output Bank B.

Negative differential clock output. Included in Bank B. Refer to 

Output Drivers section for more details.

Positive differential clock output. Included in Bank B. Refer to 

Output Drivers section for more details.

21

QB1

Output

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September 1, 2016

8P391208 Datasheet

Table 1: Pin Description (Continued)

Negative differential clock output. Included in Bank B. 

Refer to Output Drivers section for more details.

22

23

nQB0

QB0

Output

Positive differential clock output. Included in Bank B. 

Refer to Output Drivers section for more details.

Pullup /

Pulldown

24

25

26

27

28

IOB1

CLK1

nCLK1

V_CC

Input

Power

Input

Controls output functions for Bank B. 3-level input.

Pulldown Non-inverting differential clock input.

Pullup / Inverting differential clock input. V_CC/2 when left floating (set by the internal

Pulldown pullup and pulldown resistors).

Core Logic voltage supply.

Pullup /

IOB0

Controls output functions for Bank B. 3-level input.

Pulldown

Pullup /

Pulldown

29

30

31

IOA0

V_CC

Input

Power

Input

Controls output functions for Bank A. 3-level input.

Core Logic voltage supply.

Pullup /

Inverting differential clock input. V_CC/2 when left floating (set by the internal

nCLK0

Pulldown pullup and pulldown resistors).

Pulldown Non-inverting differential clock input.

Exposed pad must be connected to GND.

32

CLK0

V_EE

Input

EP

Ground

1. Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 2: Pin Characteristics

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

C_IN

Input Capacitance

2

pF

k

LVPECL

LVDS

V_CCOx^[1]= 3.465V or 2.625V

2.0

2.5

Power Dissipation

Capacitance 

(per output pair)

CML, 400mV

CML, 800mV

LVPECL

C_PD

QA[0:3], nQA[0:3];

QB[0:3], nQB[0:3]

LVDS

V_CCOx^[1]= 1.89V

CML, 400mV

CML, 800mV

R_PULLUP

Input Pullup Resistor

51

R_PULLDOWNInput Pulldown Resistor

1. V_CCOxrefers to V_CCOAfor QA[3:0], nQA[3:0] or V_CCOBfor QB[3:0], nQB[3:0].

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September 1, 2016

8P391208 Datasheet

Principles of Operation

Input Selection

The 8P391208 supports two input references: CLK0 and CLK1 that may be driven with differential or single-ended clock signals. Either may be

used as the source frequency for either or both output banks under control of the CLK_SEL input pin.

Table 3: Input Selection Control

CLK_SEL

Description

High

Middle^[1]

Low

Banks A & B Both Driven from CLK1

Bank A Driven from CLK0 & Bank B Driven from CLK1

Banks A & B Both Driven from CLK0

1. A ‘middle’ voltage level is defined in Table 10. Leaving the input pin open will

also generate this level via a weak internal resistor network.

Output Drivers

The QA[0:3] and QB[0:3] clock outputs are provided with pin-controlled output drivers. The following table shows how each bank can be

controlled. Each bank is separately controlled and all outputs within a single bank will behave the same way.

Table 4: Output Mode and Enable Control

IOx[1]

IOx[0]

Output Bank Function

High

Middle

Low

All outputs in the bank are high-impedance

All outputs in the bank are LVPECL

All outputs in the bank are LVDS

High

Middle

Low

High

All outputs in the bank are CML (400mV)

All outputs in the bank are high-impedance

All outputs in the bank are HCSL

Middle

Low

High

All outputs in the bank are CML (800mV)

All outputs in the bank are LVPECL

All outputs in the bank are high-impedance

Low

Middle

Low

CML operation supports both a 400mV (pk-pk) swing and an 800mV (pk-pk) swing selection.

The operating voltage ranges of each output is determined by its independent output power pin (V_CCOAor V_CCOB) and thus each can have

different output voltage levels. Output voltage levels of 1.8V, 2.5V or 3.3V are supported for differential operation_.

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September 1, 2016

8P391208 Datasheet

Absolute Maximum Ratings

NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are

stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC

Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may

affect product reliability.

Table 5: Absolute Maximum Ratings

Item

Supply Voltage, V_CCX^[1]to GND

Rating

3.6V

Inputs IOA[1:0], IOB[1:0], CLK_SEL, CLK0, nCLK0, CLK1, nCLK1

-0.5V to 3.6V

Outputs, I_OQA[0:3], nQA[0:3]; QB[0:3], nQB[0:3]

Continuous Current

40mA

60mA

Surge Current

Outputs, V_OQA[0:3], nQA[0:3]; QB[0:3], nQB[0:3]

Operating Junction Temperature

-0.5V to 3.6V

125°C

Storage Temperature, T_STG

-65°C to 150°C

+260°C

Lead Temperature (Soldering, 10s)

1. V_CCXdenotes V_CC, V_CCOA, or V_CCOB

.

Supply Voltage Characteristics

[1]

Table 6: Power Supply Characteristics, V

= V

= 3.3V ±5%, V = 0V, T = -40°C to +85°C

CC

CCOx

EE

A

Symbol Parameter

Test Conditions

Minimum Typical

Maximum Units

V_CC

Core Supply Voltage

Output Supply Voltage

3.135

3.3

3.465

V

V_CCOx

All Outputs Configured for LVDS Logic Levels;

Outputs Unloaded

I_CC

Core Supply Current

22

25

mA

All Outputs Configured for LVDS Logic Levels;

Outputs Unloaded

I_ccox

Output Supply Current^[2]

139

157

1. NOTE 1. V_CCOxdenotes V_CCOA, V_CCOB

.

2. Internal dynamic switching current at maximum f_OUTis included.

[1]

Table 7: Power Supply Characteristics, V

= V

= 2.5V ±5%, V = 0V, T = -40°C to +85°C

CC

CCOx

EE

A

Symbol Parameter

Test Conditions

Minimum Typical Maximum

Units

V_CC

Core Supply Voltage

Output Supply Voltage

2.375

2.5

2.625

V

V_CCOx

All Outputs Configured for LVDS Logic Levels;

Outputs Unloaded

I_CC

Core Supply Current

19

22

mA

All Outputs Configured for LVDS Logic Levels;

Outputs Unloaded

I_ccox

Output Supply Current^[2]

137

154

1. NOTE 1. V_CCOxdenotes V_CCOA, V_CCOB

.

2. Internal dynamic switching current at maximum f_OUTis included.

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September 1, 2016

8P391208 Datasheet

[1]

Table 8: Power Supply Characteristics, V

= V

= 1.8V ±5%, V = 0V, T = -40°C to +85°C

EE A

CC

CCOx

Symbol Parameter

Test Conditions

Minimum

Typical

Maximum

Units

V_CC

Core Supply Voltage

1.71

1.8

1.89

V

V_CCOxOutput Supply Voltage

All Outputs Configured for LVDS Logic Levels;

Outputs Unloaded

I_CC

Core Supply Current

15

17

mA

All Outputs Configured for LVDS Logic Levels;

Outputs Unloaded

I_ccox

Output Supply Current^[2]

125

141

1. NOTE 1. V_CCOxdenotes V_CCOA, V_CCOB

.

2. Internal dynamic switching current at maximum f_OUTis included.

Table 9: Typical Output Supply Current, V

= 3.3V, 2.5V or 1.8V, V = 0V, T = 25°C

EE A

CC

V_CCOx^[2]= 3.3V

V_CCOx^[2]= 2.5V

V_CCOx^[2]= 1.8V

Bank A

Output

Supply

Current

Outputs

Unloaded

I_CCOA

50 66 41 33 33 49 65 37 31 31 43 28 31 27 27 mA

Bank B

Output

Supply

Current

Outputs

Unloaded

I_CCOB

50 66 41 33 33 49 65 37 31 31 43 28 31 27 27 mA

1. Internal dynamic switching current at maximum f_OUTis included.

2. V_CCOxdenotes V_CCOA, or V_CCOB

.

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September 1, 2016

8P391208 Datasheet

DC Electrical Characteristics

Table 10: LVCMOS/LVTTL Control / Status Signals DC Characteristics for 3-Level Pins, V = 0V, 

EE

T = -40°C to +85°C

A

Symbol Parameter

Signals

Test Conditions

Minimum Typical

Maximum

Units

V_CC= 3.3V

0.85*V_CC

0.45*V_CC

-0.3

3.465

2.625

V

Input

V_IH

CLK_SEL, IOA[1:0], IOB[1:0]

V

_CC= 2.5V

_CC= 1.8V

High Voltage

1.89

V_CC= 3.3V

0.55*V_CC

0.15*V_CC

Input

V_IM

Middle

CLK_SEL, IOA[1:0], IOB[1:0]

CLK_SEL, IOA[1:0], IOB[1:0],

V

_CC= 2.5V

_CC= 1.8V

Voltage^[1]

V_CC= 3.3V

Input

Low Voltage

V_IL

V

_CC= 2.5V

_CC= 1.8V

-0.3

Input

High Current

V_CC= V_IN= 3.465V or

2.625V or 1.89V

I_IH

I_IM

I_IL

CLK_SEL, IOA[1:0], IOB[1:0]

CLK_SEL, IOA[1:0], IOB[1:0],

150

A

V

_CC= 3.465V or

Input

Middle Current

2.625V or 1.89V,

V_IN= V_CC/2

-10

10

Input

Low Current

V_CC= 3.465V or

2.625V or 1.89V, V_IN= 0V

-150

1. For 3-level input pins, a mid-level voltage is used to select the 3^rdstate. This voltage will be maintained by a weak internal pull-up /

pull-down network for each pin to select this state if the pin is left open. It is recommended that any external resistor networks used to

select a middle-level input voltage be terminated to the device’s core V_CCvoltage level.

,

Table 11: Differential Input DC Characteristics, V

A

= 3.3V±5%, 2.5V±5% or 1.8V±5%, V = 0V, 

EE

CC

T = -40°C to +85°C

Symbol Parameter

Test Conditions

Minimum

Typical

Maximum Units

CLKx,

I_IH

Input High Current

V_CC= V_IN= 3.465V or 2.625V

150

A

nCLKx^[1]

CLKx^[1]

V_CC= 3.465V or 2.625V, V_IN= 0V

-5

A

V

I_IL

Input Low Current

nCLKx^[1]

Peak-to-Peak Voltage^[2]

-150

0.2

V_PP

1.3

, [3]

V_CMR

Common Mode Input Voltage^[2]

V_EE

V_CC-1.2

V

1. CLKx denotes CLK0, CLK1. nCLKx denotes nCLK0, nCLK1.

2. V_ILshould not be less than -0.3V. V_IHshould not be higher than V_CC.

3. Common mode voltage is defined as the cross-point.

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September 1, 2016

8P391208 Datasheet

Table 12: LVPECL DC Characteristics, V

A

= 3.3V±5%, 2.5V±5% or 1.8V±5%, V = 0V, 

EE

CC

T = -40°C to +85°C

V_CCOx^[1]= 3.3V±5%

Min Typ Max

V_CCOx^[1]= 2.5V±5%

Min Typ Max

V_CCOx^[1]= 1.8V±5%

Symbol Parameter

Min

Typ

Max

Units

Output

Qx,

V_CCOx

1.3

-

V_CCOx

0.8

-

V_CCOx

1.35

-

V_CCOx

0.9

-

V_CCOx

1.50

-

V_CCOx

0.9

-

V_OH

High

V

nQx^[3]

Voltage^[2]

Output

V_CCOx

1.75

V_CCOx

2

V_CCOx

1.75

V_OL

Qx, nQx^[2]V_CCOx- 2

V_EE

0.25

V

Low Voltage^[2]

1. V_CCOxdenotes V_CCOA,V_CCOB.

2. Outputs terminated with 50 to V_CCOx– 2V when V_CCOX= 3.3V±5% or 2.5V±5%. Outputs terminated with 50 to ground when V_CCOX

= 1.8V±5%.

3. Qx denotes QA0, QA1, QA2, QA3, QB0, QB1, QB2, QB3. nQx denotes nQA0, nQA1, nQA2, nQA3, nQB0, nQB1, nQB2, nQB3.

[1]

Table 13: LVDS DC Characteristics, V

= 3.3V ±5%, V = 0V, T = -40°C to +85°C^[1]

EE A

CCOx

Symbol Parameter

Test Conditions

Minimum

Typical

Maximum

Units

V_OD

V_OD

V_OS

Differential Output Voltage Qx, nQx^[2]

195

480

50

mV

V

V_ODMagnitude Change

Offset Voltage

Qx, nQx^[2]

Terminated 100 across

Qx, nQx^[2]

1.1

1.375

50

Qx and nQx

V_OS

V_OSMagnitude Change

mV

1. V_CCOxdenotes V_CCOA, V_CCOB

.

2. Qx denotes QA0, QA1, QA2, QA3, QB0, QB1, QB2, QB3.

nQx denotes nQA0, nQA1, nQA2, nQA3, nQB0, nQB1, nQB2, nQB3.

[1]

Table 14: LVDS DC Characteristics, V

= 2.5V ±5%, V = 0V, T = -40°C to +85°C

EE A

CCOx

Symbol Parameter

Test Conditions

Minimum

Typical

Maximum

Units

V_OD

V_OD

V_OS

Differential Output Voltage Qx, nQx^[2]

195

470

50

mV

V

V_ODMagnitude Change

Offset Voltage

Qx, nQx^[2]

Terminated 100 across

Qx, nQx^[2]

1.1

1.375

50

Qx and nQx

V_OS

V_OSMagnitude Change

mV

1. V_CCOxdenotes V_CCOA, V_CCOB

.

2. Qx denotes QA0, QA1, QA2, QA3, QB0, QB1, QB2, QB3.

nQx denotes nQA0, nQA1, nQA2, nQA3, nQB0, nQB1, nQB2, nQB3.

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September 1, 2016

8P391208 Datasheet

[1]

Table 15: LVDS DC Characteristics, V

= 1.8V ±5%, V = 0V, T = -40°C to +85°C

CCOx

EE

A

Symbol Parameter

Test Conditions

Minimum

Typical

Maximum

Units

V_OD

V_OD

V_OS

Differential Output Voltage Qx, nQx^[2]

195

454

50

mV

V

V_ODMagnitude Change

Offset Voltage

Qx, nQx^[2]

Terminated 100 across

Qx, nQx^[2]

1.1

1.375

50

Qx and nQx

V_OS

V_OSMagnitude Change

mV

1. V_CCOxdenotes V_CCOA,V_CCOB.

2. Qx denotes QA0, QA1, QA2, QA3, QB0, QB1, QB2, QB3.

nQx denotes nQA0, nQA1, nQA2, nQA3, nQB0, nQB1, nQB2, nQB3.

Table 16: CML (400mV Swing) DC Characteristics, V

CCOx

= 3.3V ±5%, 2.5V ±5% or 1.8V ±5%, 

CC

[1]

V

= 3.3V ±5%, 2.5V ±5% or 1.8V ±5%, V

= 0V, T = -40°C to +85°C

EE A

Symbol Parameter

Test Conditions

Minimum

Typical

Maximum

Units

V_OH

V_OL

Output High Voltage

Qx, nQx^[2]

V_CCOx- 0.1

V_CCOx- 0.5

300

V_CCOx

V_CCOx- 0.3

500

V

Terminated with 50 to

Output Low Voltage

V_CCOx

V_OUT

Output Voltage Swing

mV

1. V_CCOxdenotes V_CCOA,V_CCOB.

2. Qx denotes QA0, QA1, QA2, QA3, QB0, QB1, QB2, QB3.

nQx denotes nQA0, nQA1, nQA2, nQA3, nQB0, nQB1, nQB2, nQB3.

Table 17: CML (800mV Swing) DC Characteristics, V

CCOx

= 3.3V ±5%, 2.5V ±5% or 1.8V ±5%, 

CC

[1]

V

= 3.3V ±5%, 2.5V ±5% or 1.8V ±5%, V

= 0V, T = -40°C to +85°C

EE A

Symbol Parameter

Test Conditions

Minimum

Typical

Maximum

Units

V_OH

V_OL

Output High Voltage

Qx, nQx^[2]

V_CCOx- 0.1

V_CCOx

V_CCOx- 0.7

1000

V

Output Low Voltage

Qx, nQx^[2]Terminated with 50 to V_CCOxV_CCOx- 0.95

Qx, nQx^[2]

575

V_OUT

Output Voltage Swing

mV

1. V_CCOxdenotes V_CCOA, V_CCOB

.

2. Qx denotes QA0, QA1, QA2, QA3, QB0, QB1, QB2, QB3.

nQx denotes nQA0, nQA1, nQA2, nQA3, nQB0, nQB1, nQB2, nQB3.

[1] [2]

Table 18: HCSL DC Characteristics, V

= V

= 3.3V ±5%, V = 0V, T = 25°C

,

CC

CCOA

CCOB

EE

A

Symbol Parameter

Test Conditions

Minimum

Typical

Maximum

Units

V_OH

V_OL

Output High Voltage

Output Low Voltage

Output Voltage Swing

Qx, nQx

475

-100

475

900

mV

V_OUT

900

1. Guaranteed by design and Characterization, not 100% tested in production.

2. C_L= 2pf, R_S= 33.2, R_P= 49.9

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September 1, 2016

8P391208 Datasheet

Table 19: Input Frequency Characteristics, V

A

= 3.3V±5%, 2.5V±5% or 1.8V±5%, V = 0V, 

EE

CC

T = -40°C to +85°C

Symbol Parameter

Test Conditions

Minimum

Typical

Maximum

Units

f_IN

Input Frequency

Input Duty Cycle^[3]

CLKx, nCLKx^{[1], [2]}

1Hz

700MHz

idc

50

%

1. CLKx denotes CLK0, CLK1. nCLKx denotes nCLK0, nCLK1.

2. Input frequency is up to 1GHz when V_CC/V_CCOx= 3.3V±5% for HCSL output mode.

3. Any deviation from a 50% duty cycle on the input may be reflected in the output duty cycle.

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September 1, 2016

8P391208 Datasheet

AC Electrical Characteristics

Table 20: LVDS, LVPECL, CML AC Characteristics, V

= 3.3V ±5%, 2.5V ±5% or 1.8V ±5%, 

CC

[1]

V

= 3.3V ±5%, 2.5V ±5% or 1.8V ±5%, V

= 0V, T = -40°C to +85°C

EE A

CCOx

Symbol Parameter^[2]

Test Conditions^[3]

Minimum

Typical

Maximum Units

Output

f_OUT

LVDS,

LVPECL, CML

1PPS

700

MHz

Frequency

LVPECL

LVDS

20% to 80%

20% to 80%, V_CCOx= 3.3V

20% to 80%, V_CCOx= 2.5V

20% to 80%, V_CCOx= 1.8V

20% to 80%

100

150

165

200

100

150

705

530

565

625

580

55

ps

%

Output Rise and

t_R/ t_F

Fall Times

CML 400mV

CML 800mV

LVPECL^[7]

20% to 80%

LVDS^[7]

55

Bank Skew^[4],

t_sk(b)

odc

[5], [6]

CML 400mV^[7]

CML 800mV^[7]

Output Duty Cycle^[8]

55

45

50

70

25

55

MUX_ISOLMux Isolation

t_startupStartup Time

1. V_CCOxdenotes V_CCOA, V_CCOB

dB

ms

.

2. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal

equilibrium has been reached under these conditions.

3. Tested for the following out frequencies: 100MHz, 156.25MHz, 312.5MHz, 700MHz.

4. This parameter is guaranteed by characterization. Not tested in production.

5. This parameter is defined in accordance with JEDEC Standard 65.

6. Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions.

7. Measured at the output differential crosspoint.

8. Measured using 50% duty cycle on input reference.

12

September 1, 2016

8P391208 Datasheet

= 3.3V ±5%, 2.5V ±5% or 1.8V ±5%, 

Table 21: HCSL AC Characteristics, f

CCOx

= 100MHz, V

CC

OUT

[1]

V

= 3.3V ±5%, 2.5V ±5% or 1.8V ±5%, V

= 0V, T = -40°C to +85°C

EE A

Symbol Parameter^[2]

V_RB

Ring-back Voltage Margin^{[3], [4]}

t_STABLETime before V_RBis allowed^{[3] [4]}

Test Conditions

Minimum Typical

Maximum

Units

-100

500

100

mV

ps

,

V_MAX

V_MIN

Absolute Max. Output Voltage^{[5], [6]}

1150

mV

, [7]

Absolute Min. Output Voltage^[5]

-300

200

V_CROSSAbsolute Crossing Voltage^{[8], [9],}

V_CROSSTotal Variation of V_CROSSover all edge^[8]

550

140

[5]

, [10],

[5]

1. V_CCOxdenotes V_CCOA, V_CCOB

.

2. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal

equilibrium has been reached under these conditions.

3. Measurement taken from differential waveform.

4. t_STABLEis the time the differential clock must maintain a minimum ±150mV differential voltage after rising/falling edges before it is

allowed to drop back into the V_RB±100mV differential range.

5. Measurement taken from single ended waveform.

6. Defined as the maximum instantaneous voltage including overshoot.

7. Defined as the minimum instantaneous voltage including undershoot.

8. Measured at crossing point where the instantaneous voltage value of the rising edge of Qx equals the falling edge of nQx.

9. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing

points for this measurement.

10.Defined as the total variation of all crossing voltages of rising Qx and falling nQx, This is the maximum allowed variance in V_CROSSfor any

particular system.

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September 1, 2016

8P391208 Datasheet

Table 22: HCSL Electrical Characteristics, Current Mode Differential Pair, V

= V

= 3.3V±5%,

CCOB

CC

CCOA

[1], [2]

2.5V ±5% or 1.8V ±5%, V = 0V, T = -40°C to +85°C

EE

A

Test Conditions^{[3] [4]}

Minimum Typical Maximum Units

,

Symbol

V_OH

Parameter

Output Voltage High

Output Voltage Low

Statistical Measurement on

Single-ended Signal using

Oscilliscope Math Function

300

950

mV

V_OL

-100

V_MAX

V_MIN

Absolute Max. Output Voltage^{[5], [6]}

1150

mV

, [7]

Absolute Min. Output Voltage ^[5]

-300

150

, [8], [9]

V_CROSS

Absolute Crossing Voltage ^[5]

550

140

,

, [10]

V_CROSSTotal Variation of V_CROSSover all Edges ^{[5] [8]}

Edge Rate

Rising Edge Rate^{[11], [12]}

0.3

4.5

V/ns

Rise

Edge Rate

Fall

,

Falling Edge Rate^{[11] [12]}

1. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal

equilibrium has been reached under these conditions.

2. Guaranteed by design and Characterization, not 100% tested in production.

3. Test configuration: C_L= 2pF, R_S= 33.2, R_P= 49.9

4. Tested for the following out frequencies: 156.25MHz, 245.76MHz, 312.5MHz, and 625MHz. For other frequencies, contact IDT

Marketing.

5. Measurement taken from a single-ended waveform.

6. Defined as the maximum instantaneous voltage including overshoot.

7. Defined as the minimum instantaneous voltage including undershoot.

8. Measured at crossing point where the instantaneous voltage value of the rising edge of CLK+ equals the falling edge of CLK-.

9. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing

points for this measurement.

10.Defined as the total variation of all crossing voltages of rising CLK+ and falling CLK-. this is the maximum allowed variance in VCROSS

for any particular system.

11.Measurement taken from a differential waveform.

12.Measured from -150mV on the differential waveform (derived from Q minus nQ). the signal must be monotonic through the measurement

region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing.

[1]

Table 23: Typical Additive Jitter, V

= 3.3V ±5%, 2.5V ±5% or 1.8V ±5%, V

= 3.3V ±5%, 2.5V ±5%,

CC

CCOx

1.8V ±5%, V = 0V, T = -40°C to +85°C

EE

A

Symbol Parameter

Test Conditions^[2]

Minimum

Typical

Maximum Units

LVPECL

LVDS

62

82

74

68

65

fs

RMS 

f

_OUT= 156.25MHz,

t_jit(f)

Additive Jitter HCSL

(Random)

Integration Range: 12kHz - 20MHz

CML, 400mV

1. V_CCOxdenotes V_CCOA, V_CCOB

2. All outputs configured for the specific output type, as shown in the table.

.

14

September 1, 2016

8P391208 Datasheet

Applications Information

Recommendations for Unused Input and Output Pins

Inputs:

CLK/nCLK Inputs

For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional

protection, a 1k resistor can be tied from CLK to ground.

LVCMOS LVTTL Level Control Pins

All control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. A 1k

resistor can be used.

LVCMOS 3-Level I/O Control Pins

These pins are 3-level pins and if left unconnected this is interpreted as a valid input selection option (Middle).

Outputs:

Differential Outputs

All unused Differential outputs can be left floating. It is recommended that there is no trace attached.

LVPECL Outputs

All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should

either be left floating or terminated.

LVDS Outputs

All unused LVDS output pairs can be either left floating or terminated with 100 across. If they are left floating, there should be no trace

attached.

15

September 1, 2016

8P391208 Datasheet

Wiring the Differential Input to Accept Single-Ended Levels

Figure 2 shows how a differential input can be wired to accept single ended levels. The reference voltage V₁= V_CC/2 is generated by the bias

resistors R1 and R2. The bypass capacitor (C1) is used to help filter noise on the DC bias. This bias circuit should be located as close to the

input pin as possible. The ratio of R1 and R2 might need to be adjusted to position the V₁in the center of the input voltage swing. For example,

if the input clock swing is 2.5V and V_CC= 3.3V, R1 and R2 value should be adjusted to set V₁at 1.25V. The values below are for when both the

single ended swing and V_CCare at the same voltage. This configuration requires that the sum of the output impedance of the driver (Ro) and

the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the input will attenuate the signal in

half. This can be done in one of two ways. First, R3 and R4 in parallel should equal the transmission line impedance. For most 50

applications, R3 and R4 can be 100. The values of the resistors can be increased to reduce the loading for slower and weaker LVCMOS

driver. When using single-ended signaling, the noise rejection benefits of differential signaling are reduced. Even though the differential input

can handle full rail LVCMOS signaling, it is recommended that the amplitude be reduced while maintaining an edge rate faster than 1V/ns. The

datasheet specifies a lower differential amplitude, however this only applies to differential signals. For single-ended applications, the swing

can be larger, however V_ILcannot be less than -0.3V and V_IHcannot be more than V_CC+ 0.3V. Though some of the recommended

components might not be used, the pads should be placed in the layout. They can be utilized for debugging purposes. The datasheet

specifications are characterized and guaranteed by using a differential signal.

Figure 2: Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels

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September 1, 2016

8P391208 Datasheet

3.3V Differential Clock Input Interface

The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, HCSL and other differential signals. Both V_SWINGand V_OHmust meet the V_PPand V_CMR

input requirements. Figure 3 to Figure 7 show interface examples for the CLK/nCLK input driven by the most common driver types. The input

interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination

requirements. For example, in Figure 3, the input termination applies for IDT open emitter LVHSTL drivers. If you are using an LVHSTL driver

from another vendor, use their termination recommendation.

Figure 3: CLK/nCLK Input Driven by an

Figure 6: CLK/nCLK Input Driven by a

IDT Open Emitter LVHSTL Driver

3.3V LVPECL Driver

3.3V

1.8V

Zo = 50Ω

CLK

Zo = 50Ω

nCLK

Differential

Input

LVHSTL

R1

50Ω

R2

50Ω

IDT

LVHSTL Driver

Figure 4: CLK/nCLK Input Driven by a

Figure 7: CLK/nCLK Input Driven by a

3.3V LVPECL Driver

3.3V HCSL Driver

3.3V

*R3

CLK

nCLK

Differential

Input

*R4

HCSL

Figure 5: CLK/nCLK Input Driven by a 

3.3V LVDS Driver

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September 1, 2016

8P391208 Datasheet

2.5V Differential Clock Input Interface

CLKx/nCLKx accepts LVDS, LVPECL, LVHSTL, HCSL and other differential signals. Both V_SWINGand V_OHmust meet the V_PPand V_CMRinput

requirements. Figure 8 to Figure 12 show interface examples for the CLKx/nCLKx input driven by the most common driver types. The input

interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination

requirements. For example, in Figure 8, the input termination applies for IDT open emitter LVHSTL drivers. If you are using an LVHSTL driver

from another vendor, use their termination recommendation.

Figure 8: CLKx/nCLKx Input Driven by an 

Figure 11: CLKx/nCLKx Input Driven by a 

IDT Open Emitter LVHSTL Driver

2.5V LVPECL Driver

2.5V

1.8V

Zo = 50

CLK

Zo = 50

nCLK

Differential

Input

LVHSTL

R1

50

R2

50

IDT Open Emitter

LVHSTL Driver

Figure 9: CLKx/nCLKx Input Driven by a 

Figure 12: CLKx/nCLKx Input Driven by a 

2.5V LVPECL Driver

2.5V LVDS Driver

Figure 10: CLKx/nCLKx Input Driven by a 

2.5V HCSL Driver

2.5V

Zo = 50Ω

*R3

33Ω

CLK

nCLK

Differential

Input

*R4

33Ω

HCSL

*Optional – R3 and R4 can be 0Ω

R1

50Ω

R2

50Ω

18

September 1, 2016

8P391208 Datasheet

LVDS Driver Termination

For a general LVDS interface, the recommended value for the termination impedance (Z_T) is between 90 and 132. The actual value should

be selected to match the differential impedance (Z₀) of your transmission line. A typical point-to-point LVDS design uses a 100 parallel

resistor at the receiver and a 100 differential transmission-line environment. In order to avoid any transmission-line reflection issues, the

components should be surface mounted and must be placed as close to the receiver as possible. IDT offers a full line of LVDS compliant

devices with two types of output structures: current source and voltage source. The standard termination schematic as shown in Figure 13 can

be used with either type of output structure. Figure 14, which can also be used with both output types, is an optional termination with center tap

capacitance to help filter common mode noise. The capacitor value should be approximately 50pF. If using a non-standard termination, it is

recommended to contact IDT and confirm if the output structure is current source or voltage source type. In addition, since these outputs are

LVDS compatible, the input receiver’s amplitude and common-mode input range should be verified for compatibility with the output.

Figure 13: Standard LVDS Termination

Z_O Z_T

LVDS

Driver

LVDS

Receiver

Z_T

Figure 14: Optional LVDS Termination

Z

T

2

Z_O Z_T

LVDS

Driver

Receiver

C

Z

2

19

September 1, 2016

8P391208 Datasheet

Termination for 3.3V LVPECL Outputs

The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended

only as guidelines.

The differential output is a low impedance follower output that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC

current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines.

Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figure 15 and Figure 16

show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended

that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.

Figure 15: 3.3V LVPECL Output Termination

Figure 16: 3.3V LVPECL Output Termination

3.3V

R3

R4

125

3.3V

Z_o= 50

+

_

Input

R1

84

R2

84

20

September 1, 2016

8P391208 Datasheet

Termination for 2.5V LVPECL Outputs

Figure 17 and Figure 18 show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to 

V_CCO– 2V. For V_CCO= 2.5V, the V_CCO– 2V is very close to ground level. The R3 in Figure 18 can be eliminated and the termination is shown

in Figure 19.

Figure 17: 2.5V LVPECL Driver Termination Example

2.5V

V_CCO= 2.5V

R1

R3

250

50

+

–

2.5V LVPECL Driver

R2

62.5

R4

62.5

Figure 18: 2.5V LVPECL Driver Termination Example

2.5V

V_CCO= 2.5V

50

+

50

–

2.5V LVPECL Driver

R1

50

R2

50

Figure 19: 2.5V LVPECL Driver Termination Example

2.5V

V_CCO= 2.5V

50

+

50

–

2.5V LVPECL Driver

R1

50

R2

50

R3

18

21

September 1, 2016

8P391208 Datasheet

Recommended Termination for HCSL Outputs

Figure 20 is the recommended source termination for applications where the driver and receiver will be on a separate PCBs. This termination

is the standard for PCI Express™ and HCSL output types. All traces should be 50Ω impedance single-ended or 100Ω differential.

Figure 21 is the recommended termination for applications where a point-to-point connection can be used. A point-to-point connection

contains both the driver and the receiver on the same PCB. With a matched termination at the receiver, transmission-line reflections will be

minimized. In addition, a series resistor (Rs) at the driver offers flexibility and can help dampen unwanted reflections. The optional resistor can

range from 0Ω to 33Ω. All traces should be 50Ω impedance single-ended or 100Ω differential.

Figure 20: Recommended Source Termination (where the driver and receiver will be on separate PCBs)

Rs

0.5" Max

L1

0-0.2"

L2

1-14"

L4

0.5 - 3.5"

L5

22 to 33 +/-5%

L1

L2

L4

L5

PCI Express

Connector

PCI Express

Driver

PCI Express

Add-in Card

0-0.2" L3

L3

49.9 +/- 5%

Rt

Figure 21: Recommended Termination (where a point-to-point connection can be used)

Rs

0.5" Max

L1

0-18"

L2

0-0.2"

L3

0 to 33

L1

L2

L3

PCI Express

Driver

49.9 +/- 5%

Rt

22

September 1, 2016

8P391208 Datasheet

CML Termination

Figure 22 shows an example of the termination for a CML driver. In this example, the transmission line characteristic impedance is 50. The

R1 and R2 50 matched load terminations are pulled up to V_DDO.The matched loads are located close to the receiver.

Figure 22: CML Termination Example

VDDO

R1

50

R2

50

Zo = 50

CML Driver

23

September 1, 2016

8P391208 Datasheet

Power Dissipation and Thermal Considerations

The 8P391208 is a multi-functional, high speed device that targets a wide variety of clock frequencies and applications. Since this device is

highly programmable with a broad range of features and functionality, the power consumption will vary as each of these features and functions

is enabled.

The 8P391208 device was designed and characterized to operate within the ambient industrial temperature range of 

T_A= -40°C to +85°C. The ambient temperature represents the temperature around the device, not the junction temperature. When using the

device in extreme cases, such as maximum operating frequency and high ambient temperature, external air flow may be required in order to

ensure a safe and reliable junction temperature. Extreme care must be taken to avoid exceeding 125°C junction temperature.

The power calculation examples below were generated using a maximum ambient temperature and supply voltage. For many applications, the

power consumption will be much lower. Please contact IDT technical support for any concerns on calculating the power dissipation for your

own specific configuration.

Power Domains

The 8P391208 device has a number of separate power domains that can be independently enabled and disabled via register accesses (all

power supply pins must still be connected to a valid supply voltage). Figure 23 below indicates the individual domains and the associated

power pins.

Figure 23: 8P391208 Power Domains

24

September 1, 2016

8P391208 Datasheet

Power Consumption Calculation

Determining total power consumption involves several steps:

1. Determine the power consumption using maximum current values for core voltage from Table 6, Table 7, Table 8 and Table 9, Page 7 for

the appropriate case of how many banks or outputs are enabled.

2. Determine the nominal power consumption of each enabled output path.

a. This consists of a base amount of power that is independent of operating frequency, as shown in Table 25 through Table 36 (depending

on the chosen output protocol).

b. Then there is a variable amount of power that is related to the output frequency. This can be determined by multiplying the output

frequency by the FQ_Factor shown in Table 25 through Table 36.

3. All of the above totals are then summed.

Thermal Considerations

Once the total power consumption has been determined, it is necessary to calculate the maximum operating junction temperature for the

device under the environmental conditions it will operate in. Thermal conduction paths, air flow rate and ambient air temperature are factors

that can affect this. The thermal conduction path refers to whether heat is to be conducted away via a heat-sink, via airflow or via conduction

into the PCB through the device pads (including the ePAD). Thermal conduction data is provided for typical scenarios in Table 42, Page 36.

Please contact IDT for assistance in calculating results under other scenarios.

Table 24: _JAvs. Air Flow Table for a 32-lead 5mm x 5mm VFQFN

_JAvs. Air Flow

Meters per Second

0

1

2

Multi-Layer PCB, JEDEC Standard Test Boards

35.23°C/W

31.6°C/W

30.0°C/W

25

September 1, 2016

8P391208 Datasheet

Current Consumption Data and Equations

Table 25: 3.3V LVDS Output Calculation Table

Table 28: 3.3V LVPECL Output Calculation Table

FQ_Factor

(mA/MHz)

FQ_Factor

(mA/MHz)

LVDS

Base_Current (mA)

LVPECL

Base_Current (mA)

Bank A

Bank B

0.07

30.0

Bank A

Bank B

0.04

22.0

Table 26: 2.5V LVDS Output Calculation Table

Table 29: 2.5V LVPECL Output Calculation Table

FQ_Factor

(mA/MHz)

FQ_Factor

(mA/MHz)

LVDS

Base_Current (mA)

LVPECL

Base_Current (mA)

Bank A

Bank B

0.07

26.0

Bank A

Bank B

0.04

21.0

Table 27: 1.8V LVDS Output Calculation Table

Table 30: 1.8V LVPECL Output Calculation Table

FQ_Factor

(mA/MHz)

FQ_Factor

(mA/MHz)

LVDS

Base_Current (mA)

LVPECL

Base_Current (mA)

Bank A

Bank B

0.06

38.0

Bank A

Bank B

0.04

20.0

26

September 1, 2016

8P391208 Datasheet

Table 31: 3.3V CML Output (400mV) Calculation

Table

Table 34: 3.3V CML Output (800mV) Calculation

Table

CML (400mV)

FQ_Factor (mA/MHz)

Base_Current (mA)

FQ_Factor

(mA/MHz)

CML (800mV)

Base_Current (mA)

Bank A

Bank B

0.02

19.0

Bank A

Bank B

0.02

19.0

Table 32: 2.5V CML Output (400mV) Calculation

Table

Table 35: 2.5V CML Output (800mV) Calculation

Table

FQ_Factor

CML (400mV)

(mA/MHz)

Base_Current (mA)

CML (800mV) FQ_Factor (mA/MHz)

Base_Current (mA)

Bank A

Bank B

0.02

16.0

Bank A

Bank B

0.02

16.0

Table 33: 1.8V CML Output (400mV) Calculation

Table

Table 36: 1.8V CML Output (800mV) Calculation

Table

FQ_Factor

(mA/MHz)

CML (800mV) FQ_Factor (mA/MHz)

Base_Current (mA)

CML (400mV)

Base_Current (mA)

Bank A

Bank B

0.02

15.0

Bank A

Bank B

0.02

15.0

27

September 1, 2016

8P391208 Datasheet

Applying the values to the following equation will yield output current by frequency:

Qx Current (mA) = FQ_Factor * Frequency (MHz) + Base_Current

where:

Qx Current is the specific output current according to output type and frequency

FQ_Factor is used for calculating current increase due to output frequency

Base_Current is the base current for each output path independent of output frequency

The second step is to multiply the power dissipated by the thermal impedance to determine the maximum power gradient, using the following

equation:

T_J= T_A+ (_JA* Pd_total

where:

)

T_Jis the junction temperature (°C)

T_Ais the ambient temperature (°C)



_JAis the thermal resistance value from Table 42, Page 36, dependent on ambient airflow (°C/W)

Pd_totalis the total power dissipation of the 8P391208 under usage conditions, including power dissipated due to loading (W)

Note that for LVPECL outputs the power dissipation through the load is assumed to be 27.95mW).

Example Calculations

Table 37: Example 1 – Common Customer Configuration (3.3V Core Voltage)

Circuit

Configuration

Frequency (MHz)

V_CCO

Bank A

Bank B

LVDS

3.3V

125

• Core Supply Current, I_CC= 25mA (maximum)

Output Supply Current, Bank A Current = 0.07mA x 125MHz + 30mA = 38.75mA

Output Supply Current, Bank B Current = 0.07mA x 125MHz + 30mA = 38.75mA

• Total Device Current = 25mA + 38.75mA + 38.75mA = 102.5mA

• Total Device Power = 3.465V * 102.5mA = 355.2mW or 0.3552W

With an ambient temperature of 85°C and no airflow, the junction temperature is:

T_J= 85°C + 35.23°C/W * 0.3552W = 97.5°C

28

September 1, 2016

8P391208 Datasheet

LVDS Power Considerations

This section provides information on power dissipation and junction temperature for the 8P391208. 

Equations and example calculations are also provided.

1. Power Dissipation.

The total power dissipation for the 8P391208 is the sum of the core power plus the power dissipated in the load(s). 

The following is the power dissipation for V_CC= 3.3V + 5% = 3.465V, which gives worst case results.

• Power (core)_MAX= V_{CC_MAX}* I_{CC_MAX}= 3.465V * 25mA = 86.625mW

• Power (outputs)_MAX= V_{CCO_MAX}* I_{CCO_MAX}= 3.465V * 157mA = 544.005mW

• Total Power__MAX= 86.625mW + 544.005mW = 630.63mW

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The

maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the

bond wire and bond pad temperature remains below 125°C.

The equation for Tj is as follows: Tj = _JA* Pd_total + T_A

Tj = Junction Temperature



_JA= Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

T_A= Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance _JAmust be used. Assuming no air flow and

a multi-layer board, the appropriate value is 35.23°C/W per Table 38 below.

Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:

85°C + 0.631W *35.23°C/W = 107.2°C. This is below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of

board (multi-layer).

Table 38: Thermal Resistance  for 32-lead 5mm x 5mm VFQFN, Forced Convection

JA

_JAby Velocity

Meters per Second

0

1

2

Multi-Layer PCB, JEDEC Standard Test Boards

35.23°C/W

31.6°C/W

30.0°C/W

29

September 1, 2016

8P391208 Datasheet

LVPECL Power Considerations

This section provides information on power dissipation and junction temperature for the 8P391208. 

Equations and example calculations are also provided.

1. Power Dissipation.

The total power dissipation for the 8P391208 is the sum of the core power plus the power dissipated in the load(s). 

The following is the power dissipation for V_CC+ 5% = 3.465V, which gives worst case results.

NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

• Power (core)_MAX= V_{CC_MAX}* I_{CC_MAX}= 3.465V * 128.1mA = 443.9mW

• Power (outputs)_MAX= 27.95mW/Loaded Output pair

If all outputs are loaded, the total power is 8 * 27.95mW = 223.6mW

• Total Power__MAX(3.465V, with all outputs switching) = 443.9W + 223.6mW = 667.5mW

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The

maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the

bond wire and bond pad temperature remains below 125°C.

The equation for Tj is as follows: Tj = _JA* Pd_total + T_A

Tj = Junction Temperature



_JA= Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

T_A= Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance _JAmust be used. Assuming no air flow and

a multi-layer board, the appropriate value is 35.23°C/W per Table 39 below.

Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:

85°C + 0.6675 W * 35.23°C/W = 108.5°C. This is below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of

board (multi-layer).

Table 39: Thermal Resistance  for 32-lead 5mm x 5mm VFQFN, Forced Convection

JA



_JAby Velocity

Meters per Second

0

1

2

Multi-Layer PCB, JEDEC Standard Test Boards

35.23°C/W

31.6°C/W

30.0°C/W

30

September 1, 2016

8P391208 Datasheet

3. Calculations and Equations.

The purpose of this section is to calculate the power dissipation for the LVPECL output pair.

LVPECL output driver circuit and termination are shown in Figure 24.

Figure 24: LVPECL Driver Circuit and Termination

V_CCO

Q1

V_OUT

RL

50Ω

V_CCO- 2V

To calculate power dissipation per output pair due to loading, use the following equations which assume a 50 load, and a termination voltage

of V_CCO– 2V.

•

For logic high, V_OUT= V_{OH_MAX}= V_{CCO_MAX}– 0.8V

(V_{CCO_MAX}– V_{OH_MAX}) = 0.8V

For logic low, V_OUT= V_{OL_MAX}= V_{CCO_MAX}– 1.75V

(V_{CCO_MAX}– V_{OL_MAX}) = 1.75V

Pd_H is power dissipation when the output drives high.

Pd_L is the power dissipation when the output drives low.

Pd_H = [(V_{OH_MA –}(V_{CCO_MA –}2V))/R_L] * (V_{CCO_MA –}V_{OH_MAX}) = [(2V – (V_{CCO_MAX}– V_{OH_MAX}))/R_L] * (V_{CCO_MAX}– V_{OH_MAX}) =

[(2V – 0.8V)/50] * 0.8V = 19.2mW

Pd_L = [(V_{OL_MAX}– (V_{CCO_MAX}– 2V))/R_L] * (V_{CCO_MA –}V_{OL_MAX}) = [(2V – (V_{CCO_MAX}– V_{OL_MAX}))/R_L] * (V_{CCO_MAX}– V_{OL_MAX}) =

[(2V – 1.75V)/50] * 1.75V = 8.75mW

Total Power Dissipation per output pair = Pd_H + Pd_L = 27.95mW

31

September 1, 2016

8P391208 Datasheet

HCSL Power Considerations

This section provides information on power dissipation and junction temperature for the 8P391208. 

Equations and example calculations are also provided.

1. Power Dissipation.

The total power dissipation for the 8P391208 is the sum of the core power plus the power dissipated in the load(s). 

The following is the power dissipation for V_CC= 3.3V + 5% = 3.465V, which gives worst case results.

NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

• Power (core)_MAX= V_{CC_MAX}* I_{CC_MAX}= 3.465V * 23.60mA = 81.774mW

• Power (outputs)_MAX= 44.5mW/Loaded Output pair

If all outputs are loaded, the total power is 8 * 44.5mW = 356.0mW

• Total Power__MAX= 81.774mW + 356.0mW = 437.77mW

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The

maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the

bond wire and bond pad temperature remains below 125°C.

The equation for Tj is as follows: Tj = _JA* Pd_total + T_A

Tj = Junction Temperature



_JA= Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

T_A= Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance _JAmust be used. Assuming no air flow and

a multi-layer board, the appropriate value is 35.23°C/W per Table 40 below.

Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:

85°C + 0.4378W * 35.23°C/W = 100.42°C. This is below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of

board (multi-layer).

Table 40: Thermal Resistance  for 32-lead 5mm x 5mm VFQFN, Forced Convection

JA

_JAby Velocity

Meters per Second

0

1

2

Multi-Layer PCB, JEDEC Standard Test Boards

35.23°C/W

31.6°C/W

30.0°C/W

32

September 1, 2016

8P391208 Datasheet

3. Calculations and Equations.

The purpose of this section is to calculate power dissipation on the IC per HCSL output pair.

HCSL output driver circuit and termination are shown in Figure 25.

Figure 25: HCSL Driver Circuit and Termination

VCCO

I_OUT= 17mA

V_OUT

R_REF

=

475: 1ꢀ

R_L

50:

IC

HCSL is a current steering output which sources a maximum of 17mA of current per output. To calculate worst case on-chip power dissipation,

use the following equations which assume a 50 load to ground.

The highest power dissipation occurs when V_CCO

_

.

MAX

Power= (V_{CCO_MAX}– V_OUT) * I_OUT, since V_OUT– I_OUT* R_L

= (V_{CCO_MAX – OUT}* R_L) * I_OUT

I

= (3.465V – 17mA * 50) * 17mA

Total Power Dissipation per output pair = 44.5mW

33

September 1, 2016

8P391208 Datasheet

CML Power Considerations (400mV - 800mV)

This section provides information on power dissipation and junction temperature for the 8P391208. 

Equations and example calculations are also provided.

1. Power Dissipation.

The total power dissipation for the 8P391208 is the sum of the core power plus the power dissipation in the load(s). 

The following is the power dissipation for V_CC= 3.3V + 5% = 3.465V, which gives worst case results.

NOTE: Please refer to Section 3 for details on calculating power dissipation in the load.

• Power (core)_MAX= V_{CC_MAX}* I_{CC_MAX}= 3.465V * 26.35mA = 91.30mW

• Power (outputs)_MAX= V_{CCO_MAX}* I_{CCO_MAX}= 3.465V * 68.66mA = 237.91mW

If all outputs are loaded, the total power is 8 * 56.03mW = 448.24mW

• Total Power__MAX(3.465V, with all outputs switching) = 91.30mW + 237.91mW + 448.24mW = 777.45mW

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The

maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the

bond wire and bond pad temperature remains below 125°C.

The equation for Tj is as follows: Tj = _JA* Pd_total + T_A

Tj = Junction Temperature



_JA= Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

T_A= Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance _JAmust be used. Assuming no air flow and

a multi-layer board, the appropriate value is 35.23°C/W per Table 41 below.

Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:

85°C + 0.777W * 35.23°C/W = 112.4°C. This is well below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of

board (multi-layer).

Table 41: Thermal Resistance  for 32-lead 5mm x 5mm VFQFN, Forced Convection

JA

_JAby Velocity

Meters per Second

0

1

2

Multi-Layer PCB, JEDEC Standard Test Boards

35.23°C/W

31.6°C/W

30.0°C/W

34

September 1, 2016

8P391208 Datasheet

3. Calculations and Equations.

The purpose of this section is to calculate the power dissipation for the CML driver output pair. The CML output circuit and termination are

shown in Figure 26.

Figure 26: CML Driver (without built-in 50 pullup) Circuit and Termination

VCCO

RL1

50

RL2

50

Q

nQ

V_output

Q1

Q2

I_load

External Loads

IC

To calculate worst case power dissipation due to the load, use the following equations.

Power dissipation when the output driver is logic LOW:

Pd_L = _Load * V_Output

= (V_{OUT_MAX}/R_L)* (V_{CCO_MAX}– V_{OUT_MAX})

= (1000mV/50) * (3.465V – 1000mV)

= 49.3mW

Power dissipation when the output driver is logic HIGH:

Pd_H = I_Load * V_Output

= (0.1V/50) * (3.465V – 0.1V)

= 6.73mW

Total Power Dissipation per output pair = Pd_H + Pd_L = 56.03mW

35

September 1, 2016

8P391208 Datasheet

Reliability Information

Table 42: _JAvs. Air Flow Table for a 32-lead 5mm x 5mm VFQFN

_JAvs. Air Flow

Meters per Second

0

1

2

Multi-Layer PCB, JEDEC Standard Test Boards

35.23°C/W

31.6°C/W

30.0°C/W

Transistor Count

The 8P391208 transistor count is: 6930

36

September 1, 2016

8P391208 Datasheet

32-Lead VFQFN Package Outline and Package Dimensions

37

September 1, 2016

8P391208 Datasheet

32-Lead VFQFN Package Outline and Package Dimensions (Continued)

38

September 1, 2016

8P391208 Datasheet

Ordering Information

Part/Order Number

Marking

Package

Shipping Packaging

Temperature

8P391208NLGI

IDT8P391208NLGI

32-lead VFQFN, Lead Free

Tray

-40°C to +85°C

Tape & Reel, Pin 1

Orientation: EIA-481-C

8P391208NLGI8

8P391208NLGI/W

32-lead VFQFN, Lead Free

-40°C to +85°C

Tape & Reel, Pin 1

Orientation: EIA-481-D

IDT8P391208NLGI

Table 43: Pin 1 Orientation in Tape and Reel Packaging

Part Number Suffix

Pin 1 Orientation

Illustration

CARRIER TAPE TOPSIDE

(Round Sprocket Holes)

Correct Pin 1 ORIENTATION

NLGI8

Quadrant 1 (EIA-481-C)

USER DIRECTION OF FEED

CARRIER TAPE TOPSIDE

(Round Sprocket Holes)

Correct Pin 1 ORIENTATION

NLGI/W

Quadrant 2 (EIA-481-D)

USER DIRECTION OF FEED

39

September 1, 2016

8P391208 Datasheet

Revision History

Revision Date

Description of Change

September 1, 2016

Initial Final datasheet release.

40

September 1, 2016

8P391208 Datasheet

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DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document,

including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are

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型号：	8P391208
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	Low Additive Jitter 2:8 Buffer with Universal Differential Outputs
文件：	总41页 (文件大小：919K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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