8SLVD2104 [IDT]
Dual 1:4, LVDS Output Fanout Buffer;
| 型号： | 8SLVD2104 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Dual 1:4, LVDS Output Fanout Buffer |
| 文件： | 总16页 (文件大小：436K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual 1:4, LVDS Output Fanout Buffer
8SLVD2104
DATA SHEET
Features
General Description
• Two 1:4, low skew, low additive jitter LVDS fanout buffers
The 8SLVD2104 is a high-performance differential dual 1:4 LVDS
fanout buffer. The device is designed for the fanout of high-frequency,
very low additive phase-noise clock and data signals. The
• Two differential clock inputs
• Differential pairs can accept the following differential input
levels: LVDS and LVPECL
8SLVD2104 is characterized to operate from a 2.5V power supply.
Guaranteed output-to-output and part-to-part skew characteristics
make the 8SLVD2104 ideal for those clock distribution applications
demanding well-defined performance and repeatability. Two
independent buffers with four low skew outputs each are available.
The integrated bias voltage generators enables easy interfacing of
single-ended signals to the device inputs. The device is optimized for
low power consumption and low additive phase noise.
• Maximum input clock frequency: 2GHz
• Output bank skew: 35ps, (maximum)
• Propagation delay: 300ps, (maximum)
• Low additive RMS phase jitter, 156.25MHz (10kHz - 20MHz):
105fs, (maximum)
•
2.5V supply voltage
• Lead-free (RoHS 6) 28-Lead VFQFN package
• -40°C to 85°C ambient operating temperature
Block Diagram
Pin Assignment
28 27 26 25 24 23 22
1
2
3
4
5
6
7
GND
QB3
nQA3
21
20 QA3
nQB3
19 nQA2
8SLVD2104
EN
PCLKB
QA2
nQA1
QA1
18
17
nPCLKB
16
15
VDD
VREFB
8
9 10 11 12 13 14
28-Lead, 5mm x 5mm VFQFN
8SLVD2104 REVISION 1 08/03/15
1
©2015 Integrated Device Technology, Inc.
8SLVD2104 DATA SHEET
Pin Description and Pin Characteristic Tables
1
Table 1. Pin Descriptions
Number
Name
GND
QB3
Type
Description
1
2
3
Power
Output
Output
Power supply ground.
Differential output pair B3. LVDS interface levels.
nQB3
Pullup/
Pulldown
4
5
6
EN
Input
Input
Input
Output enable pin. VDD/2 default when left floating.
Non-inverting differential clock/data input.
PCLKB
nPCLKB
Pulldown
Pullup/
Pulldown
Inverting differential clock/data input. VDD/2 default when left floating.
7
8
9
VREFB
VDD
Output
Power
Input
Bias voltage reference for the PCLKB, nPCLKB input pair.
Power supply pin.
PCLKA
Pulldown
Non-inverting differential clock/data input.
Pullup/
Pulldown
10
nPCLKA
Input
Inverting differential clock/data input. VDD/2 default when left floating.
Bias voltage reference for the PCLKA, nPCLKA input pair.
11
12,
13
14
15
16
17
18,
19
20
21
22
23
24
25
26
27
28
VREFA
QA0
Output
Output
Output
Power
Power
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Power
Differential output pair A0. LVDS interface levels.
nQA0
GND
VDD
Power supply ground.
Power supply pin.
QA1
Differential output pair A1. LVDS interface levels.
Differential output pair A2. LVDS interface levels.
Differential output pair A3. LVDS interface levels.
Differential output pair B0. LVDS interface levels.
Differential output pair B1. LVDS interface levels.
Differential output pair B2. LVDS interface levels.
nQA1
QA2
nQA2
QA3
nQA3
QB0
nQB0
QB1
nQB1
QB2
nQB2
VDD
Power supply pin.
ePAD
Thermal pad. Connect to ground.
NOTE 1: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
DUAL 1:4, LVDS OUTPUT FANOUT BUFFER
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REVISION 1 08/03/15
8SLVD2104 DATA SHEET
Table 2. Pin Characteristics
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
CIN
Input Capacitance
2
pF
EN,
PCLK[A:B],
nPCLK[A:B]
Input Pulldown
Resistor
RPULLDOWN
51
51
k
k
Input Pullup
Resistor
EN,
nPCLK[A:B]
RPULLUP
Function Table
Table 3. EN Input Selection Function Table
1
Input
EN
Operation
Outputs are disabled and static at Qx = 0 (low level) and nQx = 1 (high level).
0 (Low)
Bank A outputs are enabled and Bank B outputs are disabled at the following static levels:
QBx = 0 (low level) and nQBx = 1 (high level).
1 (High)
Open
All outputs enabled.
NOTE 1: EN is an asynchronous control input pin.
REVISION 1 08/03/15
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DUAL 1:4, LVDS OUTPUT FANOUT BUFFER
8SLVD2104 DATA SHEET
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Electrical Characteristics
or AC Electrical Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product
reliability.
Item
Rating
Supply Voltage, VDD
Inputs, VI
4.6V
-0.5V to VDD + 0.5V
Outputs, IO (LVDS)
Continuous Current
Surge Current
10mA
15mA
Maximum Junction Temperature, TJ,MAX
Storage Temperature, TSTG
125C
-65C to 150C
2000V
ESD - Human Body Model1
ESD - Charged Device Model1
1500V
NOTE 1: According to JEDEC/JESD JS-001-2012/22-C101E.
DC Electrical Characteristics
Table 4A. Power Supply Characteristics, V = 2.5V 5%, T = -40°C to 85°C
1
DD
A
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VDD
Power Supply Voltage
2.375
2.5
2.625
V
All outputs terminated with 100 in
between nQx, Qx; DC to 2GHz
IDD
Power Supply Current
145
170
mA
NOTE 1: Qx, nQx denotes QA[3:0], nQA[3:30], and QB[3:0], nQB[3:0].
Table 4B. LVCMOS/LVTTL Input Characteristics, V = 2.5V 5%, T = -40°C to 85°C
DD
A
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
Input Voltage -
Open Pin
VMID
EN
Open
V
DD / 2
V
VIH
VIL
IIH
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
EN
EN
EN
EN
0.7 * VDD
-0.3
VDD + 0.3
0.2 * VDD
150
V
V
VDD = VIN = 2.625V
µA
µA
IIL
VDD = 2.625V, VIN = 0V
-150
DUAL 1:4, LVDS OUTPUT FANOUT BUFFER
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REVISION 1 08/03/15
8SLVD2104 DATA SHEET
Table 4C. Differential Input Characteristics, V = 2.5V 5%, T = -40°C to 85°C
DD
A
Symbol
Parameter
Test Conditions
DD = VIN = 2.625V
DD = 2.625V, VIN = 0V
Minimum
Typical
Maximum
Units
Input High PCLKA, nPCLKA
Current
IIH
V
150
µA
PCLKB, nPCLKB
PCLKA, PCLKB
nPCLKA, nPCLKB
V
-10
µA
µA
Input Low
Current
IIL
VDD = 2.625V, VIN = 0V
DD = 2.5V; IREF = +100µA
-150
VREFA,
VREFB
Reference Voltages
for Input Bias
V
1.0
1.35
V
fREF < 1.5 GHz
fREF > 1.5 GHz
0.15
0.2
1.6
1.6
V
V
V
VPP
Peak-to-Peak Voltage1
VCMR
Common Mode Input Voltage1, 2
1.0
VDD – VPP/2
NOTE 1: VIL should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined at the crosspoint.
,
1, 2
Table 4D. LVDS Output DC Characteristics, V = 2.5V 5%, T = -40°C to 85°C
DD
A
Symbol
VOD
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
mV
mV
V
Differential Output Voltage
VOD Magnitude Change
Offset Voltage
247
454
50
VOD
VOS
1.0
1.4
50
VOS
VOS Magnitude Change
mV
NOTE 1: Qx, nQx denotes QA[3:0], nQA[3:30], and QB[3:0], nQB[3:0].
NOTE 2: 100 termination across differential outputs.
REVISION 1 08/03/15
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DUAL 1:4, LVDS OUTPUT FANOUT BUFFER
8SLVD2104 DATA SHEET
AC Electrical Characteristics
1
Table 5. AC Electrical Characteristics, VDD = 2.5V 5%, T = -40°C to 85°C
A
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
GHz
V/ns
fREF
Input Frequency
2
V/t
Input Edge Rate
0.75
100
PCLKA, nPCLKA to QA[3:0], nQA[3:0]
PCLKB, nPCLKB to QB[3:0], nQB[3:0]
tPD
Propagation Delay2
196
300
ps
Channel Isolation
Output Skew4, 5, 6
Output Bank Skew4, 5
Pulse Skew
NOTE3
Any Output
65
20
17
dB
ps
ps
ps
ps
tsk(o)
tsk(b)
tsk(p)
tsk(pp)
40
35
Within QA[3:0] or QB[3:0] Outputs
f
REF = 100MHz
-50
50
Part-to-Part Skew5, 7
200
f
f
f
REF = 156.25MHz Square Wave, VPP = 1V,
90
70
125
105
105
165
130
130
fs
fs
fs
fs
fs
fs
Integration Range: 1kHz – 40MHz
REF = 156.25MHz Square Wave, VPP = 1V,
Integration Range: 10kHz – 20MHz
REF = 156.25MHz Square Wave, VPP = 1V,
Integration Range: 12kHz – 20MHz
70
Buffer Additive Phase Jitter,
RMS; refer to Additive Phase
Jitter Section
tJIT
fREF = 156.25MHz Square Wave, VPP
=
100
72
0.5V, Integration Range: 1kHz – 40MHz
fREF = 156.25MHz Square Wave, VPP
=
0.5V, Integration Range: 10kHz – 20MHz
fREF = 156.25MHz Square Wave, VPP
=
72
0.5V, Integration Range: 12kHz – 20MHz
f
QB0 = 500MHz, VPP (PCLKB) = 0.15V,
CMR(PCLKB) = 1 V and fQA1 = 62.5MHz,
PP(PCLKA) = 1.0V, VCMR(PCLKA) = 1V
V
67
dB
V
Spurious suppression, coupling
from QA3 to QB0
tJIT, SP
fQB0 = 500MHz, VPP (PCLKB) = 0.15V,
CMR(PCLKB) = 1V and fQA1 = 15.625MHz,
V
80
dB
ps
VPP (PCLKA) = 1.0V, VCMR(PCLKA) = 1V
tR / tF
Output Rise/ Fall Time
20% to 80%
120
225
NOTE 1: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE 2: Measured from the differential input crossing point to the differential output crossing point.
NOTE 3: Channel Isolation is defined as the output amplitude delta between the measured output with active input and the same output
with inactive input when the other channel is active.
NOTE 4: Defined as skew among outputs at the same supply voltage and with equal load conditions. Measured at the differential cross point.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: Both PCLKA, nPCLKA and PCLKB, nPCLKB inputs are phase aligned.
NOTE 7: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using
the same type of inputs on each device, the outputs are measured at the differential cross point.
DUAL 1:4, LVDS OUTPUT FANOUT BUFFER
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REVISION 1 08/03/15
8SLVD2104 DATA SHEET
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
Offset Frequency (Hz)
As with most timing specifications, phase noise measurements have
issues relating to the limitations of the measurement equipment. The
noise floor of the equipment can be higher or lower than the noise
floor of the device. Additive phase noise is dependent on both the
noise floor of the input source and measurement equipment.
Additive phase jitter was measured with a Wenzel 156.25MHz
oscillator as the input source.
REVISION 1 08/03/15
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DUAL 1:4, LVDS OUTPUT FANOUT BUFFER
8SLVD2104 DATA SHEET
Applications Information
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
PCLK/nPCLK Inputs
LVDS Outputs
For applications not requiring the use of a differential input, both the
PCLK and nPCLK pins can be left floating. Though not required, but
for additional protection, a 1k resistor can be tied from PCLK to
ground.
All unused LVDS output pairs can be either left floating or terminated
with 100 across. If they are left floating, there should be no trace
attached.
VREFX
Unused VREFA and VREFB pins can be left floating. We recommend
that there is no trace attached.
Wiring the Differential Input to Accept Single-Ended Levels
Figure 1 shows how a differential input can be wired to accept single
ended levels. The reference voltage V1= VDD/2 is generated by the
bias resistors R1 and R2. The bypass capacitor (C1) is used to help
filter noise on the DC bias. This bias circuit should be located as close
to the input pin as possible. The ratio of R1 and R2 might need to be
adjusted to position the V1in the center of the input voltage swing. For
example, if the input clock is driven from a single-ended 2.5V
LVCMOS driver and the DC offset (or swing center) of this signal is
1.25V, the R1 and R2 values should be adjusted to set the V1 at
1.25V. The values below are for when both the single ended swing
and VDD are at the same voltage. This configuration requires that the
sum of the output impedance of the driver (Ro) and the series
resistance (Rs) equals the transmission line impedance. In addition,
matched termination at the input will attenuate the signal in half. This
can be done in one of two ways. First, R3 and R4 in parallel should
equal the transmission line impedance. For most 50 applications,
R3 and R4 can be 100. The values of the resistors can be increased
to reduce the loading for slower and weaker LVCMOS driver. When
using single-ended signaling, the noise rejection benefits of
differential signaling are reduced. Even though the differential input
can handle full rail LVCMOS signaling, it is recommended that the
amplitude be reduced while maintaining an edge rate faster than
1V/ns. The datasheet specifies a lower differential amplitude,
however this only applies to differential signals. For single-ended
applications, the swing can be larger, however VIL cannot be less
than -0.3V and VIH cannot be more than VDD + 0.3V. Though some
of the recommended components might not be used, the pads
should be placed in the layout. They can be utilized for debugging
purposes. The datasheet specifications are characterized and
guaranteed by using a differential signal.
Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels
DUAL 1:4, LVDS OUTPUT FANOUT BUFFER
8
REVISION 1 08/03/15
8SLVD2104 DATA SHEET
2.5V LVPECL Clock Input Interface
The PCLK /nPCLK accepts LVPECL, LVDS, and other differential
signals. Both signals must meet the VPP and VCMR input
requirements. Figure 2A to Figure 2D show interface examples for
the PCLK/ nPCLK input driven by the most common driver types. The
input interfaces suggested here are examples only. If the driver is
from another vendor, use their termination recommendation. Please
consult with the vendor of the driver component to confirm the driver
termination requirements.
2.5V
2.5V
2.5V
PCLK
PCLK
nPCLK
nPCLK
LVPECL
LVPECL
Input
Figure 2A. PCLK/nPCLK Input Driven by a
Figure 2C. PCLK/nPCLK Input Driven by a
2.5V LVPECL Driver
2.5V LVDS Driver
2.5V
2.5V
C1
C2
Zo = 50Ω
Zo = 50Ω
2.5V LVPECL
PCLK
V
REF
nPCLK
LVPECL
Input
R5
100Ω - 200Ω 100Ω - 200Ω
R6
R1
50Ω
R2
50Ω
Figure 2B. PCLK/nPCLK Input Driven by a
Figure 2D. PCLK/nPCLK Input Driven by a 2.5V
LVPECL Driver AC Couple with V bias
2.5V LVPECL Driver with AC Couple
REF
REVISION 1 08/03/15
9
DUAL 1:4, LVDS OUTPUT FANOUT BUFFER
8SLVD2104 DATA SHEET
LVDS Driver Termination
For a general LVDS interface, the recommended value for the
termination impedance (ZT) is between 90 and 132. The actual
value should be selected to match the differential impedance (Z0) of
your transmission line. A typical point-to-point LVDS design uses a
100 parallel resistor at the receiver and a 100 differential
transmission-line environment. In order to avoid any
transmission-line reflection issues, the components should be
surface mounted and must be placed as close to the receiver as
possible. IDT offers a full line of LVDS compliant devices with two
types of output structures: current source and voltage source. The
standard termination schematic as shown in Figure 3A can be used
with either type of output structure. Figure 3B, which can also be
used with both output types, is an optional termination with center tap
capacitance to help filter common mode noise. The capacitor value
should be approximately 50pF. If using a non-standard termination, it
is recommended to contact IDT and confirm if the output structure is
current source or voltage source type. In addition, since these
outputs are LVDS compatible, the input receiver’s amplitude and
common-mode input range should be verified for compatibility with
the output.
ZO ZT
LVDS
Driver
LVDS
ZT
Receiver
Figure 3A. Standard LVDS Termination
ZT
2
ZO ZT
LVDS
Driver
LVDS
Receiver
C
ZT
2
Figure 3B. Optional LVDS Termination
DUAL 1:4, LVDS OUTPUT FANOUT BUFFER
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REVISION 1 08/03/15
8SLVD2104 DATA SHEET
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package
corresponding to the exposed metal pad or exposed heat slug on the
package, as shown in Figure 4. The solderable area on the PCB, as
defined by the solder mask, should be at least the same size/shape
as the exposed pad/slug area on the package to maximize the
thermal/electrical performance. Sufficient clearance should be
designed on the PCB between the outer edges of the land pattern
and the inner edges of pad pattern for the leads to avoid any shorts.
and dependent upon the package power dissipation as well as
electrical conductivity requirements. Thus, thermal and electrical
analysis and/or testing are recommended to determine the minimum
number needed. Maximum thermal and electrical performance is
achieved when an array of vias is incorporated in the land pattern. It
is recommended to use as many vias connected to ground as
possible. It is also recommended that the via diameter should be 12
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is
desirable to avoid any solder wicking inside the via during the
soldering process which may result in voids in solder between the
exposed pad/slug and the thermal land. Precautions should be taken
to eliminate any solder voids between the exposed heat slug and the
land pattern. Note: These recommendations are to be used as a
guideline only. For further information, please refer to the Application
Note on the Surface Mount Assembly of Amkor’s Thermally/
Electrically Enhance Leadframe Base Package, Amkor Technology.
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from
the surface of the PCB to the ground plane(s). The land pattern must
be connected to ground through these vias. The vias act as “heat
pipes”. The number of vias (i.e. “heat pipes”) are application specific
SOLDER
PIN
SOLDER
EXPOSED HEAT SLUG
PIN
PIN PAD
GROUND PLANE
LAND PATTERN
(GROUND PAD)
PIN PAD
THERMAL VIA
Figure 4. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
REVISION 1 08/03/15
11
DUAL 1:4, LVDS OUTPUT FANOUT BUFFER
8SLVD2104 DATA SHEET
Power Considerations
This section provides information on power dissipation and junction temperature for the 8SLVD2104. Equations and example calculations are
also provided.
1. Power Dissipation.
The following is the power dissipation for VDD = 2.5V + 5% = 2.625V, which gives worst case results.
Maximum current at 85°C: IDD_MAX = 156mA
•
Power_MAX = VDD_MAX * IDD_MAX = 2.625V * 156mA = 409.5mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 46.2°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.4095W * 46.2°C/W = 103.9°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 6. Thermal Resistance for 28 Lead VFQFN, Forced Convection
JA
JA at 0 Air Flow
Meters per Second
0
1
2
Multi-Layer PCB, JEDEC Standard Test Boards
46.2°C/W
39.4°C/W
37.1°C/W
DUAL 1:4, LVDS OUTPUT FANOUT BUFFER
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REVISION 1 08/03/15
8SLVD2104 DATA SHEET
Reliability Information
Table 7. vs. Air Flow Table for a 28-Lead VFQFN
JA
JA at 0 Air Flow
Meters per Second
0
1
2
Multi-Layer PCB, JEDEC Standard Test Boards
46.2°C/W
39.4°C/W
37.1°C/W
Transistor Count
The transistor count for the 8SLVD2104 is: 394
REVISION 1 08/03/15
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DUAL 1:4, LVDS OUTPUT FANOUT BUFFER
8SLVD2104 DATA SHEET
28-Lead VFQFN Package Outline and Package Dimensions
DUAL 1:4, LVDS OUTPUT FANOUT BUFFER
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REVISION 1 08/03/15
8SLVD2104 DATA SHEET
Ordering Information
Table 8. Ordering Information
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
8SLVD2104NBGI
SLVD2104NBGI
28 Lead VFQFN, Lead-Free
Tray
-40C to 85C
Tape & Reel
8SLVD2104NBGI8
8SLVD2104NBGI/W
SLVD2104NBGI
28 Lead VFQFN, Lead-Free
28 Lead VFQFN, Lead-Free
-40C to 85C
-40C to 85C
pin 1 orientation: EIA-481-C
Tape & Reel
SLVD2104NBGI
pin 1 orientation: EIA-481-D
Table 9. Pin 1 Orientation in Tape and Reel Packaging
Part Number Suffix
Pin 1 Orientation
Illustration
CARRIER TAPE TOPSIDE
(Round Sprocket Holes)
Correct Pin 1 ORIENTATION
8
Quadrant 1 (EIA-481-C)
USER DIRECTION OF FEED
CARRIER TAPE TOPSIDE
(Round Sprocket Holes)
Correct Pin 1 ORIENTATION
/W
Quadrant 2 (EIA-481-D)
USER DIRECTION OF FEED
REVISION 1 08/03/15
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DUAL 1:4, LVDS OUTPUT FANOUT BUFFER
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San Jose, CA 95138 USA
Sales
Tech Support
email: clocks@idt.com
1-800-345-7015 or 408-284-8200
Fax: 408-284-2775
www.IDT.com
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in
this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined
in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether
express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This
document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.
IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably
expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or
other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications, such as
those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any
circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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