8T49N1012-999NLGI8_技术文档

FemtoClock^®NG 12-Output 

8T49N1012

Datasheet

Frequency Synthesizer

General Description

Features

The 8T49N1012 has one fractional-feedback PLL that can be used

for frequency synthesis. It is equipped with two integer and eight

fractional output dividers, allowing the generation of up to ten

different output frequencies, ranging from 8kHz to 1GHz. Eight of

these frequencies are completely independent of each other and the

inputs. Two more are related frequencies. The twelve outputs may

select among LVPECL, LVDS, HSCL or LVCMOS output levels.

• <350fs RMS typical jitter (including spurs), @122.88MHz (12kHz

to 20MHz)

• Operating modes: locked to input signal and free-run

• Operates from a 10MHz to 40MHz fundamental-mode crystal

• Accepts one LVPECL, LVDS, LVHSTL, HCSL or LVCMOS input

clock

• Accepts frequencies ranging from 10MHz up to 600MHz

• Clock input monitoring

This functionality makes it ideal to be used in any frequency

synthesis application, including 1G, 10G, 40G and 100G

Synchronous Ethernet, OTN, and SONET/SDH, including ITU-T

G.709 (2009) FEC rates.

• Generates 12 LVPECL / LVDS / HSCL or 24 LVCMOS output

clocks

• Output frequencies ranging from 8kHz up to 1.0GHz (Q[8:11],

The device supports Output Enable inputs and Lock and LOS status

outputs.

The device is programmable through an I²C interface. It also

supports I²C master capability to allow the register configuration to

be read from an external EEPROM.

Differential)

• Output frequencies ranging from 8kHz to 250MHz (LVCMOS)

• Two Output Enable control inputs

• Lock and Loss-of-Signal status outputs

• Programmable output de-skew adjustments in steps as small as

16ps

Applications

• Register programmable through I²C or via external I²C EEPROM

• Bypass clock paths and Reference Output for system tests

• OTN or SONET / SDH equipment Line cards (up to OC-192, and

supporting FEC ratios)

• Power supply modes:

• Gigabit and Terabit IP switches / routers

• Wireless base station baseband

• Data communications

V_CC/ V_CCA/ V_CCO

3.3V / 3.3V / 3.3V

3.3V / 3.3V / 2.5V

3.3V / 3.3V / 1.8V (LVCMOS)

2.5V / 2.5V / 3.3V

2.5V / 2.5V / 2.5V

2.5V / 2.5V / 1.8V (LVCMOS)

• -40°C to 85°C ambient operating temperature

• Package: 72QFN, lead-free RoHs (6)

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October 28, 2016

8T49N1012 Datasheet

8T49N1012 Block Diagram

LOS

LOCK

REF_OUT

PLL_BYP

Q0

Q1

Q2

Q3

Q4

Q5

OSCI

FracN Div A

FracN Div B

FracN Div C

OSC

1

0

OSCO

Fractional

Feedback

PLL

÷1, ÷ 2,

÷ 4, x2

CLK

nCLK

FracN Div D

FracN Div E

CLK_SEL

FracN Div F

FracN Div G

Q6

Q7

Reset

Logic

nRST

OTP

FracN Div H

IntN Div I

Status Registers

Control Registers

Q8

I²C Master

Q9

SCLK

SDATA

SA1

I²C SLAVE

Q10

Q11

IntN Div J

OE[1:0]

Serial EEPROM

Figure 1. 8T49N1012 Functional Block Diagram

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October 28, 2016

8T49N1012 Datasheet

Pin Assignment for 72-pin, 10mm x 10mm VFQFN Package

72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55

1

2

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

REF_OUT

V_CCA

PLL_BYP

nc

Q0

nQ0

V_CCO0

V_CCO1

Q1

nQ1

nc

Rsvd

nc

V_CCO2

Q2

nQ2

nc

V_CCO3

Q3

3

OSCI

OSCO

LOCK

V_CCO10

Q11

nQ11

Q10

nQ10

nc

Rsvd

V_CCO8

Q9

nQ9

Q8

4

5

6

8XXXXXX

7

8

9

10

11

12

13

14

15

16

17

18

nQ8

Rsvd

nQ3

19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

Figure 2. Pinout Drawing

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October 28, 2016

8T49N1012 Datasheet

Pin Description and Pin Characteristic Tables

1

Table 1. Pin Descriptions

Number

Name

Type

Description

1

2

Output

Power

REF_OUT

V_CCA

Single-ended REF output. 1.8V LVCMOS/LVTTL interface levels.

Core analog functions supply pin.

Crystal Input. Accepts a 10MHz-40MHz reference from a clock oscillator or a

12pF fundamental mode, parallel-resonant crystal.

3

4

Input

OSCI

Crystal Output. This pin should be connected to a crystal. If an oscillator is

connected to OSCI, then this pin must be left unconnected.

OSCO

Output

5

LOCK

V_CCO10

Q11

Output

Power

Output

Unused

PLL lock indicator. LVCMOS/LVTTL interface levels.

Output supply for Q10 and Q11 output clock pairs.

6

7

Output Clock 11. Refer to the Output Drivers section for more details.

Output Clock 10. Refer to the Output Drivers section for more details.

No internal connection.

8

nQ11

Q10

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

nQ10

nc

Rsvd

Reserved

Power

Output

Reserved

Input

Reserved - leave unconnected.

Output supply for Q8 and Q9 output clock pairs.

V_CCO8

Q9

Output Clock 9. Refer to the Output Drivers section for more details.

Output Clock 8. Refer to the Output Drivers section for more details.

Reserved - leave unconnected.

nQ9

Q8

nQ8

Rsvd

SA1

Pulldown I²C lower address bit A1.

V_CCD

SCLK

SDATA

V_EE

Power

I/O

Core Digital functions supply voltage.

I²C interface bi-directional Clock.

I²C interface bi-directional Data.

Negative supply voltage.

Pullup

I/O

Power

Unused

Power

Core functions supply voltage.

No internal connection.

V_CC

nc

No internal connection.

Output supply for Q7 output clock pair.

V_CCO7

28

29

30

31

32

33

34

35

36

37

38

Output

Unused

Input

Q7

nQ7

nc

Output Clock 7. Refer to the Output Drivers section for more details.

No internal connect.

OE0

nc

Pulldown Output enable. LVCMOS/LVTTL interface levels.

No internal connection.

Unused

Output

Power

Input

Q6

Output Clock 6. Refer to the Output Drivers section for more details.

Output supply for Q6 output clock pair.

nQ6

V_CCO6

OE1

Pulldown

Output enable. LVCMOS/LVTTL interface levels.

nQ3

Output

Output Clock 3. Refer to the Output Drivers section for more details.

Q3

4

October 28, 2016

8T49N1012 Datasheet

1

Table 1. Pin Descriptions (Continued)

Number

Name

Type

Description

39

Power

Output supply for Q3 output clock pair.

No internal connection.

V_CCO3

40

41

42

43

Unused

Output

Power

nc

nQ2

Q2

Output Clock 2. Refer to the Output Drivers section for more details.

Output supply for Q2 output clock pair.

V_CCO2

nc

44

45

Unused

No internal connection.

Reserved

Pulldown Reserved - leave unconnected.

Rsvd

46

47

48

49

Unused

Output

Power

No internal connection.

nc

nQ1

Q1

Output Clock 1. Refer to the Output Drivers section for more details.

Output supply for Q1 output clock pair.

V_CCO1

50

51

52

53

Power

Output

Unused

Output supply for Q0 output clock pair.

V_CCO0

nQ0

Q0

Output Clock 0. Refer to the Output Drivers section for more details.

No internal connection.

nc

Bypass Selection. Allow PLL references to bypass PLL and appear at Q[0:3].

LVTTL / LVCMOS interface levels.

54

Input

Pulldown

PLL_BYP

55

56

57

nQ5

Q5

Output

Power

Output Clock 5. Refer to the Output Drivers section for more details.

Output supply for Q5 output clock pair.

V_CCO5

Master Reset input. LVTTL / LVCMOS interface levels.

0 = All registers and state machines are reset to their default values

1 = Device runs normally

58

Input

Pullup

nRST

59

60

61

62

63

nQ4

Q4

Output

Power

Output

Power

Output Clock 4. Refer to the Output Drivers section for more details.

Output supply for Q4 output clock pair.

V_CCO4

LOS

Loss of reference to PLL indicator. LVCMOS/LVTTL interface levels.

Core analog function supply voltage.

V_CCA

64

65

Analog

PLL External Capacitance reference.

CAP_REF

PLL External Capacitance. A 0.1µF capacitance value across CAP and

CAP_REF pins is recommended.

CAP

66

67

68

Power

Core analog function supply voltage.

V_CCA

Supply voltage for status and control signals: nRST, LOCK, LOS, PLL_BYP,

OE[1:0].

69

70

Power

Input

V_CCCS

Clock select pin:

0: CLK, nCLK

CLK_SEL

Pullup

1: XTAL (default)

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October 28, 2016

8T49N1012 Datasheet

1

Table 1. Pin Descriptions (Continued)

Number

71

Name

nCLK

CLK

Type

Description

Inverting differential clock input. Internal resistor bias to V_CC/2.

Pullup/

Pulldown

Input

72

Pulldown Non-inverting differential clock input.

Exposed pad of package. All ground pins and EPAD must be connected

before any positive supply voltage is applied.

ePAD

V_{EE_EP}

Power

NOTE 1. Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

1

Table 2. Pin Characteristics

Symbol

C_IN

Parameter

Input Capacitance²

Test Conditions

Minimum

Typical

3.5

Maximum Units

pF

k

pF

R_PULLUP

Internal Pullup Resistor

51

R_PULLDOWNInternal Pulldown Resistor

LVCMOS; Q[0:7]

51

V_CCOx= 3.465V

17

LVCMOS;

Q[8:11]

14

15

pF

LVCMOS; Q[0:7]

V_CCOx= 2.625V

LVCMOS;

Q[8:11]

V_CCOx= 2.625V

V_CCOx= 1.89V

13

Power

LVCMOS; [0:7]

15

Dissipation

Capacitance

(per output pair)

C_PD

LVCMOS;

Q[8:11]

11.5

LVDS, HSCL,

LVPECL or Hi-Z;

Q[0:7]

V_CCOx= 3.465V or 2.625V

4.5

2.5

pF

LVDS, HSCL,

LVPECL or Hi-Z;

Q[8:11]

V_CCOx= 3.465V or 2.625V

V_CCCS= 3.3V

V_CCCS= 2.5V

43

52



LOCK, LOS

Output

Impedance

R_OUT

Q[0:11],

nQ[0:11]

LVCMOS Operation Selected

22

30



REF_OUT

NOTE 1. V_CCOxdenotes: V_CCO0through V_CCO8,V_CCO10.

NOTE 2. This specification does not apply to OSCI and OSCO pins.

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October 28, 2016

8T49N1012 Datasheet

Principles of Operation

The 8T49N1012 accepts either a crystal input or a differential input

clock. It generates up to twelve output clocks ranging from 8kHz up

to 1.0GHz.

The user selects via the CLK_SEL input pin whether the crystal

(CLK_SEL = HIGH) or the CLK/nCLK (CLK_SEL = LOW) is used as

the reference frequency. The CLK_SEL input has an internal pull-up

so that if it is not connected, the crystal will be selected as the source.

The output of this selection logic may be monitored via the REF_OUT

pin.

The 8T49N1012 has one fractional-feedback PLL that tracks either a

crystal or input reference clock. From the output of the PLL a wide

range of output frequencies can be simultaneously generated.

Whichever source is selected is passed to a pre-scaler function

which can multiply that frequency by a factor of 2, pass it on directly

or divide it by 2 or by 4. For best performance, this pre-scaler should

be set to provide the highest frequency less than the 150MHz limit

the PLL can accept. This scaled reference may be monitored on the

Q[0:3] outputs by use of the PLL_BYP pin or via register control.

The device monitors the input clock and generates an alarm when an

input clock or crystal failure is detected.

The PLL provides a frequency reference that is unrelated to the input

clock or crystal frequency. The PLL frequency may be used by any of

eight fractional output dividers or two Integer output dividers to

generate up to 10 different frequencies on the twelve outputs.

Input Clock Monitor

The device supports programmable skew adjustment on the eight

fractional output dividers.

The PLL input (after pre-scaling) is monitored for Loss of Signal

(LOS). If no activity has been detected by the PLL on its input within

64 clock periods then the input is considered to have failed and the

internal Loss-of-Signal status flag is set and the LOS pin is asserted.

The device is programmable through an I²C interface and may also

autonomously read its register settings from an internal One-Time

Programmable (OTP) memory or an external serial I²C EEPROM.

Once a LOS on the selected input reference is detected, the internal

LOS alarm will be asserted and it will remain asserted until that PLL

input clock returns.

Bypass Path and Reference Output

For system test purposes, the PLL may be bypassed. When

PLL_BYP is asserted the PLL input reference will be presented on

the Q0 - Q3 outputs. Note that this frequency represents the selected

input frequency after the pre-scaler circuit.

Note that the internal LOS alarm register bit is ‘sticky’. Once asserted

it will remain asserted until a ‘1’ has been written to that register bit to

clear it. If the LOS condition is still in effect when the ‘sticky’ bit is

cleared, then it will immediately re-assert.

Additionally, the input reference clock or crystal frequency may be

enabled on the REF_OUT pin. This is the selected input frequency

before the pre-scaler circuit. Note that since REF_OUT is an

LVCMOS output, it is limited to  250MHz. If the selected input

frequency is higher than this, REF_OUT must be disabled.

The LOS pin is not ‘sticky’ and will directly reflect the current LOS

status of the selected input reference.

Loop Bandwidth & Lock Indication

The 8T49N1012 has a fixed loop bandwidth set using internal

components of approximately 200kHz.

Input Clock Selection and Pre-Scaling

The 8T49N1012 is referenced either to a fundamental mode crystal

in the range of 10MHz to 40MHz or to an input reference clock with

frequency ranging from 10MHz up to 600MHz. The reference clock

input can accept LVPECL, LVDS, LVHSTL, HCSL or LVCMOS inputs

using 1.8V, 2.5V or 3.3V logic levels. To use LVCMOS inputs, please

refer to the Application Note later in this datasheet, Wiring the

Differential Input to Accept Single-Ended Levels (page 37) for biasing

instructions.

Once the PLL has locked to the selected input reference, then the

internal LOCK status will be set.

The internal lock status will be reflected directly on the LOCK pin and

on the internal LOCK status register.

Note that the internal LOCK status register bit is ‘sticky’. Once

asserted it will remain asserted until a ‘1’ has been written to that

register bit to clear it. If the LOCK condition is still in effect when the

‘sticky’ bit is cleared, then it will immediately re-assert.

The input reference clock does not support transmission of

spread-spectrum clocking sources. Since this family is intended for

high-performance applications, it will assume input reference

sources to have stabilities of +100ppm or better.

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October 28, 2016

8T49N1012 Datasheet

Fractional Output Dividers (Div A - Div H)

Output Buffers

For the fractional output dividers, the output divide ratio is given by:

The Q0 to Q11 clock outputs are provided with register-controlled

output buffers. By selecting the output drive type in the appropriate

register, any of these outputs can support LVCMOS, LVPECL, HSCL

or LVDS logic levels.

Output Divide Ratio = (N.F)x2

N = Integer Part: 4, 5, ...(2¹⁸-1)

F = Fractional Part: [0, 1, 2, ...(2²⁸-1)]/(2²⁸

)

The operating voltage ranges of each output is determined by its

independent output power pin (V_CCO) and thus each can have

different output voltage levels. Output voltage levels of 2.5V or 3.3V

are supported for differential operation and LVCMOS operation. In

For integer operation (F = 0) of these fractional output dividers, N =

3 is also supported. The max frequency with Integer Divider mode is

667.67MHz, and with Fractional Divider mode is 400MHz.

addition, LVCMOS output operation supports 1.8V V_CCO

.

Each output may be enabled or disabled by register bits and/or

OE[1:0] pins. When disabled an output will be in a high impedance

state.

Integer Output Dividers (Div I & Div J)

Each integer output divider block consists of two divider stages in a

series to achieve the desired total output divider ratio. The first stage

divider may be set to divide by 4, 5 or 6. The second stage of the

divider may be bypassed (i.e. divide-by-1) or programmed to any

even divider ratio from 2 to 131,070. The total divide ratios, settings

and possible output frequencies are shown in Table 3.

Each output has the capability of being inverted (180 degree phase

shift).

LVCMOS Operation

When a given output is configured to provide LVCMOS levels, then

both the Q and nQ outputs will toggle at the selected output

frequency. All the previously described configuration and control

apply equally to both outputs. Frequency, skew adjustment, voltage

levels and enable / disable status apply to both the Q and nQ pins.

When configured as LVCMOS, the Q and nQ outputs can be selected

to be phase-aligned with each other or inverted relative to one

another. Phase-aligned outputs will have increased simultaneous

switching currents which can negatively affect phase noise

performance and power consumption. It is recommended that use of

this selection be kept to a minimum.

Table 3. Integer Output Divider Ratios

1st-Stage 2nd-Stage

Total

Minimum

Maximum

Divide

F_OUTMHz F_OUTMHz

4

5

6

4

5

6

4

5

6

1

2

4

750

600

500

375

300

250

187.5

150

125

1000

800

5

6

8

666.7

500

10

400

12

333.3

250

Output Enables

16

Control of output enable for all outputs may be performed either via

pin control or via register control as dictated by the OEMODE control

bit.

20

200

24

166.7

...

If OEMODE = 0, then the OE[1:0] pins will control the output buffers

as indicated in Table 4.

4

5

6

131,070

524,280

655,350

786,420

0.0057

0.0046

0.0038

0.0076

0.0061

0.0051

If OEMODE = 1, then the OUTEN register bits will control the function

of each output buffer individually.

Table 4. Output Enable Pin Functions

Output Skew Adjustment (Div A - Div H)

OE1

OE0

Description

0

1

0

1

0

1

All outputs disabled (High-Impedance)

Q[0:3] enabled; Q[4:11] disabled

Q[0:3] disabled; Q[4:11] enabled

All outputs enabled

For the fractional output dividers Div A through Div H, the user may

apply adjustments that are proportional to the period of the clock

source driving each output divider. The phase of those divider

outputs may be adjusted with a granularity of 1/16th of the VCO

period. For example a 4GHz VCO frequency gives a granularity of

16ps. Anywhere from 0 to 15 steps of skew adjustment can be added

to the output clock from each fractional output divider.

This is performed by directly writing the required offset (from the

nominal rising edge position) in units of 1/16^thof the output period

into a register. Then the PLL_SYN bit must be toggled to load the

new value. The output will then jump directly to that new offset value.

For this reason, this adjustment should be made as the output is

initially programmed or in high-impedance.

8

October 28, 2016

8T49N1012 Datasheet

Power-Saving Modes

To allow the device to consume the least power possible for a given

application, the device is divided into several power domains each

with its own independent supply pins. Some of the power domains

may be powered-down under register control. Note that if the register

control is used to disable a power domain, the associated power pin

must still have an appropriate voltage applied. Each power domain

may be powered with one of the indicated voltages regardless of

what voltage is provided to any other domain. Please refer to the

Power Calculation section near the end of this document for details

on power consumption in a specific configuration.

Table 5. Device Power Domains

Power Pin

V_CC

Supported Voltages

2.5V, 3.3V

Power-down Mode Functions in the Domain

Not Supported

OTP

V_CCD

2.5V, 3.3V

Internal Registers

V_CCA

2.5V, 3.3V

Input Clock, Crystal and input reference logic, pre-scaler, PLL

Output / Input buffers for pins: nRST, CLK_SEL, PLL_BYP, LOCK, LOS,

OE[1:0], SA1, SCLK and SDATA

V_CCCS

1.8V, 2.5V, 3.3V

Not Supported

V_CCO0

V_CCO1

V_CCO2

V_CCO3

V_CCO4

V_CCO5

V_CCO6

V_CCO7

V_CCO8

V_CCO10

1.8V¹, 2.5V, 3.3V

Supported

Div A, Q0 Output Buffer & Mux

Div B, Q1 Output Buffer & Mux

Div C, Q2 Output Buffer & Mux

Div D, Q3 Output Buffer & Mux

Div E, Q4 Output Buffer & Mux

Div F, Q5 Output Buffer & Mux

Div G, Q6 Output Buffer & Mux

Div H, Q7 Output Buffer & Mux

Div I, Q8 & Q9 Output Buffers & Muxes

Div J, Q10 & Q11 Output Buffers & Muxes

NOTE 1. Operation of 1.8V is only supported when in LVCMOS output mode.

Device Hardware Configuration

The 8T49N1012 supports an internal One-Time Programmable

(OTP) memory that can be pre-programmed at the factory with one

complete device configuration. If the device is set to read a

configuration from an external, serial EEPROM, then the values read

will overwrite the OTP-defined values.

While in the reset state (nRST input asserted or POR active), the

device will operate as follows:

• All registers will return to & be held in their default states as

indicated in the applicable register description.

• All internal state machines will be in their reset conditions.

• The serial interface will not respond to read or write cycles.

• All clock outputs will be disabled.

This configuration can be over-written using the serial interface once

device initialization is complete. Any configuration written via the

programming interface needs to be re-written after any power cycle

or reset. Please contact IDT if a specific factory-programmed

configuration is desired.

• All alarm status bits will be cleared.

Upon the latter of the internal POR circuit expiring or the nRST input

negating, the device will exit reset and begin self-configuration.

Device Start-up & Reset Behavior

The device will load an initial block of its internal registers using the

configuration stored in the internal One-Time Programmable (OTP)

memory. Once this step is complete, the 8T49N1012 will check the

register settings to see if it should load the remainder of its

configuration from an external I²C EEPROM at a defined address or

continue loading from OTP. See the section on I²C Boot Initialization

for details on how this is performed.

The 8T49N1012 has an internal power-up reset (POR) circuit and a

Master Reset input pin nRST. If either is asserted, the device will be

in the Reset State.

For highly programmable devices, it's common practice to reset the

device immediately after the initial power-on sequence. IDT

recommends connecting the nRST input pin to a programmable logic

source for optimal functionality. It is recommended that a minimum

pulse width of 10ns be used to drive the nRST input pin.

Once the full configuration has been loaded, the device will respond

to accesses on the serial port and will attempt to lock the PLL to the

selected source and begin operation. Once the PLL is locked, all the

output dividers will be synchronized and output skew adjustments

can then be applied if desired.

9

October 28, 2016

8T49N1012 Datasheet

Serial Control Port Description

2

Serial Control Port Configuration Description

I C Mode Operation

The device has a serial control port capable of responding as a slave

in an I²C compatible configuration, to allow access to any of the

internal registers for device programming or examination of internal

status. All registers are configured to have default values. See the

specifics for each register for details.

The I²C interface is designed to fully support v1.2 of the I²C

Specification for Normal and Fast mode operation. The device acts

as a slave device on the I²C bus at 100kHz or 400kHz using the

address defined in the Serial Interface Control register (0006h), as

modified by the SA1 input pin settings. The interface accepts

byte-oriented block write and block read operations. Two address

bytes specify the register address of the byte position of the first

register to write or read. Data bytes (registers) are accessed in

sequential order from the lowest to the highest byte (most significant

bit first). Read and write block transfers can be stopped after any

complete byte transfer. During a write operation, data will not be

moved into the registers until the STOP bit is received, at which point,

all data received in the block write will be written simultaneously.

The device has the additional capability of becoming a master on the

I²C bus only for the purpose of reading its initial register

configurations from a serial EEPROM on the I²C bus. Writing of the

configuration to the serial EEPROM must be performed by another

device on the same I²C bus or pre-programmed into the device prior

to assembly.

For full electrical I²C compliance, it is recommended to use external

pull-up resistors for SDATA and SCLK. The internal pull-up resistors

have a size of 51k typical.

Current Read

S

Dev Addr + R

A

Data 0

A

Data 1

A

Data n

Dev Addr + R

A

P

Sequential Read

S

Dev Addr + W

Offset Addr MSB

A

Offset Addr LSB

A

Sr

A

Data 0

A

Data 1

A

Data n

A

P

Sequential Write

S

Dev Addr + W

Data 0

Data 1

A

Data n

A

P

S = start

from master to slave

from slave to master

Sr = repeated start

A = acknowledge

A = none acknowledge

P = stop

2

Figure 3. I C Slave Read and Write Cycle Sequencing

10

October 28, 2016

8T49N1012 Datasheet

2

I C Master Mode

When operating in I²C mode, the 8T49N1012 has the capability to

become a bus master on the I²C bus for the purposes of reading its

configuration from an external I²C EEPROM. Only a block read cycle

will be supported.

• Fixed-period cycle response timer to prevent permanently hanging

the I²C bus.

• Read will abort with an alarm (BOOTFAIL) if any of the following

conditions occur: Slave NACK, Arbitration Fail, Collision during

Address Phase, CRC failure, Slave Response time-out

The 8T49N1012 will not support the following functions:

As an I²C bus master, the 8T49N1012 will support the following

functions:

• 7-bit addressing mode

• I²C General Call

• Base address register for EEPROM

• Slave clock stretching

• I²C Start Byte protocol

• Validation of the read block via CCITT-8 CRC check against value

stored in last byte (B4h) of EEPROM

• EEPROM Chaining

• Support for 100kHz and 400kHz operation with speed negotiation.

If bit d0 is set at Byte address 05h in the EEPROM, this will shift

from 100kHz operation to 400kHz operation.

• CBUS compatibility

• Responding to its own slave address when acting as a master

• Writing to external I²C devices including the external EEPROM

used for booting

• Support for 1- or 2-byte addressing mode

• Master arbitration with programmable number of retries

Sequential Read (1‐byte offset address)

S

Dev Addr + W

A

Offset Addr

A

Sr

Dev Addr + R

A

Data 0

A

Data 1

A

Data n

A

P

Sequential Read (2‐byte offset address)

S

Dev Addr + W

A

Offset Addr MSB

A

Offset Addr LSB

A

Sr

Dev Addr + R

A

Data 0

A

Data 1

A

Data n

A

P

S = start

from master to slave

from slave to master

Sr = repeated start

A = acknowledge

A = none acknowledge

P = stop

2

Figure 4. I C Master Read Cycle Sequencing

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October 28, 2016

8T49N1012 Datasheet

2

I C Boot-up Initialization Mode

If enabled (via the BOOT_EEP bit in the Startup register), once the

nRST input has been deasserted (high) and its internal power-up

reset sequence has completed, the device will contend for ownership

of the I²C bus to read its initial register settings from a memory

location on the I²C bus. The address of that memory location is kept

in non-volatile memory in the Startup register. During the boot-up

process, the device will not respond to serial control port accesses.

Once the initialization process is complete, the contents of any of the

device’s registers can be altered. It is the responsibility of the user to

make any desired adjustments in initial values directly in the serial

bus memory.

If a NACK is received to any of the read cycles performed by the

device during the initialization process, or if the CRC does not match

the one stored in address B4h of the EEPROM the process will be

aborted and any uninitialized registers will remain with their default

values. The BOOTFAIL bit (0214h) in the Global Status register will

also be set in this event.

Contents of the EEPROM should be as shown in Table 6.

Table 6. External Serial EEPROM Contents

EEPROM Offset

Contents

(Hex)

D7

D6

D5

1

D4

1

D3

1

D2

1

D1

1

D0

1

00

1

01

1

02

1

03

1

04

1

Serial EEPROM

Speed Select

0 = 100kHz

05

1

0

1

1 = 400kHz

06

07

1

0

8T49N1012 Device I²C Address [6:2]

1

0

1

0

08 - B3

B4

Desired contents of Device Registers 08h - B3

Serial EEPROM CRC

B5 - FF

Unused

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October 28, 2016

8T49N1012 Datasheet

Register Descriptions

Table 7A. Register Blocks

Register Ranges Offset (Hex)

Register Block Description

0000 - 0001

0002 - 0005

0006 - 0007

0008 - 0032

0033 - 003E

003F - 0048

0049 - 008C

008D - 008F

0090- 0091

0092 - 0099

009A - 009F

00A0- 00A2

00A3 - 01FF

0200 - 0203

0204- 0212

0213 - 0215

0216 - 03FF

Startup Control Registers

Device ID Control Registers

Serial Interface Control Registers

Reserved

PLL Divider Control Registers

Output Buffer Control Registers

Output Divider Control Registers

Output Mux Control Registers

Divider Power Control Registers

Reserved

PLL Control Registers

Buffer Power Control Registers

Reserved

Interrupt Status Registers

Reserved

Global Status Registers

Reserved

Table 7B. Startup Control Register Bit Field Locations and Descriptions

Startup Control Register Block Field Locations

Address (Hex)

0000

D7

D6

D5

D4

D3

D2

D1

D0

EEP_RTY[4:0]

Rsvd

nBOOT_OTP nBOOT_EEP

0001

EEP_A15

EEP_ADDR[6:0]

Startup Control Register Block Field Descriptions

Default Value Description

Bit Field Name

Field Type

Select number of times arbitration for the I²C bus to read the serial EEPROM will be

retried before being aborted. Note that this number does not include the original try.

EEP_RTY[4:0]

R/W

00001b

Internal One-Time Programmable (OTP) memory usage on power-up:

0 = Load power-up configuration from OTP

1 = Only load 1st eight bytes from OTP

nBOOT_OTP

nBOOT_EEP

R/W

Various¹

External EEPROM usage on power-up:

0 = Load power-up configuration from external serial EEPROM (overwrites OTP

values)

Various¹

1 = Don’t use external EEPROM

EEP_A15

EEP_ADDR[6:0]

Rsvd

R/W

Various¹

-

Serial EEPROM supports 15-bit addressing mode (multiple pages).

I²C base address for serial EEPROM.

Reserved. Always write 0 to this bit location. Read values are not defined.

NOTE 1. These values are specific to the device configuration and can be customized when ordering. Refer to the FemtoClock NG Uni-

versal Frequency Translator Ordering Product Information guide or custom datasheet addendum for more details.

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October 28, 2016

8T49N1012 Datasheet

Table 7C. Device ID Control Register Bit Field Locations and Descriptions

Device ID Register Control Block Field Locations

Address (Hex)

0002

D7

D6

D5

D4

D3

D2

D1

D0

REV_ID[3:0]

DEV_ID[15:12]

0003

DEV_ID[11:4]

0004

DEV_ID[3:0]

DASH_CODE[10:7]

0005

DASH_CODE[6:0]

1

Device ID Control Register Block Field Descriptions

Default Value Description

Bit Field Name

REV_ID[3:0]

Field Type

R/W

0000b

060Eh

Device revision.

Device ID code.

Device Dash Code.

DEV_ID[15:0]

R/W

Decimal value assigned by IDT to identify the configuration loaded at the factory.

May be over-written by users at any time. Refer to FemtoClock NG Universal

Frequency Translator Ordering Product Information to identify major configuration

parameters associated with this Dash Code value.

DASH_CODE

[10:0]

R/W

Various¹

NOTE 1:These values are specific to the device configuration and can be customized when ordering. Refer to the FemtoClock NG Uni-

versal Frequency Translator Ordering Product Information guide or custom datasheet addendum for more details.

Table 7D. Serial Interface Control Register Bit Field Locations and Descriptions

Serial Interface Control Block Field Locations

Address

(Hex)

0006

0007

D7

D6

D5

D4

DEVADD[6:2]

Rsvd

D3

D2

D1

D0

Rsvd

1

Rsvd

DEVADD[1]

Serial Interface Control Register Block Field Descriptions

Default Value Description

Bit Field Name

Field Type

DEVDD[6:2]

R/W

Various¹

Configurable portion of I²C Base Address (bits 6:2) for this device.

I²C Base Address bit 1. This address bit reflects the status of the SA1 external input

pin. See Pin Description and Pin Characteristic Tables (page 4).

DEVADD[1]

R/O

0b

Rsvd

R/O

R/W

0b

-

Reserved.

Reserved. Always write 0 to this bit location. Read values are not defined.

NOTE 1. These values are specific to the device configuration and can be customized when ordering. Generic dash codes -900 through

-903, -998 and -999 are available and programmed with the default I²C address of 1111100b.Please refer to the FemtoClock NG

Universal Frequency Translator Ordering Product Information guide or custom datasheet addendum for more details.

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October 28, 2016

8T49N1012 Datasheet

Table 7E. PLL Divider Control Register Bit Field Locations and Descriptions

PLL Divider Control Register Block Field Locations

Address (Hex)

0033

D7

D6

D5

D4

D3

D2

D1

D0

Rsvd

DSM_INT[8]

0034

DSM_INT[7:0]

DSMFRAC[23:16]

DSMFRAC[15:8]

DSMFRAC[7:0]

Rsvd

0035

0036

0037

0038

0039

01h

003A

Rsvd

003B

Rsvd

003C

003D

003E

DSM_ORD[1:0]

DCXOGAIN[1:0]

Rsvd

DITHGAIN[2:0]

Rsvd

PLL Divider Control Register Block Field Descriptions

Default Value Description

Bit Field Name

Field Type

DSM_INT[8:0]

R/W

02Dh

Integer portion of the Delta-Sigma Modulator value.

Fractional portion of Delta-Sigma Modulator value. Divide this number by 2²⁴to

determine the actual fraction.

DSMFRAC[23:0]

DSM_ORD[1:0]

R/W

000000h

Delta-Sigma Modulator Order for PLL:

00 = Delta-Sigma Modulator disabled

01 = 1st order modulation

10 = 2nd order modulation

11 = 3rd order modulation

11b

01b

Multiplier applied to instantaneous frequency error before it is applied to the Digitally

Controlled Oscillator:

00 = 0.5

DCXOGAIN[1:0]

R/W

01 = 1

10 = 2

11 = 4

Dither Gain setting for Digitally Controlled Oscillator:

000 = No dither

001 = Least Significant Bit (LSB) only

010 = 2 LSBs

DITHGAIN[2:0]

R/W

000b

011 = 4 LSBs

100 = 8 LSBs

101 = 16 LSBs

110 = 32 LSBs

111 = 64 LSBs

Rsvd

-

Reserved. Always write 0 to this bit location. Read values are not defined.

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8T49N1012 Datasheet

Table 7F. Output Buffer Control Register Bit Field Locations and Descriptions

Output Buffer Control Register Block Field Locations

Address (Hex)

003F

D7

D6

D5

D4

D3

D2

D1

OUTEN[11:8]

D0

Rsvd

OEMODE

0040

OUTEN[7:0]

0041

Rsvd

POL_Q[11:8]

0042

POL_Q[7:0]

SE_MODE11

0043

OUTMODE11[2:0]

OUTMODE9[2:0]

OUTMODE7[2:0]

OUTMODE5[2:0]

OUTMODE3[2:0]

OUTMODE1[2:0]

OUTMODE10[2:0]

OUTMODE8[2:0]

OUTMODE6[2:0]

OUTMODE4[2:0]

OUTMODE2[2:0]

OUTMODE0[2:0]

SE_MODE10

SE_MODE8

SE_MODE6

SE_MODE4

SE_MODE2

SE_MODE0

0044

SE_MODE9

SE_MODE7

SE_MODE5

SE_MODE3

SE_MODE1

0045

0046

0047

0048

Output Buffer Control Register Block Field Descriptions

Default Value Description

Bit Field Name

Field Type

Register or OE[1:0] pins to control Output Enable operation:

OEMODE

R/W

0b

fffh

0 = OE[1:0] pins will control enabling of the output buffers as shown in Table 4

1 = OE[1:0] pins are disabled and Output Enables are controlled by internal registers

Output Enable control for Clock Outputs Q[0:11], nQ[0:11]:

0 = Qn is in a high-impedance state

1 = Qn is enabled as indicated in appropriate OUTMODEn[2:0] register field

OUTEN[11:0]

POL_Q[11:0]

R/W

Polarity of Clock Outputs Q[0:11], nQ[0:11]:

0 = Normal polarity

000h

1 = Inverted polarity

Output Driver Mode of Operation for Clock Output Pair Qm, nQm:

000 = High-impedance

001 = LVPECL

010 = LVDS

011 = LVCMOS

100 = HCSL

101 - 111 = reserved

OUTMODEm

[2:0]

R/W

001b

0b

Behavior of Output Pair Qm, nQm when LVCMOS operation is selected

(Must be 0 if LVDS, HCSL or LVPECL output style is selected):

0 = Qm and nQm are both the same frequency but inverted in phase

1 = Qm and nQm are both the same frequency and phase

SE_MODEm

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8T49N1012 Datasheet

Table 7G. Output Divider Control Register Bit Field Locations and Descriptions

Output Divider Control Register Block Field Locations

Address (Hex)

0049

004A

004B

004C

004D

004E

004F

0050

0051

0052

0053

0054

0055

0056

0057

0058

0059

005A

005B

005C

005D

005E

005F

0060

0061

0062

0063

0064

0065

0066

0067

0068

0069

006A

006B

006C

006D

006E

006F

0070

0071

D7

D6

D5

D4

D3

D2

D1

N_DIVA[17]

D0

Rsvd

N_DIVA[16]

N_DIVA[15:8]

N_DIVA[7:0]

N_DIVB[17] N_DIVB[16]

N_DIVC[17] N_DIVC[16]

N_DIVD[17] N_DIVD[16]

N_DIVE[17] N_DIVE[16]

N_DIVB[15:8]

N_DIVB[7:0]

N_DIVC[15:8]

N_DIVC[7:0]

N_DIVD[15:8]

N_DIVD[7:0]

N_DIVE[15:8]

N_DIVE[7:0]

N_DIVF[17]

N_DIVF[16]

N_DIVF[15:8]

N_DIVF[7:0]

N_DIVG[17] N_DIVG[16]

N_DIVH[17] N_DIVH[16]

N1_DIVI[1:0]

N_DIVG[15:8]

N_DIVG[7:0]

N_DIVH[15:8]

N_DIVH[7:0]

N2_DIVI[15:8]

N2_DIVI[7:0]

N1_DIVJ[1:0]

N2_DIVJ[15:8]

N2_DIVJ[7:0]

Rsvd

F_DIVA[27:24]

F_DIVA[23:16]

F_DIVA[15:8]

F_DIVA[7:0]

F_DIVB[27:24]

F_DIVC[27:24]

F_DIVB[23:16]

F_DIVB[15:8]

F_DIVB[7:0]

F_DIVC[23:16]

F_DIVC[15:8]

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October 28, 2016

8T49N1012 Datasheet

Output Divider Control Register Block Field Locations

D6 D5 D4 D3

F_DIVC[7:0]

Address (Hex)

0072

0073

0074

0075

0076

0077

0078

0079

007A

007B

007C

007D

007E

007F

0080

0081

0082

0083

0084

0085

0086

0087

0088

0089

008A

008B

008C

D7

D2

D1

D0

Rsvd

F_DIVD[27:24]

F_DIVD[23:16]

F_DIVD[15:8]

F_DIVD[7:0]

F_DIVE[27:24]

F_DIVF[27:24]

F_DIVG[27:24]

F_DIVH[27:24]

F_DIVE[23:16]

F_DIVE[15:8]

F_DIVE[7:0]

F_DIVF[23:16]

F_DIVF[15:8]

F_DIVF[7:0]

F_DIVG[23:16]

F_DIVG[15:8]

F_DIVG[7:0]

F_DIVH[23:16]

F_DIVH[15:8]

F_DIVH[7:0]

FINE_C[3:0]

FINE_D[3:0]

FINE_G[3:0]

FINE_H[3:0]

FINE_A[3:0]

FINE_B[3:0]

FINE_E[3:0]

FINE_F[3:0]

Rsvd

Output Divider Control Register Block Field Descriptions

Bit Field Name Field Type Default Value Description

1st Stage Output Divider Ratio for Integer Output Dividers I and J:

00 = /5

N1_DIVm[1:0]

R/W

10b

01 = /6

10 = /4

11 = Output Qm, nQm not switching

2nd Stage Output Divider Ratio for Integer Output Dividers I and J:

Actual divider ratio is 2x the value written here.

A value of 0 in this register will bypass the second stage of the divider.

N2_DIVm[15:0]

N_DIVm[17:0]

R/W

0002h

Integer Portion of Output Divider Ratio for Fractional Output Dividers A - H:

Values of 0, 1 or 2 cannot be written to this register. Actual integer portion is 2x the

value written here.

00008h

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October 28, 2016

8T49N1012 Datasheet

Output Divider Control Register Block Field Descriptions

Bit Field Name Field Type Default Value Description

Fractional Portion of Output Divider Ratio for Fractional Output Dividers A - H:

Actual fractional portion is 2x the value written here.

Fraction = (F_DIVm * 2) * 2^-28

F_DIVm[27:0]

R/W

0000000h

Number of 1/16ths of the VCO clock period to add to the phase of a Fractional Output

Divider A-H. The PLL_SYN bit must be toggled to make this value take effect.

FINE_m[3:0]

Rsvd

R/W

0100b

-

Reserved. Always write 0 to this bit location. Read values are not defined.

Table 7H. Output Mux Control Register Bit Field Locations and Descriptions

Output Mux Control Register Block Field Locations

Address (Hex)

008D

D7

D6

D5

D4

D3

D2

D1

D0

Rsvd

PLL_SYN

MUX_8_9

Rsvd

008E

Rsvd

MUX_10_11

MUX_1

008F

MUX_7

MUX_6

MUX_5

MUX_4

MUX_3

MUX_2

Output Mux Control Register Block Field Descriptions

Default Value Description

Bit Field Name

Field Type

Output Synchronization Control.

Setting this bit from 01 will cause the output divider(s) to be held in reset.

Setting this bit from 10 will release all the output divider(s) to run from the same

point in time with the output skew adjustment reset to 0.

PLL_SYN

R/W

0b

Output Divider selection for Output Q10, nQ10 and Q11, nQ11:

0 = Output of Integer Divider J is used

1 = Output of Integer Divider I is used

MUX_10_11

MUX_8_9

MUX_7

R/W

0b

Output Divider selection for Output Q8, nQ8 and Q9, nQ9:

0 = Output of Integer Divider I is used

1 = Output of Integer Divider J is used

Output Divider selection for Output Q7, nQ7:

0 = Output of Fractional Divider H is used

1 = Output of Fractional Divider G is used

Output Divider selection for Output Q6, nQ6:

0 = Output of Fractional Divider G is used

1 = Output of Fractional Divider H is used

MUX_6

Output Divider selection for Output Q5, nQ5:

0 = Output of Fractional Divider F is used

1 = Output of Fractional Divider E is used

MUX_5

Output Divider selection for Output Q4, nQ4:

0 = Output of Fractional Divider E is used

1 = Output of Fractional Divider F is used

MUX_4

Output Divider selection for Output Q3, nQ3:

0 = Output of Fractional Divider D is used

1 = Output of Fractional Divider A is used

MUX_3

Output Divider selection for Output Q2, nQ2:

0 = Output of Fractional Divider C is used

1 = Output of Fractional Divider A is used

MUX_2

Output Divider selection for Output Q1, nQ1:

0 = Output of Fractional Divider B is used

1 = Output of Fractional Divider A is used

MUX_1

Rsvd

R/W

0b

-

Reserved. Always write 0 to this bit location. Read values are not defined.

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October 28, 2016

8T49N1012 Datasheet

Table 7I. Divider Power Control Register Bit Field Locations and Descriptions

Divider Power Control Register Block Field Locations

Address (Hex)

0090

D7

D6

D5

D4

D3

D2

D1

D0

Rsvd

PWR_DIVJ

PWR_DIVB

PWR_DIVI

PWR_DIVA

0091

PWR_DIVH PWR_DIVG PWR_DIVF PWR_DIVE PWR_DIVD PWR_DIVC

Divider Power Control Register Block Field Descriptions

Bit Field Name

PWR_DIVm

Rsvd

Field Type

R/W

Default Value Description

Power-Down Control for Output Divider m:

0b

0 = Output Divider m operating normally

1 = Output Divider m powered-down

R/W

-

Reserved. Always write 0 to this bit location. Read values are not defined.

20

October 28, 2016

8T49N1012 Datasheet

Table 7J. PLL Control Register Bit Field Locations and Descriptions

Please contact IDT through one of the methods listed on the last page of this datasheet for details on how to set these fields for a particular

user configuration.

PLL Control Register Block Field Locations

Address (Hex)

009A

D7

D6

D5

D4

D3

D2

D1

D0

CPSET[2:0]

RS[1:0]

CP[1:0]

WPOST

DBITM

009B

Rsvd

DLCNT

009C

VCOMAN

DBIT1[4:0]

DBIT2[4:0]

REF_OE

009D

Rsvd

009E

PLL_BYP

Rsvd

P_MODE[1:0]

009F

Rsvd

PLL Control Register Block Field Descriptions

Default Value Description

Charge Pump Current Setting for PLL:

Bit Field Name

Field Type

000 = 110µA

001 = 220µA

010 = 330µA

011 = 440µA

100 = 550µA

101 = 660µA

110 = 770µA

111 = 880µA

CPSET[2:0]

R/W

100b

Internal Loop Filter Series Resistor Setting for PLL:

00 = 330

01 = 640

10 = 1.2k

11 = 1.79k

RS[1:0]

CP[1:0]

R/W

01b

Internal Loop Filter Parallel Capacitor Setting for PLL:

00 = 40pF

01 = 80pF

10 = 140pF

11 = 200pF

Internal Loop Filter 2nd Pole Setting for PLL:

0 = Rpost = 497, Cpost = 40pF

1 = Rpost = 1.58k, Cpost = 40pF

WPOST

DLCNT

R/W

1b

Digital Lock Count Setting for PLL. Set to 0 if external capacitor (CAP) for PLL is

>95nF, otherwise set to 1:

0 = 1 ppm accuracy

1 = 16 ppm accuracy

Digital Lock Manual Override Setting for PLL:

0 = Automatic Mode

1 = Manual Mode

DBITM

R/W

0b

1b

Manual Lock Mode VCO Selection Setting for PLL:

0 = VCO2

1 = VCO1

VCOMAN

DBIT1[4:0]

DBIT2[4:0]

R/W

01011b

00000b

Manual Mode Digital Lock Control Setting for VCO1 in PLL.

Manual Mode Digital Lock Control Setting for VCO2 in PLL.

PLL Bypass mode (same function as PLL_BYP pin):

0 = Q[0:3]outputs operate normally

PLL_BYP

R/W

0b

1 = Q[0:3] outputs driven by PLL input reference clock

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October 28, 2016

8T49N1012 Datasheet

PLL Control Register Block Field Descriptions

Default Value Description

Bit Field Name

Field Type

Enable Reference Output pin:

0 = REF_OUT pin is high-impedance

REF_OE

R/W

0b

1 = REF_OUT pin is driven from the input reference mux with either the direct

crystal frequency or the direct CLK input reference frequency (as controlled by the

CLK_SEL pin)

Pre-Scaler Mode Selection:

00 = Selected reference input is driven directly to the PLL (divide-by-1)

01 = Selected reference input is divided-by-2 before being driven to the PLL

10 = Selected reference input is divided-by-4 before being driven to the PLL

11 = Selected reference input is multiplied-by-2 before being driven to the PLL

P_MODE[1:0]

Rsvd

R/W

11b

-

Reserved. Always write 0 to this bit location. Read values are not defined.

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October 28, 2016

Table 7K. Buffer Power Control Register Bit Field Locations and Descriptions

The power controls below will disable specific logic blocks by turning-off the regulators associated with those logic blocks. The associated

power supply pin must remain powered, but minimal current will be drawn. The user must ensure that appropriate control bits are set elsewhere

to ensure the powered-down functions are not selected to drive other, still enabled, output paths.

Buffer Power Control Register Block Field Locations

Address

(Hex)

00A0

00A1

00A2

D7

PATHH_OFF PATHG_OFF PATHF_OFF PATHE_OFF PATHD_OFF

Rsvd REF_OFF Rsvd

D6

D5

D4

D3

D2

PATHC_OFF PATHB_OFF PATHA_OFF

PATHJ_OFF PATHI_OFF

DSM_OFF Rsvd

D1

D0

Rsvd

Buffer Power Control Register Block Field Descriptions

Bit Field Name Field Type Default Value Description

Power Control for Div H, Q7, nQ7 output buffer and associated output mux (Associated

supply pin: V_CCO7):

0 = Regulator enabled & logic operates normally

1 = Regulator disabled and logic powered down

PATHH_OFF

PATHG_OFF

PATHF_OFF

PATHE_OFF

PATHD_OFF

PATHC_OFF

PATHB_OFF

PATHA_OFF

PATHI_OFF

PATHJ_OFF

R/W

0b

Power Control for Div G, Q6, nQ6 output buffer and associated output mux (Associated

supply pin: V_CCO6):

0 = Regulator enabled & logic operates normally

1 = Regulator disabled and logic powered down

Power Control for Div F, Q5, nQ5 output buffer and associated output mux (Associated

supply pin: V_CCO5):

0 = Regulator enabled & logic operates normally

1 = Regulator disabled and logic powered down

Power Control for Div E, Q4, nQ4 output buffer and associated output mux (Associated

supply pin: V_CCO4):

0 = Regulator enabled & logic operates normally

1 = Regulator disabled and logic powered down

Power Control for Div D, Q3, nQ3 output buffer and associated output mux (Associated

supply pin: V_CCO3):

0 = Regulator enabled & logic operates normally

1 = Regulator disabled and logic powered down

Power Control for Div C, Q2, nQ2 output buffer and associated output mux (Associated

supply pin: V_CCO2):

0 = Regulator enabled & logic operates normally

1 = Regulator disabled and logic powered down

Power Control for Div B, Q1, nQ1 output buffer and associated output mux (Associated

supply pin: V_CCO1):

0 = Regulator enabled & logic operates normally

1 = Regulator disabled and logic powered down

Power Control for Div A, Q0, nQ0 output buffer and associated output mux (Associated

supply pin: V_CCO0):

0 = Regulator enabled & logic operates normally

1 = Regulator disabled and logic powered down

Power Control for Div I, Q8, nQ8 output buffer, Q9, nQ9 output buffer and associated output

mux (Associated supply pin: V_CCO8):

0 = Regulator enabled & logic operates normally

1 = Regulator disabled and logic powered down

Power Control for Div J, Q10, nQ10 output buffer, Q11, nQ11 output buffer and associated

output mux (Associated supply pin: V_CCO10):

0 = Regulator enabled & logic operates normally

1 = Regulator disabled and logic powered down

8T49N1012 Datasheet

Buffer Power Control Register Block Field Descriptions

Bit Field Name Field Type Default Value Description

Power Control for REF_OUT output buffer (Associated supply pin: V_CCCS):

0 = Regulator enabled & logic operates normally

REF_OFF

R/W

0b

1 = Regulator disabled and logic powered down

Power Control for PLL Fractional Feedback Divider (Associated supply pin: V_CCD):

0 = Feedback Divider in Fractional Mode

1 = Feedback Divider in Integer Mode; some power savings will be realized

DSM_OFF

Rsvd

R/W

0b

-

Reserved. Always write 0 to this bit location. Read values are not defined.

Table 7L. Interrupt Status Register Bit Field Locations and Descriptions

This register contains’ sticky’ bits for tracking the status of the various alarms. Whenever an alarm occurs, the appropriate Interrupt Status bit

will be set. The Interrupt Status bit will remain asserted even after the original alarm goes away. The Interrupt Status bits remain asserted until

explicitly cleared by a write of a ‘1’ to the bit over the serial port. This type of functionality is referred to as Read / Write-1-to-Clear (R/W1C).

Note that the alarm pin is not ‘sticky’ but reflects the real-time status of the appropriate alarm.

Interrupt Status Register Block Field Locations

Address (Hex)

0200

D7

D6

D5

D4

D3

D2

D1

D0

Rsvd

0201

Rsvd

LOL_INT

LOS_INT

Rsvd

0202

Rsvd

0203

Rsvd

Interrupt Status Register Block Field Descriptions

Default Value Description

Interrupt Status Bit for Loss-of-Lock on PLL:

Bit Field Name

Field Type

0 = No Loss-of-Lock alarm flag on PLL has occurred since the last time this register

bit was cleared.

LOL_INT

R/W1C

0b

1 = At least one Loss-of-Lock alarm flag on PLL has occurred since the last time this

register bit was cleared.

Interrupt Status Bit for PLL Input Reference Clock:

0 = No Loss-of Signal (LOS) alarm has occurred since the last time this register bit

LOS_INT

Rsvd

R/W1C

R/W

0b

-

was cleared.

1 = At least one LOS alarm flag has occurred since the last time this register bit was

cleared.

Reserved. Always write 0 to this bit location. Read values are not defined.

24

October 28, 2016

8T49N1012 Datasheet

Table 7M. Global Status Register Bit Field Locations and Descriptions

Global Status Register Block Field Locations

Address (Hex)

0213

D7

D6

D5

D4

D3

D2

D1

D0

Rsvd

0214

Rsvd

BOOTFAIL

EEPDONE

0215

Rsvd

nEEP_CRC

Global Interrupt Status Register Block Field Descriptions

Field Type Default Value Description

Bit Field Name

BOOTFAIL

R/O

-

Reading of Serial EEPROM failed. Once set this bit is only cleared by reset.

EEPROM CRC Error (Active Low):

0 = EEPROM was detected and read, but CRC check failed - please reset the device

via the nRST pin to retry (serial port is locked)

1 = No EEPROM CRC Error

nEEP_CRC

R/O

-

EEPDONE

Rsvd

R/O

R/W

-

Serial EEPROM Read cycle has completed. Once set this bit is only cleared by reset.

Reserved. Always write 0 to this bit location. Read values are not defined.

25

October 28, 2016

8T49N1012 Datasheet

Absolute Maximum Ratings

NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress

specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the DC Characteristics or

AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.

Item

Rating

Supply Voltage, V_CCX

3.63V

Inputs, V_I

OSCI

Other Input

0V to 2V

-0.5V to V_CCX+ 0.5V

Outputs, V_O(Q[0:11], nQ[0:11])

Outputs, V_O(LOS, LOCK, REF_OUT)

Outputs, V_O(SCLK, SDATA)

-0.5V to V_CCOx+ 0.5V

-0.5V to V_CCCS+ 0.5V

-0.5V to V_CCD+ 0.5V

Outputs, I_O(Q[0:11], nQ[0:11])

Continuous Current

Surge Current



40mA

65mA

Outputs, I_O(REF_OUT, LOS, LOCK, SDATA, SCLK)

Continuous Current

Surge Current



8mA

13mA

Junction Temperature, T_J

Storage Temperature, T_STG

125C

-65C to 150C

NOTE: V_CCXdenotes: V_CCD,V_CC,V_CCCS.

NOTE: V_CCOxdenotes: V_CCO0through V_CCO8and V_CCO10.

Supply Voltage Characteristics

1

Table 8A. Power Supply Characteristics, V

= 3.3V ±5%, V = 0V, T = -40°C to 85°C

EE A

CCX

Symbol Parameter

Test Conditions

Minimum

3.135

Typical

3.3

Maximum

3.465

Units

1

V_CCX

V_CCA

Core Supply Voltage

V

Analog Supply Voltage

3.135

3.3

3.465

2

Core Supply Current

18

28

mA

I_CCX

I_CCA

Analog Supply Current

All Functions Enabled³

140

170

NOTE 1. V_CCXdenotes: V_CCD,V_CC,V_CCCS.

NOTE 2. I_CCXdenotes the sum of: I_{CCD, CC, CCCS.}

NOTE 3. REF_OUT is disabled to high-impedance.

I

1

Table 8B. Power Supply Characteristics, V

= 2.5V ±5%, V = 0V, T = -40°C to 85°C

EE A

CCX

Symbol Parameter

Test Conditions

Minimum

2.375

Typical

2.5

Maximum

2.625

Units

1

V_CCX

V_CCA

Core Supply Voltage

V

Analog Supply Voltage

2.375

2.5

2.625

2

Core Supply Current

17

26

mA

I_CCX

I_CCA

Analog Supply Current

All Functions Enabled³

137

160

NOTE 1. V_CCXdenotes: V_CCD,V_CC,V_CCCS.

NOTE 2. I_CCXdenotes the sum of: I_{CCD, CC, CCCS.}

I

NOTE 3. REF_OUT is disabled to high-impedance.

26

October 28, 2016

8T49N1012 Datasheet

1, 2

Table 8C. Maximum Output Supply Current, V = 0V, T = -40°C to 85°C

EE

A

V_CCOx= 1.8V

3

V_CCOx³= 3.3V ±5%

V_CCOx= 2.5V ±5%

±5%

Test

Conditions

LVPEC LVDS

L

HCSL LVCMO LVPEC LVDS

HCSL LVCMO

S

LVCMOS

Units

Symbol

Parameter

S

L

Q0, nQ0 Output

Supply Current

Outputs

Unloaded

I_CCO0

71

81

71

72

58

66

58

56

48

mA

Q1, nQ1 Output

Supply Current

Outputs

Unloaded

I_CCO1

I_CCO2

I_CCO3

I_CCO4

I_CCO5

I_CCO6

I_CCO7

72

58

Q2, nQ2 Output

Supply Current

Outputs

Unloaded

Q3, nQ3 Output

Supply Current

Outputs

Unloaded

Q4, nQ4 Output

Supply Current

Outputs

Unloaded

Q5, nQ5 Output

Supply Current

Outputs

Unloaded

Q6, nQ6 Output

Supply Current

Outputs

Unloaded

Q7, nQ7 Output

Supply Current

Outputs

Unloaded

Q[8:9], nQ[8:9]

Outputs

Supply Current

Outputs

Unloaded

4

I_CCO8

67

86

67

72

50

66

50

53

42

mA

Q[10:11],nQ[10:11]

Outputs 

Supply Current

Outputs

Unloaded

4

I_CCO10

NOTE 1. Internal dynamic switching current at maximum f_OUTis included.

NOTE 2. Currents per I_CCO.

NOTE 3. V_CCOxdenotes: V_CCO0through V_CCO8and V_CCO10.

NOTE 4. Supply current specifications refer to two output pairs (Q[8:9] or Q[10:11]) being driven by one divider (Divider I or J).

27

October 28, 2016

8T49N1012 Datasheet

DC Electrical Characteristics

Table 9A. LVCMOS/LVTTL Control/Status Signals DC Characteristics, V = 0V, T = -40°C to 85°C

EE

A

Symbol Parameter

Test Conditions

Minimum

2

Typical

Maximum Units

V_CCCS= 3.3V

V_CCX+0.3

0.8

V

V_IH

Input High Voltage

V_CCCS= 2.5V

1.7

V_CCCS= 1.8V

V_CCCS= 3.3V

1.2

-0.3

V_IL

Input Low Voltage

V_CCCS= 2.5V

0.7

V_CCCS= 1.8V

0.3

PLL_BYP,

SA1, OE1, OE0

V_CCCS= V_IN= 3.465V or 2.625V or 1.9V

_CCCS= V_IN= 3.465V or 2.625V or 1.9V

150

5

μA

V

Input

High

Current

I_IH

nRST, SDATA,

CLK_SEL, SCLK

V

PLL_BYP,

SA1, OE1, OE0

V_CCCS= 3.465V or 2.625V or 1.9V, V_IN= 0V

V_CCCS= 3.3V ±5%, I_OH= -2mA

-5

Input

Low

Current

I_IL

nRST, SDATA,

CLK_SEL, SCLK

-150

2.6

LOS, LOCK,

SDATA,¹SCLK

Output

High

V_OH

LOS, LOCK,

V_CCCS= 2.5V ±5%, I_OH= -2mA

1.8

V

Voltage SDATA,¹SCLK

REF_OUT²

I

_OH= -2mA

1.45

LOS, LOCK,

Output

Low

Voltage

V_CCCS= 3.3V ±5% or 2.5V ±5%, I_OL= 2mA

0.4

SDATA¹, SCLK

V_OL

REF_OUT²

I_OL= 2mA

0.45

NOTE 1. Use of external pull-up resistor is recommended.

NOTE 2. REF_OUT is internally regulated 1.8V output.

Table 9B. Differential Input DC Characteristics, V

Symbol Parameter

= 3.3V ±5% or 2.5V ±5%, V = 0V, T = -40°C to 85°C

CCA

EE

A

Test Conditions

Minimum

Typical

Maximum

Units

μA

V

I_IH

Input High Current

CLK

nCLK

V_CCA= V_IN= 3.465V or 2.625V

V_CCA= 3.465V or 2.625V, V_IN= 0V

150

-5

I_IL

Input Low Current

-150

0.15

V_EE

V_PP

Peak-to-Peak Voltage¹

1.3

V_CMR

Common Mode Input Voltage^{1, 2}

V_CCA– 1.2

V

NOTE 1. V_ILshould not be less than -0.3V. V_IHshould not be higher than V_CCA.

NOTE 2. Common mode voltage is defined as the cross-point.

28

October 28, 2016

8T49N1012 Datasheet

1

Table 9C. LVPECL DC Characteristics, V

= 3.3V ±5% or 2.5V ±5%, V = 0V, T = -40°C to 85°C

CCOx

EE

A

V_CCOx¹= 3.3V±5%

V_CCOx¹= 2.5V±5%

Symbol Parameter

Test Conditions

Minimum

Typical Maximum

Minimum

Typical

Maximum Units

Output 

V_OH

V_CCOx- 1.3

V_CCOx- 0.8 V_CCOx- 1.4

V_CCOx- 1.75 V_CCOx- 1.95

V_CCOx- 0.9

V

High Voltage²

Output 

V_OL

V_CCOx- 1.95

V_CCOx- 1.75

Low Voltage²

NOTE 1. V_CCOxdenotes: V_CCO0through V_CCO8,V_CCO10.

NOTE 2. Outputs terminated with 50 to V_CCOx– 2V.

1

2

Table 9D. LVDS DC Characteristics,

V

=

3.3V ±5% or 2.5V ±5%,

Test Conditions

V

= 3.3V ±5% or 2.5V ±5%,

V

= 0V, 

EE

CCX

CCOx

3

T = -40°C to 85°C

A

Symbol

V_OD

Parameter

Minimum

Typical

Maximum

454

Units

mV

V

Differential Output Voltage

V_ODMagnitude Change

Offset Voltage

195

V_OD

V_OS

50

1.1

1.375

50

V_OS

V_OSMagnitude Change

mV

NOTE 1. V_CCXdenotes: V_CCD,V_CC,V_CCCS.

NOTE 2. V_CCOxdenotes: V_CCO0through V_CCO8,V_CCO10.

NOTE 3. Terminated 100 across Qx and nQx.

1

2

Table 9E. LVCMOS Clock Output DC Characteristics, V

= 3.3V ±5% or 2.5V ±5%, V = 0V, T = -40°C to 85°C

EE A

CCX

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

Output 

High Voltage

V_OH

Qx, nQx

V_CCOx= 3.3V±5%, I_OH= -8mA

2.6

V

Output 

Low Voltage

V_OL

V_OH

V_OL

V_OH

V_OL

V_CCOx= 3.3V±5%, I_OL= 8mA

0.4

V

Output 

High Voltage

V_CCOx= 2.5V±5%, I_OH= -8mA

1.8

Output 

Low Voltage

V_CCOx= 2.5V±5%, I_OL= 8mA

V_CCOx= 1.8V±5%, I_OH= -2mA

V_CCOx= 1.8V±5%, I_OL= 2mA

0.4

Output 

High Voltage

V_CCOx– 0.45

Output 

Low Voltage

0.45

NOTE 1. V_CCXdenotes: V_CCD,V_CC,V_CCCS.

NOTE 2. V_CCOxdenotes: V_CCO0through V_CCO8,V_CCO10.

29

October 28, 2016

8T49N1012 Datasheet

Table 10. Input Frequency Characteristics, V

Symbol Parameter

= 3.3V±5% or 2.5V±5%, T_A= -40°C to 85°C

CCX

Test Conditions

Minimum

Typical

Maximum

Units

Using a crystal (See Table 11,

Crystal Characteristics)

10

40

MHz

Overdriving Crystal Input, Doubler

Logic Enabled²

OSCI, OSCO

10

62.5

MHz

f_IN

Input Frequency¹

Overdriving Crystal Input, Doubler

Logic Disabled²

10

125

600

400

MHz

kHz

CLK, nCLK

Serial Port Clock

SCLK (slave mode)

f_SCLK

I²C Operation

100

NOTE 1. For the input reference frequency, the divider values must be set for the VCO to operate within its supported range.

NOTE 2. For optimal noise performance, the use of a quartz crystal is recommended. Refer to Overdriving the XTAL Interface in the Applica-

tions Information section.

Table 11. Crystal Characteristics

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

Mode of Oscillation

Frequency

Fundamental

10

40

MHz



Equivalent Series Resistance (ESR)

Load Capacitance (C_L)

Frequency Stability (total)

15

12

pF

-100

100

ppm

30

October 28, 2016

8T49N1012 Datasheet

AC Electrical Characteristics

1

2

Table 12A. AC Characteristics, V

= 3.3V ±5% or 2.5V ±5%, V

= 3.3V ±5%, 2.5V ±5% or 1.8V ±5% (1.8V only

CCX

CCOx

3

supported for LVCMOS outputs), T = -40°C to 85°C

A

Symbol

f_VCO

Parameter

Test Conditions

Minimum Typical Maximum Units

VCO Operating Frequency

PLL Input Reference Frequency

3000

10

4000

150

MHz

f_REF

Q[8:11], nQ[8:11]

Integer Divider

0.008

1000

Integer Output Dividers with

No Skew Adjustment

LVPECL,

LVDS,

HCSL

Q[0:7], nQ[0:7]

0.008

666.67

MHz

Output

Frequency

Outputs Fractional Divide

and/or

f_OUT

Q[0:7], nQ[0:7]

0.008

400

MHz

Added Skew Delay

Q[0:11], nQ[0:11]

REF_OUT

0.008

10

250

650

450

460

600

630

620

700

740

MHz

ps

LVCMOS

LVPECL

20% to 80%, F_OUT< 666MHz

20% to 80%, F_OUT 666MHz

20% to 80%

250

180

100

130

160

190

210

ps

LVDS

HCSL

ps

Output 

Rise and

20% to 80%

ps

t_R/ t_F

Q[0:11], nQ[0:11]

REF_OUT

20% to 80%, V_CCOx= 3.3V

20% to 80%, V_CCOx= 2.5V

20% to 80%, V_CCOx= 1.8V

20% to 80%

ps

Fall Times

ps

,

LVCMOS^{4 5}

ps

Measured on Differential

Waveform, ±150mV from

Center

LVPECL

LVDS

1

4

V/ns

Measured on Differential

Waveform, ±150mV from

Center

0.5

Output 

Slew

Measured on Differential

Waveform, ±150mV from

Center, V_CCOx= 2.5V,

f_OUT 125MHz

SR

Rate⁶

1.5

2.5

4

V/ns

HCSL

Measured on Differential

Waveform, ±150mV from

Center, V_CCOx= 3.3V,

f_OUT 125MHz

5.5

Q8, nQ8; Q9, nQ9^{8, 9, 10}

75

ps

Q10, nQ10; Q11, nQ11^8,

LVPECL

LVDS

9, 10

Q8, nQ8; Q9, nQ9^{8, 9, 10}

75

Q10, nQ10; Q11, nQ11^8,

75

9, 10

Bank

tsk(b)

Skew⁷

Q8, nQ8; Q9, nQ9^{8, 9, 10}

75

Q10, nQ10; Q11, nQ11^8,

HCSL

75

9, 10

Q8, nQ8; Q9, nQ9^{4, 8, 9, 11}

115

Q10, nQ10; Q11, nQ11^4,

LVCMOS

8, 9, 11

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October 28, 2016

8T49N1012 Datasheet

1

2

Table 12A. AC Characteristics, V

= 3.3V ±5% or 2.5V ±5%, V

= 3.3V ±5%, 2.5V ±5% or 1.8V ±5% (1.8V only

CCOx

CCX

3

supported for LVCMOS outputs), T = -40°C to 85°C (Continued)

A

Symbol

Parameter

Test Conditions

Minimum Typical Maximum Units

f_OUT 666.667MHz

45

40

50

55

60

%

LVPECL, LVDS, HCSL

Q[0:11], nQ[0:11]

Output 

Duty

f

_OUT> 666.667MHz

odc

Cycle¹²

LVCMOS

REF_OUT

f_OUT 62.5MHz¹³

dBc/

Hz



_SSB(1k)

1kHz

122.88MHz Output

-113

-130

-137

-149

-155

dBc/

Hz

_SSB(10k)

_SSB(100k)

_SSB(1M)

_SSB(10M)

_SSB(30M)

10kHz

122.88MHz Output

dBc/

Hz

100kHz

1MHz

Single Sideband 

Phase Noise¹⁴

dBc/

Hz

dBc/

Hz

10MHz

30MHz

dBc/

Hz

122.88MHz Output

-156

-85

Spurious Limit at Offset 800kHz

Internal OTP Startup¹⁶

122.88MHz Output¹⁵

dBc

from V_CCX>80% to

First Output Clock Edge

110

150

200

ms

I²C Frequency = 100kHz;

from V_CCX>80% to

First Output Clock Edge (0

retries)

I²C Frequency = 400kHz;

from V_CCX>80% to

First Output Clock Edge (0

retries)

I²C Frequency = 100kHz;

from V_CCX>80% to First

Output Clock Edge (31

retries)

I²C Frequency = 400kHz;

from V_CCX>80% to First

Output Clock Edge (31

retries)

150

130

925

360

ms

150

1200

500

tstartup

Startup Time

External EEPROM

Startup^{16, 17}

NOTE 1. V_CCXdenotes: V_CCD,V_CC,V_CCCS.

NOTE 2. V_CCOxdenotes: V_CCO0through V_CCO8,V_CCO10.

NOTE 3. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the

device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications

after thermal equilibrium has been reached under these conditions.

NOTE 4. Appropriate SE_MODE bit must be configured to select phase-aligned or phase-inverted operation.

NOTE 5. All Q and nQ outputs in phase-inverted operation.

NOTE 6. Measured from -150mV to +150mV on the differential waveform (derived from Qx minus nQx). The signal must be monotonic

through the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero

crosspoint.

NOTE 7. Defined as skew within a bank of outputs at the same voltages and with equal load conditions.

NOTE 8. This parameter is guaranteed by characterization. Not tested in production.

NOTE 9. This parameter is defined in accordance with JEDEC Standard 65.

NOTE 10. Measured at the output differential crosspoints.

NOTE 11. Measured at V_CCOx/2 of the rising edge. All Qx and nQx outputs phase-aligned.

NOTE 12. Duty Cycle of bypassed signals (input reference clocks or crystal input) is not adjusted by the device.

32

October 28, 2016

8T49N1012 Datasheet

NOTE 13. REF_OUT output duty cycle characterized with CLK input duty cycle between 48% and 52%.

NOTE 14. Both PLL and output dividers are in Integer Mode. Characterized with 8T49N1012-900.

NOTE 15. Tested with all outputs operating at 122.88MHz.

NOTE 16. This parameter is guaranteed by design.

NOTE 17. Assuming a clear I²C bus.

1

2

Table 12B. HCSL AC Characteristics, V

= 3.3V ±5% or 2.5V ±5%, V

Test Conditions

= 3.3V ±5% or 2.5V ±5%,

CCOx

CCX

3

T = -40°C to 85°C

A

Symbol

V_RB

Parameter

Ring-back Voltage Margin^{4 5}

Minimum

Typical

Maximum

Units

mV

ps

,

-100

500

100

,

t_STABLE

V_MAX

Time before V_RBis allowed^{4 5}

,

Absolute Max. Output Voltage^{6 7}

1150

mV

,

V_MIN

Absolute Min. Output Voltage^{6 8}

-300

250

,

V_CROSS

Absolute Crossing Voltage^{9 10}

550

140

Total Variation of V_CROSSover all

V_CROSS

mV

,

Edges^{9 11}

NOTE 1. V_CCXdenotes: V_CCD,V_CC,V_CCCS.

NOTE 2. V_CCOxdenotes: V_CCO0through V_CCO8,V_CCO10.

NOTE 3. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the

device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications

after thermal equilibrium has been reached under these conditions.

NOTE 4. Measurement taken from differential waveform.

NOTE 5. T_STABLEis the time the differential clock must maintain a minimum ±150mV differential voltage after rising/falling edges before it

is allowed to drop back into the V_RB±100mV differential range.

NOTE 6. Measurement taken from single-ended waveform.

NOTE 7. Defined as the maximum instantaneous voltage including overshoot.

NOTE 8. Defined as the minimum instantaneous voltage including undershoot.

NOTE 9. Measured at crossing point where the instantaneous voltage value of the rising edge of Qn equals the falling edge of nQn.

NOTE 10. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all

crossing points for this measurement.

NOTE 11. Defined as the total variation of all crossing voltages of rising Qn and falling nQn. This is the maximum allowed variance in

V_CROSSfor any particular system.

33

October 28, 2016

8T49N1012 Datasheet

1

2

Table 13. Typical RMS Phase Jitter, V

= 3.3V ±5% or 2.5V ±5%, V

= 3.3V ±5%, 2.5V ±5% or 1.8V ±5% (1.8V only

CCOx

CCX

3

supported for LVCMOS outputs), T = -40°C to 85°C

A

Symbol Parameter

Test Conditions

LVPECL

219

LVDS

218

220

190

251

296

HCSL

216

LVCMOS⁴

238

Units

fs

f_OUT= 122.88MHz⁶

f_OUT= 156.25MHz⁷

_OUT= 622.08MHz⁸

_OUT= 122.88MHz⁶

RMS

Phase Jitter⁵

Q[0:7] Integer

223

220

N/A⁹

fs

tjit()

(Random)

Integration Range:

12kHz - 20MHz

f

183

199

fs

Q[8:11]

f

251

240

263

fs

Q[0:7] Fractional

f

_OUT= 122.88MHz¹⁰

295

294

307

fs

NOTE 1. V_CCXdenotes: V_CCD,V_CC,V_CCCS.

NOTE 2. V_CCOxdenotes: V_CCO0through V_CCO8,V_CCO10.

NOTE 3. All outputs configured for the specific output type, as shown in the table.

NOTE 4. Qx and nQx are 180° out of phase.

NOTE 5. It is recommended to use IDT’s Timing Commander software to program the device for optimal jitter performance.

NOTE 6. Characterized with 8T49N1012-900.

NOTE 7. Characterized with 8T49N1012-901.

NOTE 8. Characterized with 8T49N1012-902.

NOTE 9. This frequency is not supported for LVCMOS operation.

NOTE 10. Characterized with 8T49N1012-903.

1

2

Table 14. PCI Express Jitter Specifications, V

= 3.3V ±5% or 2.5V ±5%, V

= 3.3V ±5% or 2.5V ±5%, 

CCX

CCOx

3

T = -40°C to 85°C

A

PCIe

Industry

Symbol

Parameter

Test Conditions

Minimum Typical Maximum Specification Units

ƒ = 100MHz, 40MHz Crystal Input,

Evaluation Band: 0Hz - Nyquist

(clock frequency/2)

tj

Phase Jitter

Peak-to-Peak^{4 5 6}

6

18

86

ps

,

(PCIe Gen 1)

ƒ = 100MHz, 40MHz Crystal Input,

t_{REFCLK_HF_RMS}

(PCIe Gen 2)

Phase Jitter RMS^{5, 6, 7}High Band: 1.5MHz - Nyquist (clock

frequency/2)

0.5

0.1

1.8

0.5

0.2

3.1

3.0

0.8

ps

t_{REFCLK_LF_RMS}

(PCIe Gen 2)

ƒ = 100MHz, 40MHz Crystal Input,

Phase Jitter RMS^{5, 6, 7}

Low Band: 10kHz - 1.5MHz

ƒ = 100MHz, 40MHz Crystal Input,

t_{REFCLK_RMS}

(PCIe Gen 3)

Phase Jitter RMS^{5, 6, 8}

Evaluation Band: 0Hz - Nyquist

(clock frequency/2)

NOTE 1. V_CCXdenotes: V_CCD,V_CC,V_CCCS.

NOTE 2. V_CCOxdenotes: V_CCO0through V_CCO8,V_CCO10.

NOTE 3. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the

device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications

after thermal equilibrium has been reached under these conditions.

NOTE 4. Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express

Gen1.

NOTE 5. This parameter is guaranteed by characterization. Not tested in production.

NOTE 6. Outputs configured for HSCL mode using integer output dividers. Fox 277LF-40-22 (40MHz, 12pF) crystal used with doubler

logic enabled.

NOTE 7. RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and

reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps RMS for t_REF-

_{CLK_HF_RMS}(High Band) and 3.0ps RMS for t_{REFCLK_LF_RMS}(Low Band).

NOTE 8. RMS jitter after applying system transfer function for the common clock architecture. This specification is based on the PCI Ex-

press Base Specification Revision 0.7, October 2009 and is subject to change pending the final release version of the specifica-

tion.

34

October 28, 2016

8T49N1012 Datasheet

Typical Phase Noise at 122.88MHz (3.3V)

Offset Frequency (Hz)

35

October 28, 2016

8T49N1012 Datasheet

Applications Information

Overdriving the XTAL Interface

The OSCI input can be overdriven by an LVCMOS driver or by one

side of a differential driver through an AC coupling capacitor. The

OSCO pin can be left floating. The amplitude of the input signal

should be between 500mV and 1.8V and the slew rate should not be

less than 0.2V/ns. For 3.3V LVCMOS inputs, the amplitude must be

reduced from full swing to at least half the swing in order to prevent

signal interference with the power rail and to reduce internal noise.

Figure 5A shows an example of the interface diagram for a high

speed 3.3V LVCMOS driver. This configuration requires that the sum

of the output impedance of the driver (Ro) and the series resistance

(Rs) equals the transmission line impedance. In addition, matched

termination at the crystal input will attenuate the signal in half. This

can be done in one of two ways. First, R1 and R2 in parallel should

equal the transmission line impedance. For most 50 applications,

R1 and R2 can be 100. This can also be accomplished by removing

R1 and changing R2 to 50. The values of the resistors can be

increased to reduce the loading for a slower and weaker LVCMOS

driver. Figure 5B shows an example of the interface diagram for an

LVPECL driver. This is a standard LVPECL termination with one side

of the driver feeding the OSCI input. It is recommended that all

components in the schematics be placed in the layout. Though some

components might not be used, they can be utilized for debugging

purposes. If the duty cycle of the input reference is not 50% then

increased phase noise may result. The datasheet specifications are

characterized and guaranteed by using a quartz crystal as the input.

OSCO

OSCI

VCC

R1

100

C1

Zo = 50Ω

Ro

RS

0.1μF

Zo = Ro + Rs

LVCMOS_Driver

R2

100

Figure 5A. General Diagram for LVCMOS Driver to XTAL Input Interface

OSCO

C2

Zo = 50Ω

OSCI

0.1μF

Zo = 50Ω

R1

50

R2

50

LVPECL_Driver

R3

50

Figure 5B. General Diagram for LVPECL Driver to XTAL Input Interface

36

October 28, 2016

8T49N1012 Datasheet

Wiring the Differential Input to Accept Single-Ended Levels

Figure 6 shows how a differential input can be wired to accept single

ended levels. The reference voltage V₁= V_CCD/2 is generated by the

bias resistors R1 and R2. The bypass capacitor (C1) is used to help

filter noise on the DC bias. This bias circuit should be located as

close to the input pin as possible. The ratio of R1 and R2 might need

to be adjusted to position the V₁in the center of the input voltage

swing. For example, if the input clock swing is 2.5V and V_CCD= 3.3V,

R1 and R2 value should be adjusted to set V₁at 1.25V. Similarly, if

the input clock swing is 1.8V and V_CCD= 3.3V, R1 and R2 value

should be adjusted to set V₁at 0.9V. It is recommended to always

use R1 and R2 to provide a known V₁voltage. The values below are

for when both the single ended swing and V_CCDare at the same

voltage. This configuration requires that the sum of the output

impedance of the driver (Ro) and the series resistance (Rs) equals

the transmission line impedance. In addition, matched termination at

the input will attenuate the signal in half. This can be done in one of

two ways. First, R3 and R4 in parallel should equal the transmission

line impedance. For most 50 applications, R3 and R4 can be 100.

The values of the resistors can be increased to reduce the loading for

slower and weaker LVCMOS driver. When using single-ended

signaling, the noise rejection benefits of differential signaling are

reduced. Even though the differential input can handle full rail

LVCMOS signaling, it is recommended that the amplitude be

reduced. The datasheet specifies a lower differential amplitude,

however this only applies to differential signals. For single-ended

applications, the swing can be larger, however V_ILcannot be less

than -0.3V and V_IHcannot be more than V_CCD+ 0.3V. Though some

of the recommended components might not be used, the pads should

be placed in the layout. They can be utilized for debugging purposes.

The datasheet specifications are characterized and guaranteed by

using a differential signal.

Figure 6. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels

37

October 28, 2016

8T49N1012 Datasheet

3.3V Differential Clock Input Interface

CLK/nCLK accepts LVDS, LVPECL, LVHSTL, HCSL and other

differential signals. Both V_SWINGand V_OHmust meet the V_PPand

V_CMRinput requirements. Figure 7A to Figure 7E show interface

examples for the CLK/nCLK input driven by the most common driver

types. The input interfaces suggested here are examples only.

Please consult with the vendor of the driver component to confirm the

driver termination requirements. For example, in Figure 7A, the input

termination applies for IDT open emitter LVHSTL drivers. If you are

using an LVHSTL driver from another vendor, use their termination

recommendation.

3.3V

1.8V

Zo = 50Ω

CLK

Zo = 50Ω

nCLK

Differential

Input

LVHSTL

R1

50Ω

R2

50Ω

IDT

LVHSTL Driver

Figure 7A. CLK/nCLK Input Driven by an 

Figure 7D. CLK/nCLK Input Driven by a 

IDT Open Emitter LVHSTL Driver

3.3V LVPECL Driver

Figure 7B. CLK/nCLK Input Driven by a 

Figure 7E. CLK/nCLK Input Driven by a 

3.3V LVPECL Driver

3.3V LVDS Driver

3.3V

*R3

*R4

CLK

nCLK

Differential

Input

HCSL

Figure 7C. CLK/nCLK Input Driven by a 

3.3V HCSL Driver

38

October 28, 2016

8T49N1012 Datasheet

2.5V Differential Clock Input Interface

CLK/nCLK accepts LVDS, LVPECL, LVHSTL and other differential

signals. Both V_SWINGand V_OHmust meet the V_PPand V_CMRinput

requirements. Figure 8A to Figure 8D show interface examples for

the CLK/nCLK input driven by the most common driver types. The

input interfaces suggested here are examples only. Please consult

with the vendor of the driver component to confirm the driver

termination requirements. For example, in Figure 8A, the input

termination applies for IDT open emitter LVHSTL drivers. If you are

using an LVHSTL driver from another vendor, use their termination

recommendation.

2.5V

1.8V

Zo = 50

CLK

Zo = 50

nCLK

Differential

Input

LVHSTL

R1

50

R2

50

IDT Open Emitter

LVHSTL Driver

Figure 8A. CLK/nCLK Input Driven by an 

Figure 8C. CLK/nCLK Input Driven by a 

IDT Open Emitter LVHSTL Driver

2.5V LVPECL Driver

Figure 8B. CLK/nCLK Input Driven by a 

Figure 8D. CLK/nCLK Input Driven by a 

2.5V LVPECL Driver

2.5V LVDS Driver

39

October 28, 2016

8T49N1012 Datasheet

Recommendations for Unused Input and Output Pins

Inputs:

Outputs:

CLK/nCLK Inputs

Differential Outputs

For applications not requiring the use the reference clock inputs,

both CLK and nCLK can be left floating. Though not required, but for

additional protection, a 1k resistor can be tied from CLK to ground.

It is recommended that CLK, nCLK not be driven with active signals

when not enabled for use by the PLL.

Unused differential outputs should be programmed to

high-impedance.

LVCMOS Outputs

If only one output from an output pair (such as Q0 is used and nQ0

remains unused) is intended for use, it is then recommended to

program the unused output to inverted mode and terminate both

outputs properly. If both outputs (Qx and nQx) are unused, it is

recommended to program the output buffers to high-impedance.

Crystal Inputs

For applications not requiring the use of the crystal oscillator input,

both OSCI and OSCO can be left floating. Though not required, but

for additional protection, a 1k resistor can be tied from OSCI to

ground.

LVCMOS Control Pins

All control pins have internal pullup or pulldown resistors; additional

resistance is not required but can be added for additional protection.

A 1k resistor can be used.

40

October 28, 2016

8T49N1012 Datasheet

LVDS Driver Termination

For a general LVDS interface, the recommended value for the

termination impedance (Z_T) is between 90 and 132. The actual

value should be selected to match the differential impedance (Z₀) of

your transmission line. A typical point-to-point LVDS design uses a

100 parallel resistor at the receiver and a 100 differential

transmission-line environment. In order to avoid any

transmission-line reflection issues, the components should be

surface mounted and must be placed as close to the receiver as

possible. IDT offers a full line of LVDS compliant devices with two

types of output structures: current source and voltage source. The

standard termination schematic as shown in Figure 9A can be used

with either type of output structure. Figure 9B, which can also be

used with both output types, is an optional termination with center tap

capacitance to help filter common mode noise. The capacitor value

should be approximately 50pF. If using a non-standard termination, it

is recommended to contact IDT and confirm if the output structure is

current source or voltage source type. In addition, since these

outputs are LVDS compatible, the input receiver’s amplitude and

common-mode input range should be verified for compatibility with

the output.

Z_O Z_T

LVDS

Driver

LVDS

Z_T

Receiver

Figure 9A.Standard LVDS Termination

Z

T

2

Z_O Z_T

LVDS

Driver

Receiver

C

Z

T

2

Figure 9B. Optional LVDS Termination

41

October 28, 2016

8T49N1012 Datasheet

Termination for 3.3V LVPECL Outputs

The clock layout topology shown below is a typical termination for

LVPECL outputs. The two different layouts mentioned are

recommended only as guidelines.

designed to drive 50 transmission lines. Matched impedance

techniques should be used to maximize operating frequency and

minimize signal distortion. Figure 10A and Figure 10B show two

different layouts which are recommended only as guidelines. Other

suitable clock layouts may exist and it would be recommended that

the board designers simulate to guarantee compatibility across all

printed circuit and clock component process variations.

The differential outputs generate ECL/LVPECL compatible outputs.

Therefore, terminating resistors (DC current path to ground) or

current sources must be used for functionality. These outputs are

3.3V

R3

R4

125

3.3V

Z_o= 50

+

_

Input

Z_o= 50

R1

84

R2

84

Figure 10A. 3.3V LVPECL Output Termination

Figure 10B. 3.3V LVPECL Output Termination

42

October 28, 2016

8T49N1012 Datasheet

Termination for 2.5V LVPECL Outputs

Figure 11A and Figure 11C show examples of termination for 2.5V

LVPECLdriver. These terminations are equivalent to terminating 50

to V_CCO– 2V. For V_CCO= 2.5V, the V_CCO– 2V is very close to ground

level. The R3 in Figure 11C can be eliminated and the termination is

shown in Figure 11B.

2.5V

V_DDO= 2.5V

2.5V

V_DDO= 2.5V

R1

R3

50Ω

250

+

50Ω

+

–

50Ω

–

2.5V LVPECL Driver

R1

50

R2

50

2.5V LVPECL Driver

R2

62.5

R4

62.5

R3

18

Figure 11A. 2.5V LVPECL Driver Termination Example

Figure 11C. 2.5V LVPECL Driver Termination Example

2.5V

V_DDO= 2.5V

50Ω

+

50Ω

–

2.5V LVPECL Driver

R1

50

R2

50

Figure 11B. 2.5V LVPECL Driver Termination Example

43

October 28, 2016

8T49N1012 Datasheet

2.5V and 3.3V HCSL Output Termination

Figure 12A is the recommended source termination for applications

where the driver and receiver will be on a separate PCBs. This

termination is the standard for PCI Express™ and HCSL output

types. All traces should be 50 impedance single-ended or 100

differential.

Rs

0.5" Max

L1

0-0.2"

L2

1-14"

L4

0.5 - 3.5"

L5

22 to 33 +/-5%

L1

L2

L4

L5

PCI Express

Connector

PCI Express

Driver

PCI Express

Add-in Card

0-0.2" L3

L3

49.9 +/- 5%

Rt

Figure 12A. Recommended Source Termination (where the driver and receiver will be on separate PCBs)

Figure 12B is the recommended termination for applications where a

point-to-point connection can be used. A point-to-point connection

contains both the driver and the receiver on the same PCB. With a

matched termination at the receiver, transmission-line reflections will

be minimized. In addition, a series resistor (Rs) at the driver offers

flexibility and can help dampen unwanted reflections. The optional

resistor can range from 0 to 33. All traces should be 50

impedance single-ended or 100 differential.

Rs

0.5" Max

L1

0-18"

L2

0-0.2"

L3

0 to 33

L1

L2

L3

PCI Express

Driver

49.9 +/- 5%

Rt

Figure 12B. Recommended Termination (where a point-to-point connection can be used)

44

October 28, 2016

8T49N1012 Datasheet

VFQFN EPAD Thermal Release Path

In order to maximize both the removal of heat from the package and

the electrical performance, a land pattern must be incorporated on

the Printed Circuit Board (PCB) within the footprint of the package

corresponding to the exposed metal pad or exposed heat slug on the

package, as shown in Figure 13. The solderable area on the PCB, as

defined by the solder mask, should be at least the same size/shape

as the exposed pad/slug area on the package to maximize the

thermal/electrical performance. Sufficient clearance should be

designed on the PCB between the outer edges of the land pattern

and the inner edges of pad pattern for the leads to avoid any shorts.

and dependent upon the package power dissipation as well as

electrical conductivity requirements. Thus, thermal and electrical

analysis and/or testing are recommended to determine the minimum

number needed. Maximum thermal and electrical performance is

achieved when an array of vias is incorporated in the land pattern. It

is recommended to use as many vias connected to ground as

possible. It is also recommended that the via diameter should be 12

to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is

desirable to avoid any solder wicking inside the via during the

soldering process which may result in voids in solder between the

exposed pad/slug and the thermal land. Precautions should be taken

to eliminate any solder voids between the exposed heat slug and the

land pattern. Note: These recommendations are to be used as a

guideline only. For further information, please refer to the Application

Note on the Surface Mount Assembly of Amkor’s Thermally/

Electrically Enhance Lead frame Base Package, Amkor Technology.

While the land pattern on the PCB provides a means of heat transfer

and electrical grounding from the package to the board through a

solder joint, thermal vias are necessary to effectively conduct from

the surface of the PCB to the ground plane(s). The land pattern must

be connected to ground through these vias. The vias act as “heat

pipes”. The number of vias (i.e. “heat pipes”) are application specific

SOLDER

EXPOSED HEAT SLUG

PIN PAD

GROUND PLANE

LAND PATTERN

(GROUND PAD)

PIN PAD

THERMAL VIA

Figure 13. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)

Schematic and Layout Information

Schematics for 8T49N1012 can be found on IDT.com. Please search

for the 8T49N1012 device and click on the link for evaluation board

schematics.

Crystal Recommendation

This device was characterized using FOX 277LF series through-hole

crystals including part #277LF-40-18 (40MHz) and 277LF-38.88-2

(38.88MHz). If a surface mount crystal is desired, we recommend

FOX Part #603-40-48 (40MHz) or FOX Part #603-38.88-7

(38.88MHz).

2

I C Serial EEPROM Recommendation

The 8T49N1012 was designed to operate with most standard I²C

serial EEPROMs of 256 bytes or larger. Atmel AT24C04C was used

during device characterization and is recommended for use. Please

contact IDT for review of any other I²C EEPROM’s compatibility with

the 8T49N1012.

45

October 28, 2016

8T49N1012 Datasheet

PCI Express Application Note

PCI Express jitter analysis methodology models the system

response to reference clock jitter. The block diagram below shows

the most frequently used Common Clock Architecture in which a

copy of the reference clock is provided to both ends of the PCI

Express Link.

In the jitter analysis, the transmit (Tx) and receive (Rx) serdes PLLs

are modeled as well as the phase interpolator in the receiver. These

transfer functions are called H1, H2, and H3 respectively. The overall

system transfer function at the receiver is:

Hts = H3s  H1s – H2s

The jitter spectrum seen by the receiver is the result of applying this

system transfer function to the clock spectrum X(s) and is:

Ys = Xs  H3s  H1s – H2s

PCIe Gen 2A Magnitude of Transfer Function

In order to generate time domain jitter numbers, an inverse Fourier

Transform is performed on X(s)*H3(s) * [H1(s) - H2(s)].

PCI Express Common Clock Architecture

For PCI Express Gen 1, one transfer function is defined and the

evaluation is performed over the entire spectrum: DC to Nyquist (e.g

for a 100MHz reference clock: 0Hz – 50MHz) and the jitter result is

reported in peak-peak.

PCIe Gen 2B Magnitude of Transfer Function

For PCI Express Gen 3, one transfer function is defined and the

evaluation is performed over the entire spectrum. The transfer

function parameters are different from Gen 1 and the jitter result is

reported in RMS.

PCIe Gen 1 Magnitude of Transfer Function

For PCI Express Gen 2, two transfer functions are defined with 2

evaluation ranges and the final jitter number is reported in rms. The

two evaluation ranges for PCI Express Gen 2 are 10kHz – 1.5MHz

(Low Band) and 1.5MHz – Nyquist (High Band). The plots show the

individual transfer functions as well as the overall transfer function Ht.

PCIe Gen 3 Magnitude of Transfer Function

For a more thorough overview of PCI Express jitter analysis

methodology, please refer to IDT Application Note, PCI Express

Application Note.

46

October 28, 2016

8T49N1012 Datasheet

Power Dissipation and Thermal Considerations

The 8T49N1012 is a multi-functional, high speed device that targets a wide variety of clock frequencies and applications. Since this device is

highly programmable with a broad range of features and functionality, the power consumption will vary as each of these features and functions

is enabled.

The 8T49N1012 device was designed and characterized to operate within the ambient industrial temperature range of -40°C to +85°C. The

ambient temperature represents the temperature around the device, not the junction temperature. When using the device in extreme cases,

such as maximum operating frequency and high ambient temperature, external air flow may be required in order to ensure a safe and reliable

junction temperature. Extreme care must be taken to avoid exceeding 125°C junction temperature.

The power calculation examples below were generated using a maximum ambient temperature and supply voltage. For many applications, the

power consumption will be much lower. Please contact IDT technical support for any concerns on calculating the power dissipation for your

own specific configuration.

Power Domains

The 8T49N1012 device has a number of separate power domains that can be independently enabled and disabled via register accesses (all

power supply pins must still be connected to a valid supply voltage). Figure 14 below indicates the individual domains and the associated power

pins.

Q0 Output Buffer & Mux, Div A (V_CCO0

Q1 Output Buffer & Mux, Div B (V_CCO1

Q2 Output Buffer & Mux, Div C (V_CCO2

Q3 Output Buffer & Mux, Div D (V_CCO3

)

Control & Status Buffers (V_CCCS

)

LOS, LOCK, nRST, SA1, SDATA, SCLK,

CLK_SEL, OE[1:0], PLL_BYP, REF_OUT

Core Digital Logic (V_CCD)

Q4 Output Buffer & Mux, Div E (V_CCO4

Q5 Output Buffer & Mux, Div F (V_CCO5

)

Q6 Output Buffer & Mux, Div G (V_CCO6

Q7 Output Buffer & Mux, Div H (V_CCO7

)

Core Memory (V_CC)

OTP Memory

Q8 & Q9 Output Buffers & Mux, Div I (V_CCO8

)

Core Analog Circuitry (V_CCA)

CLK, nCLK, Oscillator and PLL

Q10 & Q11 Output Buffers & Mux, Div J (V_CCO10

)

Figure 14. 8T49N1012 Power Domains

For the output paths shown above, there are many different structures that are used. Power consumption data will vary slightly depending on

the structure used as shown in the Output Current Calculation tables on the following pages.

47

October 28, 2016

8T49N1012 Datasheet

Power Consumption Calculation

Determining total power consumption involves several steps:

1. Determine the power consumption using maximum current values for core and analog voltage supplies from Table 8A through Table 8B.

2. Determine the nominal power consumption of each enabled output path.

a. This consists of a base amount of power that is independent of operating frequency, as shown in Table 16A through Table 16G

(depending on the chosen output protocol).

b. Then there is a variable amount of power that is related to the output frequency. This can be determined by multiplying the output

frequency by the FQ_Factor shown in Table 16A through Table 16G.

3. All of the above totals are then summed.

Thermal Considerations

Once the total power consumption has been determined, it is necessary to calculate the maximum operating junction temperature for the device

under the environmental conditions it will operate in. Thermal conduction paths, air flow rate and ambient air temperature are factors that can

affect this. The thermal conduction path refers to whether heat is to be conducted away via a heatsink, via airflow or via conduction into the

PCB through the device pads (including the ePAD). Thermal conduction data is provided for typical scenarios in Table 15 below. Please contact

IDT for assistance in calculating results under other scenarios.

Table 15. Thermal Resistance  for 72-Lead VFQFN, Forced Convection

JA

_JAby Velocity

Meters per Second

0

1

2

Multi-Layer PCB, JEDEC Standard Test Boards

16.1°C/W

12.4°C/W

11.1°C/W

48

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8T49N1012 Datasheet

Current Consumption Data and Equations

Table 16A. 3.3V LVPECL/HCSL Output Current

Calculation Table

Table 16D. 2.5V LVPECL/HCSL Output Current

Calculation Table

LVPECL/HCSL FQ_Factor (µA/MHz)

Base_Current (mA)

LVPECL/HCSL FQ_Factor (µA/MHz)

Base_Current (mA)

Q[0:7]¹

15.0

Q[0:7]¹

12.0

43.2

41.9

Q[8:9],

16.4

Q[8:9],

11.5

34.7

32.0

Q[10:11]²

NOTE 1. The values are per channel (one divider and an output

pair.

NOTE 1. The values are per channel (one divider and an output

pair.

NOTE 2. The values are based on a divider and two output pairs.

Table 16B. 3.3V LVDS Output Current Calculation Table

Table 16E. 2.5V LVDS Output Current Calculation Table

LVDS

FQ_Factor (µA/MHz)

Base_Current (mA)

LVDS

FQ_Factor (µA/MHz)

Base_Current (mA)

Q[0:7]¹

15.0

52.6

12.0

50.6

Q[8:9]],

Q[10:11]²

Q[8:9],

Q[10:11]²

16.4

52.5

11.5

48.9

NOTE 1. The values are per channel (one divider and an output

pair.

NOTE 1. The values are per channel (one divider and an output

pair.

NOTE 2. The values are based on a divider and two output pairs.

Table 16F. 2.5V LVCMOS Output Current Calculation

Table

Table 16C. 3.3V LVCMOS Output Current Calculation

Table

LVCMOS

Q[0:7]¹

Q[8:9], Q[10:11]²

Base_Current (mA)

LVCMOS

Q[0:7]¹

Q[8:9], Q[10:11]²

Base_Current (mA)

40.2

28.7

41.2

30.5

NOTE 1. The values are per channel (one divider and two 

LVCMOS outputs).

NOTE 2. The values are based on a divider and four LVCMOS

outputs

NOTE 2. The values are based on a divider and four LVCMOS

outputs.

Table 16G. 1.8V LVCMOS Output Current Calculation

Table

LVCMOS

Q[0:7]¹

Q[8:9], Q[10:11]²

Base_Current (mA)

39.7

27.5

NOTE 1. The values are per channel (one divider and two 

LVCMOS outputs).

NOTE 2. The values are based on a divider and four LVCMOS

outputs

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October 28, 2016

8T49N1012 Datasheet

Applying the values to the following equation will yield output current by frequency:

Qx Current = FQ_Factor * Frequency + Base_Current

where:

Qx Current is the specific output current according to output type and frequency

FQ_Factor is used for calculating current increase due to output frequency

Base_Current is the base current for each output path independent of output frequency

The second step is to multiply the power dissipated by the thermal impedance to determine the maximum power gradient, using the following

equation:

T_J= T_A+ (_JA* Pd_total

)

where:

T_Jis the junction temperature (°C)

T_Ais the ambient temperature (°C)

_JAis the thermal resistance value from Table 15, dependent on ambient airflow (°C/W)

Pd_totalis the total power dissipation of the 8T49N1012 under usage conditions, including power dissipated due to loading (W).

Note that the power dissipation per output pair due to loading is assumed to be 27.95mW for LVPECL outputs and 44.5mW for HCSL outputs.

When selecting LVCMOS outputs, power dissipation through the load will vary based on a variety of factors including termination type and trace

length. For these examples, power dissipation through loading will be calculated using C_PD(found in Table 2) and output frequency:

2

Pd_OUT= C_PD* F_OUT* V_CCO

where:

Pd_OUTis the power dissipation of the output (W)

C_PDis the power dissipation capacitance (F)

F_OUTis the output frequency of the selected output (Hz)

V_CCOis the voltage supplied to the appropriate output (V)

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October 28, 2016

8T49N1012 Datasheet

Example Calculations

Example 1. PLL is running in Integer mode and REF_OUT Off (3.3V Core Voltage)

V_CCO

Output

Q0

Output Type

LVCMOS

LVPECL

HCSL

LVPECL

LVCMOS

LVDS

Frequency (MHz)

25

1.8

3.3

2.5

3.3

2.5

Q1

125

25

Q2

Q3

Q4

100

150

Q5

Q6

Q7

Q8

LVPECL

LVDS

Q9

Q10

Q11

LVDS

Core Power Dissipation:

• Core Supply Current, I_CC= 28mA (V_CCD= V_CC= V_CCCS= 3.3V)

• Analog Supply Current, I_CCA= 170mA (V_CCA= 3.3V)

• Total Core and Analog Power = 3.465V * (28 + 170)mA = 686.1mW

Output Power Dissipation:

Q0 Current = 15pF * 25MHz * 1.89V + 39.7mA = 40.4mA

Q1 Current = 17pF * 125MHz * 3.465V + 41.2mA = 48.6mA

Q2 Current = 15µA/MHz * 25MHz + 43.2mA = 43.6mA

Q3 Current = 15µA/MHz * 100MHz + 43.2mA = 44.7mA

Q4 Current = 15µA/MHz * 100MHz + 43.2mA = 44.7mA

Q5 Current = 15µA/MHz * 100MHz + 43.2mA = 44.7mA

Q6 Current = 15pF * 100MHz * 2.5V + 40.2mA = 44mA

Q7 Current = 15µA/MHz * 100MHz + 52.6mA = 54.1mA

Q[8:9] Current = 16.4µA/MHz * 100MHz + 34.7mA = 36.3mA

Q[10:11] Current = 11.5µA/MHz * 150MHz + 48.9mA = 50.6mA

• Output Current @ 1.8V = 40.4mA

• Output Current @ 2.5V = 44mA + 50.6mA = 94.6mA

• Output Current @ 3.3V = 48.6mA + 43.6mA + 44.7mA + 44.7mA + 44.7mA + 54.1mA + 36.3mA = 316.7mA

• Power dissipated due to switching:

LVPECL Outputs = 5 * 27.95mW = 139.8mW

HCSL Output = 1 * 44.5mW = 44.5mW

Total Output Power = (1.89V * 40.4mA) + (2.625V * 94.6mA) + (3.465V * 316.7mA) + 139.8mW + 44.5mW = 1606.35mW

Total Power Dissipation:

• Total Power = 686.1mW + 1606.35mW = 2292.4mW

Junction Temperature Calculation:

With an ambient temperature of 85°C and no airflow, the junction temperature is:

T_J= 85°C + 16.1°C/W * 2.2924W = 121.9°C (which is below the maximum allowable temperature)

Due to the 8T49N1012 flexibility and highly configurable outputs, the power dissipation will vary depending on the specific device configuration.

The power calculations example shown above illustrates a single configuration and its corresponding power figures. If additional support on

calculating power consumption for other configurations is needed, please contact IDT (clocks@idt.com).

51

October 28, 2016

8T49N1012 Datasheet

Reliability Information

Table 17.  vs. Air Flow Table for a 72-Lead VFQFN

JA

_JAvs. Air Flow

Meters per Second

0

1

2

Multi-Layer PCB, JEDEC Standard Test Boards

16.1°C/W

12.4°C/W

11.1°C/W

NOTE: Theta JA (_JA)values calculated using a 4-layer JEDEC PCB (114.3mm x 101.6mm), with 2oz. (70um) copper plating on all 4 layers.

Transistor Count

The transistor count for 8T49N1012 is: 579,607

52

October 28, 2016

8T49N1012 Datasheet

72-Lead VFQFN Package Outline

53

October 28, 2016

8T49N1012 Datasheet

72-Lead VFQFN Package Outline, continued

54

October 28, 2016

8T49N1012 Datasheet

72-Lead VFQFN Package Outline, continued

55

October 28, 2016

8T49N1012 Datasheet

Ordering Information

Table 18. Ordering Information

Part/Order Number

Marking

Package

Shipping Packaging

Temperature

8T49N1012-dddNLGI

IDT8T49N1012-dddNLGI

72-Lead VFQFN, Lead-Free

Tray

-40C to +85C

Tape & Reel, Pin 1

Orientation: EIA-481-C

8T49N1012-dddNLGI8

IDT8T49N1012-dddNLGI

72-Lead VFQFN, Lead-Free

-40C to +85C

Tape & Reel, Pin 1

Orientation: EIA-481-D

8T49N1012-dddNLGI#

IDT8T49N1012-dddNLGI

NOTE: For the specific, publicly available -ddd order codes, refer to FemtoClock NG Universal Frequency Translator Ordering Product

Information document. For custom -ddd order codes, please contact IDT for more information.

Table 19. Pin 1 Orientation in Tape and Reel Packaging

Part Number Suffix

Pin 1 Orientation

Illustration

CARRIER TAPE TOPSIDE

(Round Sprocket Holes)

Correct Pin 1 ORIENTATION

NLGI8

Quadrant 1 (EIA-481-C)

USER DIRECTION OF FEED

Correct Pin 1 ORIENTATION

CARRIER TAPE TOPSIDE

(Round Sprocket Holes)

NLGI#

Quadrant 2 (EIA-481-D)

USER DIRECTION OF FEED

56

October 28, 2016

8T49N1012 Datasheet

Revision History Sheet

Date

Description of Change

Crystal Recommendation - deleted IDT crystal reference.

October 28, 2016

Corporate Headquarters

6024 Silver Creek Valley Road

San Jose, CA 95138 USA

www.IDT.com

Sales

Tech Support

www.idt.com/go/support

1-800-345-7015 or 408-284-8200

Fax: 408-284-2775

www.IDT.com/go/sales

DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications

and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein

is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability,

or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.

IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably

expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.

Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of

IDT or their respective third party owners.

For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary.


型号：	8T49N1012-999NLGI8
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	FemtoClock NG 12-Output Frequency Synthesizer
文件：	总57页 (文件大小：1310K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

8T49N1012-999NLGI8 [IDT]

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