8T79S838-08NLGI [IDT]
1-to-8 Differential to Universal Output Fanout Buffer;
| 型号： | 8T79S838-08NLGI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 1-to-8 Differential to Universal Output Fanout Buffer 驱动 逻辑集成电路 |
| 文件： | 总25页 (文件大小：418K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1-to-8 Differential to Universal Output
Fanout Buffer
IDT8T79S838-08I
DATA SHEET
General Description
Features
The IDT8T79S838-08I is a high performance, 1-to-8, differential input
to universal output fanout buffer. The device is designed for signal
fanout of high-frequency clock signals in applications requiring output
frequencies generated simultaneously. The IDT8T79S838-08I is
optimized for 3.3V and 2.5V supply voltages and a temperature range
of -40°C to 85°C. The device is packaged in a space-saving 32 lead
VFQFN package.
• Four banks of two output pairs
• Individual output type control, LVDS or LVPECL, via
serial interface
• Individual outputs remain enabled while serial loading new
device configurations
• One differential PCLK, nPCLK input
• PCLK, nPCLK input pair can accept the following differential input
levels: LVPECL, LVDS levels
• Maximum input frequency: 1.5GHz
• LVCMOS control inputs
• Individual output enable/disable control via serial interface
• 2.375V to 3.465V supply voltage operation
• -40°C to 85°C ambient operating temperature
• Lead-free (RoHS 6) packaging
Pin Assignment
Block Diagram
QA0
nQA0
VCC
VCC 25
VEE 26
16 VCC
QA1
15 VEE
nQA1
Pulldown
PCLK
IDT8T79S838-08I
Pullup / Pulldown
nQA1 27
QA1 28
nQA0 29
QA0 30
VCC 31
14 QD0
13 nQD0
12 QD1
11 nQD1
10 VCC
nPCLK
QB0
32 lead VFQFN
5mm x 5mm x 0.925mm
Pad size 3.15mm x 3.15mm
NL package
nQB0
VEE
VEE
QB1
nQB1
Top View
QC0
SDATA 32
9
PWR_SEL
nQC0
Pulldown
PWR_SEL
QC1
nQC1
VEE
QD0
nQD0
QD1
nQD1
Pulldown
OE
Output Type and
Output Enable
logic
Pulldown
Pulldown
Pulldown
LE
SCLK
SDATA
MISO
VEE VEE VEE VEE
IDT8T79S838-08NLGI REVISION A JANUARY 29, 2014
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©2014 Integrated Device Technology, Inc.
IDT8T79S838-08I Data Sheet
1-to-8 Differential to Universal Output Fanout Buffer
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
Name
SCLK
MISO
nc
Type
Description
1
2
3
4
Input
Output
Unused
Input
Pulldown Serial Control Port Mode Data Input. LVCMOS/LVTTL interface levels.
Serial Control Port Mode Data Output. LVCMOS/LVTTL interface levels.
No connect.
PCLK
Pulldown Non-inverting differential clock input.
Pullup /
5
nPCLK
Input
Inverting differential clock input. VCC / 2 by default when left floating.
Pulldown
Default output disable. LVCMOS/LVTTL interface levels.
See “Table 3B. OE Truth Table”.
6
OE
VCC
LE
Input
Power
Input
Pulldown
7, 10, 16, 25, 31
8
Power supply voltage pin.
Serial Control Port Mode Enable. Latches data when the pin gets a high level.
Pulldown
Outputs remain enabled when LE is low. LVCMOS/LVTTL interface levels.
9
PWR_SEL
nQD1, QD1
nQD0, QD0
VEE
Input
Output
Output
Power
Output
Output
Output
Output
Output
Output
Input
Pulldown Power supply selection. See “Table 3A. PWR_SEL Truth Table”.
Differential Bank D output pair.
11, 12
13, 14
15, 26
17, 18
19, 20
21, 22
23, 24
27, 28
29, 30
32
Differential Bank D output pair.
Negative power supply pins.
nQC1, QC1
nQC0, QC0
nQB1, QB1
nQB0, QB0
nQA1, QA1
nQA0, QA0
SDATA
Differential Bank C output pair. LVPECL or LVDS interface levels.
Differential Bank C output pair. LVPECL or LVDS interface levels.
Differential Bank B output pair. LVPECL or LVDS interface levels.
Differential Bank B output pair. LVPECL or LVDS interface levels.
Differential Bank A output pair. LVPECL or LVDS interface levels.
Differential Bank A output pair. LVPECL or LVDS interface levels.
Pulldown Serial Control Port Mode Data Input. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See “Table 2. Pin Characteristics” for typical values.
Table 2. Pin Characteristics
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
2
Maximum
Units
pF
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
RPULLDOWN
RPULLUP
51
k
k
51
VCC = 3.3V
VCC = 2.5V
125
125
ROUT
Output Impedance
MISO
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IDT8T79S838-08I Data Sheet
1-to-8 Differential to Universal Output Fanout Buffer
Function Tables
Table 3A. PWR_SEL Truth Table
PWR_SEL
Function
L (Connect to VEE
)
2.5V power supply
3.3V power supply
H (Connect to VCC
)
Table 3B. OE Truth Table
OE
L (default)
H
Function
All outputs disabled (Low/High static mode), regardless of individual OE registers set by Serial Interface.
Outputs enabled according to individual OE registers set by Serial Interface (see “Table 3E. Configuration Table”).
Output Type Control and Start-up Status
Two output types are available: LVDS and LVPECL. The part features
four modes of output type control:
At startup, the outputs are in static Low/High LVDS mode until the
part has been configured. Disabled outputs are in static Low/High
mode. A global hardware Output Enable (OE pin #6) enables or
disables all outputs at once. The global hardware OE has priority over
a serial interface configuration.
•
•
•
•
Eight LVDS outputs
Eight LVPECL outputs
Two LVDS (QAx) + six LVPECL (QBx, QCx, QDx)
Two LVPECL (QAx) + six LVDS (QBx, QCx, QDx)
Table 3C. Output Type Control
Control Bits
D2
D1
Output Configuration
LOW
HIGH
HIGH
LOW
LOW
HIGH
LOW
HIGH
8 LVDS Outputs
8 LVPECL Outputs
2 LVDS (QAx) + 6 LVPECL (QBx, QCx, QDx) Outputs
2 LVPECL (QAx) + 6 LVDS (QBx, QCx, QDx) Outputs
IDT8T79S838-08NLGI REVISION A JANUARY 29, 2014
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IDT8T79S838-08I Data Sheet
1-to-8 Differential to Universal Output Fanout Buffer
Serial Interface
Configuration of the IDT8T79S838I-08 is achieved by writing 10
configuration bits over serial interface. All 10 bits have to be written in
sequence.
After writing the 10 configuration bits, the LE pin must remain at high
level for outputs to toggle.
W
6+
W+,
W/2
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W
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+(
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Figure 1. Serial Interface Timing Diagram for Write and Read Access
Table 3D. Timing AC Characteristics
Symbol
tS
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
ns
Data to Clock Setup Time
Data to Clock Hold Time
Clock to LE Hold Time
Clock High Duration
Clock Low Duration
10
10
10
25
25
10
10
tH
ns
tHE
ns
tHI
ns
tLO
ns
tSL
LE to Clock Setup Time
LE to SCLK Setup Time
Clock to MISO Delay Time
ns
tSH
ns
tDELAY
10
ns
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
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IDT8T79S838-08I Data Sheet
1-to-8 Differential to Universal Output Fanout Buffer
Table 3E. Configuration Table
Bit
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
Name
oed1
oed0
oec1
oec0
oeb1
oeb0
oea1
oea0
ot1
Function
Output Enable QD1
Output Enable QD0
Output Enable QC1
Output Enable QC0
Output Enable QB1
Output Enable QB0
Output Enable QA1
Output Enable QA0
Banks QB, QC, QD Output Type
Bank QA Output Type
Truth Table
Low: Disabled
High: Enabled
Low: LVDS
High: LVPECL
ot0
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IDT8T79S838-08I Data Sheet
1-to-8 Differential to Universal Output Fanout Buffer
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC
Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Rating
Supply Voltage, VCC
Inputs, VI
4.6V
-0.5V to VCC + 0.5V
-0.5V to VCC + 0.5V
Outputs, VO (LVCMOS)
Outputs, IO (LVPECL)
Continuous Current
Surge Current
50mA
100mA
Outputs, IO (LVDS)
Continuos Current
Surge Current
10mA
15mA
Package Thermal Impedance, JA
48.9C/W (0 mps)
-65C to 150C
Storage Temperature, TSTG
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VCC = 3.3V 5%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
VCC Power Supply Voltage
IEE
Test Conditions
Minimum
Typical
3.3
Maximum
3.465
135
Units
V
3.135
Power Supply Current
Power Supply Current
D[10:1] = HIGH, LVPECL
120
mA
mA
ICC
D[10:3] = HIGH; D[2:1] = LOW, LVDS
215
235
Table 4B. Power Supply DC Characteristics, VCC = 2.5V 5%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
VCC Power Supply Voltage
IEE
Test Conditions
Minimum
Typical
2.5
Maximum
2.625
125
Units
V
2.375
Power Supply Current
Power Supply Current
D[10:1] = HIGH, LVPECL
114
mA
mA
ICC
D[10:3] = HIGH; D[2:1] = LOW, LVDS
210
230
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IDT8T79S838-08I Data Sheet
1-to-8 Differential to Universal Output Fanout Buffer
Table 4C. LVCMOS/LVTTL DC Characteristics, VCC = 3.3V 5% or 2.5V 5%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
CC = 3.3V
VCC = 2.5V
CC = 3.3V
Minimum
2.2
Typical
Maximum
VCC + 0.3
VCC + 0.3
0.8
Units
V
V
V
V
V
VIH Input High Voltage
1.7
V
-0.3
VIL
Input Low Voltage
VCC = 2.5V
-0.3
0.7
OE, LE,
PWR_SEL,
SCLK, SDATA
Input High
Current
IIH
VCC = VIN = 3.465V or 2.625V
150
µA
µA
OE, LE,
PWR_SEL,
SCLK, SDATA
Input Low
Current
IIL
VCC = 3.465V or 2.625V, VIN = 0V
-10
VCC = 3.465V, IOH = -1mA
VCC = 2.625V, IOH = -1mA
2.6
1.8
V
V
Output High
Voltage
VOH
MISO
MISO
Output Low
Voltage
VCC = 3.465V or 2.625V,
IOL = 1mA
VOL
0.5
V
Table 4D. Differential Input DC Characteristics, VCC = 3.3V 5% or 2.5V 5%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
IIH Input High Current
Test Conditions
Minimum
Typical
Maximum
Units
PCLK,
nPCLK
VCC = VIN = 3.465V or 2.625V
150
µA
PCLK
V
V
CC = 3.465V or 2.625V, VIN = 0V
CC = 3.465V or 2.625V, VIN = 0V
-10
-150
0.15
µA
µA
V
IIL
Input Low Current
nPCLK
VPP
Peak-to-Peak Voltage
1.3
Common Mode Input Voltage;
NOTE 1
VCMR
1.0
VCC – 0.5
V
NOTE 1: Common mode input voltage is defined at the cross point.
Table 4E. LVPECL DC Characteristics, VCC = 3.3V 5% or 2.5V 5%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
VCC – 1.3
VCC – 2.0
0.6
Typical
Maximum
VCC – 0.75
VCC – 1.6
1.0
Units
VOH
Output High Voltage; NOTE 1
V
V
V
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50 to VCC – 2V.
Table 4F. LVDS DC Characteristics, VCC = 3.3V 5% or 2.5V 5%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
454
Units
mV
mV
V
VOD
Differential Output Voltage
247
VOD
VOS
VOD Magnitude Change
Offset Voltage
50
1.125
1.45
50
VOS
VOS Magnitude Change
mV
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IDT8T79S838-08I Data Sheet
1-to-8 Differential to Universal Output Fanout Buffer
AC Electrical Characteristics
Table 5. AC Characteristics, VCC = 3.3V 5% or 2.5V 5%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
PCLK,
nPCLK
fIN
Input Frequency
1.5
GHz
fOUT
Output Frequency
Qx, nQx
LVPECL
LVDS
1.5
650
650
80
GHz
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
%
200
200
Propagation Delay;
NOTE 5
tPD
LVPECL
LVDS
Output Skew;
NOTE 1, 2
tsk(o)
tsk(b)
tsk(pp)
tR / tF
odc
80
LVPECL
LVDS
55
Bank Skew;
NOTE 1, 3
55
LVPECL
LVDS
450
450
300
300
60
Part-to-Part Skew;
NOTE 1, 4
LVPECL
LVDS
20% to 80%
20% to 80%
50
50
40
40
Output Rise/Fall
Time
LVPECL
LVDS
Output Duty Cycle
60
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential
crosspoints.
NOTE 3: Defined as skew within a bank of outputs at the same voltage and with equal load conditions.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential crosspoints.
NOTE 5: Measured from the differential input crosspoint to the differential output crosspoint.
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IDT8T79S838-08I Data Sheet
1-to-8 Differential to Universal Output Fanout Buffer
Parameter Measurement Information
2V
2V
SCOPE
V
SCOPE
CC
V
Qx
CC
Qx
nQx
nQx
VEE
VEE
-1.3V 0.165V
-0.5V 0.125V
3.3V LVPECL Output Load Test Circuit
2.5V LVPECL Output Load Test Circuit
V
V
CC
CC
3.3V LVDS Output Load Test Circuit
2.5V LVDS Output Load Test Circuit
V
CC
nPCLK
PCLK
nPCLK
PCLK
nQX[0:1]
QX[0:1]
tPD
V
EE
Differential Input Levels
Propagation Delay
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IDT8T79S838-08I Data Sheet
1-to-8 Differential to Universal Output Fanout Buffer
Parameter Measurement Information, continued
nQXx
nQx
QXx
Qx
nQXy
nQy
QXy
tsk(b)
Where X = a single output bank
Qy
Output Skew
Bank Skew
Part 1
nQx
nQX[0:1]
80%
80%
Qx
VOD
20%
Part 2
nQy
20%
QX[0:1]
tF
tR
Qy
tsk(pp)
Part-to-Part Skew
LVDS Output Rise/Fall Time
nQX[0:1]
QX[0:1]
nQX[0:1]
QX[0:1]
LVPECL Output Rise/Fall Time
Output Duty Cycle/Pulse Width/Period
IDT8T79S838-08NLGI REVISION A JANUARY 29, 2014
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IDT8T79S838-08I Data Sheet
1-to-8 Differential to Universal Output Fanout Buffer
Parameter Measurement Information, continued
VCC
VCC
out
out
DC Input
LVDS
LVDS
DC Input
100
out
VOS/∆ VOS
out
ä
Offset Voltage Setup
Differential Output Voltage Setup
Applications Information
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
LVCMOS Control Pins
LVPECL Outputs
All control pins have internal pulldowns; additional resistance is not
required but can be added for additional protection. A 1k resistor
can be used.
Any unused LVPECL output pairs can be left floating. We
recommend that there is no trace attached. Both sides of the
differential output pair should either be left floating or terminated.
LVDS Outputs
All unused LVDS output pairs can be either left floating or terminated
with 100 across. If they are left floating, there should be no trace
attached.
LVCMOS Outputs
The unused LVCMOS output can be left floating. There should be no
trace attached.
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IDT8T79S838-08I Data Sheet
1-to-8 Differential to Universal Output Fanout Buffer
Wiring the Differential Input to Accept Single-Ended Levels
Figure 2 shows how a differential input can be wired to accept single
ended levels. The reference voltage V1= VCC/2 is generated by the
bias resistors R1 and R2. The bypass capacitor (C1) is used to help
filter noise on the DC bias. This bias circuit should be located as close
to the input pin as possible. The ratio of R1 and R2 might need to be
adjusted to position the V1in the center of the input voltage swing. For
example, if the input clock swing is 2.5V and VCC = 3.3V, R1 and R2
value should be adjusted to set V1 at 1.25V. The values below are for
when both the single ended swing and VCC are at the same voltage.
This configuration requires that the sum of the output impedance of
the driver (Ro) and the series resistance (Rs) equals the transmission
line impedance. In addition, matched termination at the input will at-
tenuate the signal in half. This can be done in one of two ways. First,
R3 and R4 in parallel should equal the transmission line impedance.
For most 50 applications, R3 and R4 can be 100. The values of
the resistors can be increased to reduce the loading for slower and
weaker LVCMOS driver. When using single-ended signaling, the
noise rejection benefits of differential signaling are reduced. Even
though the differential input can handle full rail LVCMOS signaling, it
is recommended that the amplitude be reduced. The datasheet spec-
ifies a lower differential amplitude, however this only applies to differ-
ential signals. For single-ended applications, the swing can be larger,
however VIL cannot be less than -0.3V and VIH cannot be more than
VCC + 0.3V. Though some of the recommended components might
not be used, the pads should be placed in the layout. They can be uti-
lized for debugging purposes. The datasheet specifications are char-
acterized and guaranteed by using a differential signal.
VCC
VC C
VCC
VCC
R3
100
R1
1K
Ro
RS
Zo = 50 Ohm
+
Receiv er
Driver
V1
R4
-
100
R2
1K
Ro +Rs = Zo
C1
0.1uF
Figure 2. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels
IDT8T79S838-08NLGI REVISION A JANUARY 29, 2014
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IDT8T79S838-08I Data Sheet
1-to-8 Differential to Universal Output Fanout Buffer
3.3V LVPECL Clock Input Interface
The PCLK /nPCLK accepts LVPECL, LVDS and other differential sig-
nals. Both VSWING and VOH must meet the VPP and VCMR input re-
quirements. Figures 3A to 3C show interface examples for the PCLK/
nPCLK input driven by the most common driver types. The input in-
terfaces suggested here are examples only. If the driver is from an-
other vendor, use their termination recommendation. Please consult
with the vendor of the driver component to confirm the driver termi-
nation requirements.
3.3V
3.3V
3.3V
R3
125Ω
R4
125Ω
Zo = 50Ω
Zo = 50Ω
PCLK
nPCLK
LVPECL
Input
LVPECL
R1
84Ω
R2
84Ω
Figure 3A. PCLK/nPCLK Input Driven by a
3.3V LVPECL Driver
Figure 3B. PCLK/nPCLK Input Driven by a
3.3V LVPECL Driver with AC Couple
3.3V
3.3V
Zo = 50
PCLK
R1
100
nPCLK
Zo = 50
LVPECL
Input
LVDS
Figure 3C. PCLK/nPCLK Input Driven by a
3.3V LVDS Driver
IDT8T79S838-08NLGI REVISION A JANUARY 29, 2014
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©2014 Integrated Device Technology, Inc.
IDT8T79S838-08I Data Sheet
1-to-8 Differential to Universal Output Fanout Buffer
2.5V LVPECL Clock Input Interface
The PCLK /nPCLK accepts LVPECL, LVDS and other differential sig-
nals. Both VSWING and VOH must meet the VPP and VCMR input re-
quirements. Figures 4A to 4C show interface examples for the PCLK/
nPCLK input driven by the most common driver types. The input in-
terfaces suggested here are examples only. If the driver is from an-
other vendor, use their termination recommendation. Please consult
with the vendor of the driver component to confirm the driver termi-
nation requirements.
2.5V
2.5V
2.5V
PCLK
nPCLK
LVPECL
LVPECL
Input
Figure 4A. PCLK/nPCLK Input Driven by a
2.5V LVPECL Driver
Figure 4B. PCLK/nPCLK Input Driven by a
2.5V LVPECL Driver with AC Couple
PCLK
nPCLK
Figure 4C. PCLK/nPCLK Input Driven by a
2.5V LVDS Driver
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©2014 Integrated Device Technology, Inc.
IDT8T79S838-08I Data Sheet
1-to-8 Differential to Universal Output Fanout Buffer
LVDS Driver Termination
For a general LVDS interface, the recommended value for the
termination impedance (ZT) is between 90 and 132. The actual
value should be selected to match the differential impedance (Z0) of
your transmission line. A typical point-to-point LVDS design uses a
100 parallel resistor at the receiver and a 100 differential
transmission-line environment. In order to avoid any
standard termination schematic as shown in Figure 5A can be used
with either type of output structure. Figure 5B, which can also be
used with both output types, is an optional termination with center tap
capacitance to help filter common mode noise. The capacitor value
should be approximately 50pF. If using a non-standard termination, it
is recommended to contact IDT and confirm if the output structure is
current source or voltage source type. In addition, since these
outputs are LVDS compatible, the input receiver’s amplitude and
common-mode input range should be verified for compatibility with
the output.
transmission-line reflection issues, the components should be
surface mounted and must be placed as close to the receiver as
possible. IDT offers a full line of LVDS compliant devices with two
types of output structures: current source and voltage source. The
ZO ZT
LVDS
Receiver
LVDS
Driver
ZT
Figure 5A. Standard Termination
ZT
ZO ZT
LVDS
Driver
LVDS
Receiver
2
ZT
2
C
Figure 5B. Optional Termination
LVDS Termination
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©2014 Integrated Device Technology, Inc.
IDT8T79S838-08I Data Sheet
1-to-8 Differential to Universal Output Fanout Buffer
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are recom-
mended only as guidelines.
functionality. These outputs are designed to drive 50 transmission
lines. Matched impedance techniques should be used to maximize
operating frequency and minimize signal distortion. Figures 6A and
6B show two different layouts which are recommended only as guide-
lines. Other suitable clock layouts may exist and it would be recom-
mended that the board designers simulate to guarantee compatibility
across all printed circuit and clock component process variations.
The differential outputs are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs. Therefore, terminating resis-
tors (DC current path to ground) or current sources must be used for
3.3V
R3
125
R4
125
3.3V
3.3V
Z
o = 50
+
_
LVPECL
Input
Zo = 50
R1
84
R2
84
Figure 6A. 3.3V LVPECL Output Termination
Figure 6B. 3.3V LVPECL Output Termination
IDT8T79S838-08NLGI REVISION A JANUARY 29, 2014
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©2014 Integrated Device Technology, Inc.
IDT8T79S838-08I Data Sheet
1-to-8 Differential to Universal Output Fanout Buffer
Termination for 2.5V LVPECL Outputs
Figure 7A and Figure 7B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminating 50
to VCC – 2V. For VCC = 2.5V, the VCC – 2V is very close to ground
level. The R3 in Figure 7B can be eliminated and the termination is
shown in Figure 7C.
2.5V
VCC = 2.5V
2.5V
2.5V
VCC = 2.5V
50Ω
R1
250Ω
R3
250Ω
+
50Ω
50Ω
+
–
50Ω
–
2.5V LVPECL Driver
R1
50Ω
R2
50Ω
2.5V LVPECL Driver
R2
62.5Ω
R4
62.5Ω
R3
18Ω
Figure 7A. 2.5V LVPECL Driver Termination Example
Figure 7B. 2.5V LVPECL Driver Termination Example
2.5V
VCC = 2.5V
50Ω
+
50Ω
–
2.5V LVPECL Driver
R1
50Ω
R2
50Ω
Figure 7C. 2.5V LVPECL Driver Termination Example
IDT8T79S838-08NLGI REVISION A JANUARY 29, 2014
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©2014 Integrated Device Technology, Inc.
IDT8T79S838-08I Data Sheet
1-to-8 Differential to Universal Output Fanout Buffer
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package
corresponding to the exposed metal pad or exposed heat slug on the
package, as shown in Figure 8. The solderable area on the PCB, as
defined by the solder mask, should be at least the same size/shape
as the exposed pad/slug area on the package to maximize the ther-
mal/electrical performance. Sufficient clearance should be designed
on the PCB between the outer edges of the land pattern and the inner
edges of pad pattern for the leads to avoid any shorts.
pendent upon the package power dissipation as well as electrical
conductivity requirements. Thus, thermal and electrical analysis
and/or testing are recommended to determine the minimum number
needed. Maximum thermal and electrical performance is achieved
when an array of vias is incorporated in the land pattern. It is recom-
mended to use as many vias connected to ground as possible. It is
also recommended that the via diameter should be 12 to 13mils (0.30
to 0.33mm) with 1oz copper via barrel plating. This is desirable to
avoid any solder wicking inside the via during the soldering process
which may result in voids in solder between the exposed pad/slug
and the thermal land. Precautions should be taken to eliminate any
solder voids between the exposed heat slug and the land pattern.
Note: These recommendations are to be used as a guideline only.
For further information, please refer to the Application Note on the
Surface Mount Assembly of Amkor’s Thermally/ Electrically Enhance
Leadframe Base Package, Amkor Technology.
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a sol-
der joint, thermal vias are necessary to effectively conduct from the
surface of the PCB to the ground plane(s). The land pattern must be
connected to ground through these vias. The vias act as “heat pipes”.
The number of vias (i.e. “heat pipes”) are application specific and de-
SOLDER
SOLDER
PIN
PIN
EXPOSED HEAT SLUG
PIN PAD
GROUND PLANE
LAND PATTERN
(GROUND PAD)
PIN PAD
THERMAL VIA
Figure 8. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
IDT8T79S838-08NLGI REVISION A JANUARY 29, 2014
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©2014 Integrated Device Technology, Inc.
IDT8T79S838-08I Data Sheet
1-to-8 Differential to Universal Output Fanout Buffer
3.3V LVDS Power Considerations
This section provides information on power dissipation and junction temperature for the IDT8T79S838-08I. Equations and example calculations
are also provided.
1. Power Dissipation.
The total power dissipation for the IDT8T79S838-08I is the sum of the core power plus the power dissipated due to the load.
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
•
Power (core)MAX = VCC_MAX * ICC_MAX = 3.465V * 235mA = 814.3mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 48.9°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.814W * 48.9°C/W = 124.8°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 6. Thermal Resistance JA for 32-lead VFQFN Package
JA by Velocity
Meters per Second
0
1
2
Multi-Layer PCB, JEDEC Standard Test Boards
48.9°C/W
42°C/W
39.4°C/W
IDT8T79S838-08NLGI REVISION A JANUARY 29, 2014
19
©2014 Integrated Device Technology, Inc.
IDT8T79S838-08I Data Sheet
1-to-8 Differential to Universal Output Fanout Buffer
3.3V LVPECL Power Considerations
This section provides information on power dissipation and junction temperature for the IDT8T79S838-08I, for all outputs that are configured
to LVPECL. Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the IDT8T79S838-08I is the sum of the core power plus the power dissipated due to loading.
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated due to loading.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 135mA = 467.8mW
Power (outputs)MAX = 31.55mW/Loaded Output pair
If all outputs are loaded, the total power is 8 * 31.55mW = 252.4mW
Total Power_MAX (3.465V, with all outputs switching) = 467.8mW + 252.4mW = 720.2mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no airflow and
a multi-layer board, the appropriate value is 48.9°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.720W * 48.9°C/W = 120.2°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 7. Thermal Resistance JA for 32-lead VFQFN Package
JA by Velocity
Meters per Second
0
1
2
Multi-Layer PCB, JEDEC Standard Test Boards
48.9°C/W
42°C/W
39.4°C/W
IDT8T79S838-08NLGI REVISION A JANUARY 29, 2014
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©2014 Integrated Device Technology, Inc.
IDT8T79S838-08I Data Sheet
1-to-8 Differential to Universal Output Fanout Buffer
3. Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the LVPECL output pairs.
LVPECL output driver circuit and termination are shown in Figure 9.
VCC
Q1
VOUT
RL
VCC - 2V
Figure 9. LVPECL Driver Circuit and Termination
To calculate power dissipation per output pair due to loading, use the following equations which assume a 50 load, and a termination voltage
of VCC – 2V.
•
•
For logic high, VOUT = VOH_MAX = VCC_MAX – 0.75V
(VCC_MAX – VOH_MAX) = 0.75V
For logic low, VOUT = VOL_MAX = VCC_MAX – 1.6V
(VCC_MAX – VOL_MAX) = 1.6V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX– (VCC_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX) = [(2V – (VCC_MAX – VOH_MAX))/RL] * (VCC_MAX– VOH_MAX) =
[(2V – 0.75V)/50] * 0.75V = 18.75mW
Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOL_MAX) = [(2V – (VCC_MAX – VOL_MAX))/RL] * (VCC_MAX – VOL_MAX) =
[(2V – 1.6V)/50] * 1.6V = 12.80mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 31.55mW
IDT8T79S838-08NLGI REVISION A JANUARY 29, 2014
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©2014 Integrated Device Technology, Inc.
IDT8T79S838-08I Data Sheet
1-to-8 Differential to Universal Output Fanout Buffer
Reliability Information
Table 8. JA vs. Air Flow Table for a 32-lead VFQFN Package
JA vs. Air Flow
Meters per Second
0
1
2
Multi-Layer PCB, JEDEC Standard Test Boards
48.9°C/W
42.0°C/W
39.4°C/W
Transistor Count
The transistor count for IDT8T79S838-08I is: 2618
IDT8T79S838-08NLGI REVISION A JANUARY 29, 2014
22
©2014 Integrated Device Technology, Inc.
IDT8T79S838-08I Data Sheet
1-to-8 Differential to Universal Output Fanout Buffer
32 Lead VFQFN Package Outline and Package Dimensions
IDT8T79S838-08NLGI REVISION A JANUARY 29, 2014
23
©2014 Integrated Device Technology, Inc.
IDT8T79S838-08I Data Sheet
1-to-8 Differential to Universal Output Fanout Buffer
Ordering Information
Table 9. Ordering Information
Part/Order Number
Marking
Package
Shipping Packaging
Tray
Temperature
-40C to 85C
-40C to 85C
8T79S838-08NLGI
8T79S838-08NLGI8
IDT8T79S838-08NLGI
IDT8T79S838-08NLGI
“Lead-Free” 32 Lead VFQFN
“Lead-Free” 32 Lead VFQFN
Tape & Reel
IDT8T79S838-08NLGI REVISION A JANUARY 29, 2014
24
©2014 Integrated Device Technology, Inc.
IDT8T79S838-08I Data Sheet
1-to-8 Differential to Universal Output Fanout Buffer
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DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document,
including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not
guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the
suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any
license under intellectual property rights of IDT or any third parties.
IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to signifi-
cantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third
party owners.
Copyright 2014. All rights reserved.
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