8V89704ANLGI_技术文档

FemtoClock^®NG Crystal-to-3.3V, 2.5V LVPECL IDT8V89704I

Clock Generator w/Fanout Buffer

DATA SHEET

General Description

Features

The IDT8V89704I is a four output Clock Generator with LVPECL

outputs. The IDT8V89704I can generate any one of four frequencies

from a single crystal or reference clock. The four frequencies are

selected from the Function Table (Table 3) by two frequency

selection pins. Note the desired programmed frequencies must be

used with the corresponding crystal as indicated in Table 3.

• Fourth Generation FemtoClock^®NG PLL technology

• Ideal for 10G EPON ONU and 1G/10G OLT Line Card

• Four LVPECL outputs

• One Reference LVCMOS clock output

• The CLK, nCLK input pair can accept the following differential

input levels: LVPECL, LVDS, HCSL

Excellent phase noise performance is maintained with IDT’s Fourth

Generation FemtoClock^®NG PLL technology.

• RMS phase jitter at 156.25MHz (12kHz - 20MHz): 0.239ps

(typical)

• Full 2.5V or 3.3V power supply

• -40°C to 85°C ambient operating temperature

• Lead-free (RoHS 6) packaging

Pin Assignment

32 31 30 29 28 27 26 25

1

2

3

4

5

6

7

8

VEE

V^EE

24

23

22

21

20

Q0

Q2

nQ0

nQ2

V^CCO

Q3

V^CCO

Q1

nQ1

V^EE

nc

nQ3

19

18

17

V^EE

FSEL1

9

10 11 12 13 14 15 16

IDT8V89704I

32 Lead VFQFN

5mm x 5mm x 0.925mm package body

3.15mm x 3.15mm EPad

NL Package

IDT8V89704ANLGI REVISION A APRIL 3, 2013

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IDT8V89704I Data Sheet

FEMTOCLOCK^®NG CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR

Block Diagram

Pulldown

REF_OUT

CLK_SEL

_

XTAL IN

Xtal

Osc.

25MHz

Q0, nQ0

Q1, nQ1

_

XTAL OUT

0

1

Phase

Detector

+

Charge

Pump

PS

Pulldown

CLK

FemtoClock® NG

÷P

÷N

VCO

nCLK

/

Pullup

Pulldown

Q2 , nQ2

Q3, nQ3

÷M

Pulldown

FSEL 0

FSEL1

Control

Logic

IDT8V89704ANLGI REVISION A APRIL 3, 2013

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IDT8V89704I Data Sheet

FEMTOCLOCK^®NG CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR

Pin Description and Pin Characteristic Tables

Table 1. Pin Descriptions

Number

Name

Type

Description

1, 7, 11, 15,

18, 24, 27, 30

V_EE

Power

Negative supply pins.

2, 3

4, 21

5, 6

8

Q0, nQ0

V_CCO

Output

Power

Differential output pair. LVPECL interface levels.

Output supply pins.

Q1, nQ1

nc

Output

Unused

Differential output pair. LVPECL interface levels.

No connect.

9,

10

XTAL_IN

XTAL_OUT

Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.

Crystal frequency is selected from Table 3A.

Input

12

CLK

Pulldown

Non-inverting differential clock input.

Pullup/

Pulldown

13

nCLK

Inverting differential clock input. Internal resistor bias to V_CC/2.

FSEL0,

FSEL1

14, 17

Input

Pulldown

Frequency select pins. LVCMOS/LVTTL interface levels.

16, 31

19, 20

22, 23

25, 26

28

V_CC

Power

Output

Core supply pins.

nQ3, Q3

nQ2, Q2

RESERVED

V_CCA

Differential output pair. LVPECL interface levels.

Reserved.

Power

Input

Analog supply pin.

29

CLK_SEL

REF_OUT

Pulldown

Input source control pin. LVCMOS/LVTTL interface levels.

Single-ended reference output. LVCMOS/LVTTL interface levels.

32

Output

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

Symbol

C_IN

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

pF

Input Capacitance

2

C_PD

Power Dissipation Capacitance

Input Pulldown Resistor

Input Pullup Resistor

10

51

20

pF

R_PULLDOWN

R_PULLUP

R_OUT

k



Output Impedance

REF_OUT

IDT8V89704ANLGI REVISION A APRIL 3, 2013

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IDT8V89704I Data Sheet

FEMTOCLOCK^®NG CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR

Function Table

Table 3A. Control Input Function Table

Inputs

Outputs

CLK_EN

CLK_SEL

Selected Source

Q0

nQ0

Q1:Q3

0

CLK

Disabled; LOW

Disabled; HIGH

Disabled; LOW

XTAL_IN,

XTAL_OUT

0

1

0

1

Disabled; LOW

Enabled

Disabled; HIGH

Enabled

Disabled; LOW

Enabled

CLK

XTAL_IN,

XTAL_OUT

Enabled

NOTE: After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock or crystal oscillator edge as

shown in Figure 1.

NOTE: In the active mode, the state of the outputs are a function of the CLK input as described in Table 3B.

Enabled

Disabled

CLK

CLK_EN

nQ0

Q0:Q3

Frequency Configuration

Table 3B. Frequency Configuration Examples

Output

Frequency

(MHz)

InputFrequency

Input Clock

Divider (P)

Input Clock

Pre-scale (PS)

M

N

VCO Frequency

(MHz)

FSEL1

FSEL0

(MHz)

Divider Divider

0

125

25

1

x2

40

16

2000

(default) (default)

0

1

0

1

156.25

250

25

1

x2

50

40

16

8

2500

2000

100

20

IDT8V89704ANLGI REVISION A APRIL 3, 2013

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IDT8V89704I Data Sheet

FEMTOCLOCK^®NG CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR

Absolute Maximum Ratings

NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.

These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond

those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for

extended periods may affect product reliability.

Item

Rating

Supply Voltage, V_CC

3.6V

Inputs, V_I

XTAL_IN

Other Input

0V to 2V

-0.5V to V_CC+ 0.5V

Outputs, V_O(LVCMOS)

-0.5V to V_CC+ 0.5V

Outputs, I_O(LVPECL)

Continuous Current

Surge Current

50mA

100mA

Package Thermal Impedance, _JA

33.1C/W (0 mps)

-65C to 150C

Storage Temperature, T_STG

DC Electrical Characteristics

Table 4A. Power Supply DC Characteristics, V_CC= V_CCO= 3.3V 5%, V_EE= 0V, T_A= -40°C to 85°C

Symbol Parameter

Test Conditions

Minimum

3.135

Typical

3.3

Maximum

3.465

V_CC

Units

V

V_CC

V_CCA

V_CCO

I_CCA

I_EE

Core Supply Voltage

Analog Supply Voltage

Output Supply Voltage

Analog Supply Current

Power Supply Current

V_CC– 0.32

3.135

3.3

V

3.3

3.465

32

V

28

mA

183

204

Table 4B. Power Supply DC Characteristics, V_CC= V_CCO= 2.5V 5%, V_EE= 0V, T_A= -40°C to 85°C

Symbol Parameter

Test Conditions

Minimum

2.375

Typical

2.5

Maximum

2.625

V_CC

Units

V

V_CC

V_CCA

V_CCO

I_CCA

I_EE

Core Supply Voltage

Analog Supply Voltage

Output Supply Voltage

Analog Supply Current

Power Supply Current

V_CC– 0.15

2.375

2.5

V

2.5

2.625

30

V

26

mA

173

192

IDT8V89704ANLGI REVISION A APRIL 3, 2013

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IDT8V89704I Data Sheet

FEMTOCLOCK^®NG CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR

Table 4C. LVCMOS/LVTTL DC Characteristics, V_CC= V_CCO= 3.3V 5% or 2.5V 5%, V_EE= 0V, T_A= -40°C to 85°C

Symbol Parameter

Test Conditions

V_CC= 3.3V

V_CC= 2.5V

V_CC= 3.3V

V_CC= 2.5V

Minimum

2

Typical

Maximum

V_CC+ 0.3

0.8

Units

V

Input High

Voltage

FSEL[1:0],

CLK_SEL

V_IH

1.7

CLK_SEL

FSEL[1:0]

-0.3

Input Low

Voltage

V_IL

-0.3

0.7

V_CC= 3.3V or 2.5V

-0.3

0.5

Input

I_IH

FSEL[1:0],

CLK_SEL

V

_CC= V_IN= 3.465V or 2.625V

150

µA

High Current

Input

I_IL

FSEL[1:0],

CLK_SEL

V_CC= 3.465V or 2.625V, V_IN= 0V

_CCO= 3.465V

-5

Low Current

Output

REF_OUT

V

2.6

1.8

V

V_OH

High Voltage;

NOTE 1

V_CCO= 2.625V

Output

V_OL

Low Voltage;

NOTE 1

REF_OUT

V_CCO= 3.465V or 2.625V

0.5

V

NOTE 1: Outputs terminated with 50 to V_CCO/2. In the Parameter Measurement Information Section, see Output Load Test Circuit Diagrams.

Table 4D. Differential DC Characteristics, V_CC= V_CCO= 3.3V 5% or 2.5V 5%, V_EE= 0V, T_A= -40°C to 85°C

Symbol Parameter

Test Conditions

Minimum

Typical

Maximum

Units

Input

I_IH

CLK, nCLK

V

_CC= V_IN= 3.465V or 2.625V

150

µA

High Current

nCLK

CLK

V_CC= 3.465V or 2.625V, V_IN= 0V

-150

-5

µA

V

Input

I_IL

Low Current

V_PP

Peak-to-Peak Voltage

0.15

1.3

Common Mode Input Voltage;

NOTE 1

V_CMR

V_EE

V_EE– 0.85

V

NOTE 1: Common mode input voltage is at the cross point.

Table 4E. LVPECL DC Characteristics, V_CC= V_CCO= 3.3V 5% or 2.5V 5%, V_EE= 0V, T_A= -40°C to 85°C

Symbol Parameter

Test Conditions

Minimum

V_CCO– 1.1

V_CCO– 2.0

0.6

Typical

Maximum

V_CCO– 0.75

V_CCO– 1.6

1.0

Units

V_OH

Output High Voltage; NOTE 1

V

V_OL

Output Low Voltage; NOTE 1

V_SWING

Peak-to-Peak Output Voltage Swing

NOTE 1: Outputs termination with 50 to V_CCO– 2V.

IDT8V89704ANLGI REVISION A APRIL 3, 2013

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IDT8V89704I Data Sheet

FEMTOCLOCK^®NG CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR

Table 5. Crystal Characteristics

Parameter

Test Conditions

Minimum

Typical

Fundamental

25

Maximum

Units

Mode of Oscillation

Frequency

MHz



Equivalent Series Resistance (ESR)

Shunt Capacitance

50

7

pF

NOTE: Characterized using an 12pF parallel resonant crystal.

AC Electrical Characteristics

Table 6. AC Characteristics, V_CC= V_CCO= 3.3V 5% or 2.5V 5% V_EE= 0V, T_A= -40°C to 85°C

Symbol Parameter

Test Conditions

Minimum

Typical

Maximum

Units

f_{DIFF_IN}

Differential Input Frequency

25

MHz

25MHz, REF_OUT, Integration

Range: 12kHz - 5MHz

0.215

0.239

0.230

0.190

0.239

0.195

0.215

0.305

0.330

0.320

0.265

0.325

0.260

0.295

35

ps

%

100MHz, Integration Range: 12kHz

– 20MHz

125MHz, Integration Range: 12kHz

– 20MHz

RMS Phase Jitter, Random;

NOTE 1

125MHz, Integration Range: 10kHz

– 1MHz

tjit(Ø)

156.25MHz, Integration Range:

12kHz – 20MHz

156.25MHz, Integration Range:

10kHz – 1MHz

250MHz, Integration Range: 12kHz

– 20MHz

Output Skew; NOTE 2, 3

Output Rise/Fall Time

Output Duty Cycle

tsk(o)

t_R/ t_F

odc

20% - 80%

100

48

400

52

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium

has been reached under these conditions.

NOTE: Phase Noise Characterized using 25MHz, 12pF resonant crystal.

NOTE 1: Refer to Phase Noise plot.

NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential crosspoint.

NOTE 3: These parameters are guaranteed by characterization. Not tested in production.

IDT8V89704ANLGI REVISION A APRIL 3, 2013

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IDT8V89704I Data Sheet

FEMTOCLOCK^®NG CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR

Typical Phase Noise at 156.25MHz (12k – 20MHz, 3.3V)

Offset Frequency (Hz)

IDT8V89704ANLGI REVISION A APRIL 3, 2013

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IDT8V89704I Data Sheet

FEMTOCLOCK^®NG CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR

Parameter Measurement Information

2V

5

SCOPE

V

DD,

V

Qx

DD,

V

DDO

V

DDO

DDA

V

DDA

nQx

V_EE

-0.5V 0.125V

-1.3V 0.165V

3.3V LVPECL Output Load Test Circuit

2.5V LVPECL Output Load Test Circuit

1.65V 5%

1.25V 5%

5

SCOPE

V

DD,

DDO

V_DDA

Qx

GND

-1.65V 5%

-1.25V 5%

3.3V LVCMOS Output Load Test Circuit

2.5V LVCMOS Output Load Test Circuit

Phase Noise Plot

V

CC

nCLK

V_PP

Cross Points

CLK

V_CMR

Offset Frequency

f₁

f₂

V

EE

RMS Phase Jitter =

1

*

Area Under Curve Defined by the Offset Frequency Markers

2 * * ƒ

Differential Input Levels

RMS Phase Jitter

IDT8V89704ANLGI REVISION A APRIL 3, 2013

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IDT8V89704I Data Sheet

FEMTOCLOCK^®NG CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR

Parameter Measurement Information, continued

nQ[0:3]

Q[0:3]

nQx

Qx

t_PW

t_PERIOD

nQy

t_PW

Qy

odc =

x 100%

tsk(o)

t_PERIOD

Output Skew

Output Duty Cycle/Pulse Width/Period

nQ[0:3]

80%

t_F

80%

t_R

V_SWING

20%

Q[0:3]

LVPECL Output Rise/Fall Time

IDT8V89704ANLGI REVISION A APRIL 3, 2013

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IDT8V89704I Data Sheet

FEMTOCLOCK^®NG CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR

Applications Information

Wiring the Differential Input to Accept Single-Ended Levels

Figure 1 shows how a differential input can be wired to accept single

ended levels. The reference voltage V₁= V_CC/2 is generated by the

bias resistors R1 and R2. The bypass capacitor (C1) is used to help

filter noise on the DC bias. This bias circuit should be located as close

to the input pin as possible. The ratio of R1 and R2 might need to be

adjusted to position the V₁in the center of the input voltage swing.

For example, if the input clock swing is 2.5V and V_CC= 3.3V, R1 and

R2 value should be adjusted to set V₁at 1.25V. The values below are

for when both the single ended swing and V_CCare at the same

voltage. This configuration requires that the sum of the output

impedance of the driver (Ro) and the series resistance (Rs) equals

the transmission line impedance. In addition, matched termination at

the input will attenuate the signal in half. This can be done in one of

two ways. First, R3 and R4 in parallel should equal the transmission

line impedance. For most 50 applications, R3 and R4 can be 100.

The values of the resistors can be increased to reduce the loading for

slower and weaker LVCMOS driver. When using single-ended

signaling, the noise rejection benefits of differential signaling are

reduced. Even though the differential input can handle full rail

LVCMOS signaling, it is recommended that the amplitude be

reduced. The datasheet specifies a lower differential amplitude,

however this only applies to differential signals. For single-ended

applications, the swing can be larger, however V_ILcannot be less

than -0.3V and V_IHcannot be more than V_CC+ 0.3V. Though some

of the recommended components might not be used, the pads

should be placed in the layout. They can be utilized for debugging

purposes. The datasheet specifications are characterized and

guaranteed by using a differential signal.

Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels

IDT8V89704ANLGI REVISION A APRIL 3, 2013

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IDT8V89704I Data Sheet

FEMTOCLOCK^®NG CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR

Overdriving the XTAL Interface

The XTAL_IN input can accept a single-ended LVCMOS signal

through an AC coupling capacitor. A general interface diagram is

shown in Figure 2A. The XTAL_OUT pin can be left floating. The

maximum amplitude of the input signal should not exceed 2V and the

input edge rate can be as slow as 10ns. This configuration requires

that the output impedance of the driver (Ro) plus the series

resistance (Rs) equals the transmission line impedance. In addition,

matched termination at the crystal input will attenuate the signal in

half. This can be done in one of two ways. First, R1 and R2 in parallel

should equal the transmission line impedance. For most 50

applications, R1 and R2 can be 100. This can also be

accomplished by removing R1 and making R2 50. By overdriving

the crystal oscillator, the device will be functional, but note, the device

performance is guaranteed by using a quartz crystal.

3.3V

R1

100

C1

Ro

~ 7 Ohm

Zo = 50 Ohm

XTAL_I N

RS

43

0.1uF

R2

Driver_LVCMOS

100

XTAL_OU T

Crystal Input Interf ace

Figure 2A. General Diagram for LVCMOS Driver to XTAL Input Interface

VCC=3.3V

C1

Zo = 50 Ohm

XTAL_IN

0.1uF

R1

50

Zo = 50 Ohm

XTAL_OUT

LVPECL

Cry stal Input Interface

R2

50

R3

50

Figure 2B. General Diagram for LVPECL Driver to XTAL Input Interface

IDT8V89704ANLGI REVISION A APRIL 3, 2013

12

IDT8V89704I Data Sheet

FEMTOCLOCK^®NG CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR

3.3V Differential Clock Input Interface

The CLK /nCLK accepts LVDS, LVPECL, HCSL and other differential

signals. Both V_SWINGand V_OHmust meet the V_PPand V_CMRinput

requirements. Figures 3A to 3D show interface examples for the

CLK/nCLK input driven by the most common driver types. The input

interfaces suggested here are examples only. If the driver is from

another vendor, use their termination recommendation. Please

consult with the vendor of the driver component to confirm the driver

termination requirements.

3.3V

Zo = 50Ω

CLK

Zo = 50Ω

nCLK

Differential

Input

LVPECL

nCLK

R1

50Ω

R2

50Ω

Differential

Input

LVPECL

R2

50Ω

Figure 3A. CLK/nCLK Input Driven by a

3.3V LVPECL Driver

Figure 3B. CLK/nCLK Input Driven by a

3.3V LVPECL Driver

3.3V

Zo = 50Ω

*R3

*R4

CLK

R1

100Ω

nCLK

Zo = 50Ω

Differential

Input

Receiver

HCSL

LVDS

Figure 3C. CLK/nCLK Input Driven by a

3.3V HCSL Driver

Figure 3D. CLK/nCLK Input Driven by a 3.3V LVDS Driver

IDT8V89704ANLGI REVISION A APRIL 3, 2013

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IDT8V89704I Data Sheet

FEMTOCLOCK^®NG CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR

2.5V Differential Clock Input Interface

The CLK /nCLK accepts LVDS, LVPECL, HCSL and other differential

signals. Both V_SWINGand V_OHmust meet the V_PPand V_CMRinput

requirements. Figures 4A to 4D show interface examples for the

CLK/nCLK input driven by the most common driver types. The input

interfaces suggested here are examples only. If the driver is from

another vendor, use their termination recommendation. Please

consult with the vendor of the driver component to confirm the driver

termination requirements.

2.5V

R3

R4

Zo = 50

250

CLK

Zo = 50

CLK

Zo = 50

nCLK

Differential

Input

LVPECL

nCLK

R1

50

R2

50

Differential

Input

LVPECL

R1

R2

62.5

R3

18

Figure 4A. CLK/nCLK Input Driven by a

2.5V LVPECL Driver

Figure 4B. CLK/nCLK Input Driven by a

2.5V LVPECL Driver

2.5V

Zo = 50

*R3

*R4

33

CLK

R1

100

Zo = 50

nCLK

Zo = 50

Differential

Input

Differential

Input

HCSL

R1

50

R2

50

LVDS

*Optional R3 and R4 can be 0

Figure 4C. CLK/nCLK Input Driven by a

2.5V HCSL Driver

Figure 4D. CLK/nCLK Input Driven by a 2.5V LVDS Driver

IDT8V89704ANLGI REVISION A APRIL 3, 2013

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IDT8V89704I Data Sheet

FEMTOCLOCK^®NG CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR

Recommendations for Unused Input and Output Pins

Inputs:

Outputs:

LVCMOS Control Pins

LVPECL Outputs

All control pins have internal pulldowns; additional resistance is not

required but can be added for additional protection. A 1k resistor

can be used.

All unused LVPECL outputs can be left floating. We recommend that

there is no trace attached. Both sides of the differential output pair

should either be left floating or terminated.

LVCMOS Outputs

CLK/nCLK Inputs

The unused LVCMOS output can be left floating. There should be no

trace attached.

For applications not requiring the use of the differential input, both

CLK and nCLK can be left floating. Though not required, but for

additional protection, a 1k resistor can be tied from CLK to ground.

Crystal Inputs

For applications not requiring the use of the crystal oscillator input,

both XTAL_IN and XTAL_OUT can be left floating. Though not

required, but for additional protection, a 1k resistor can be tied from

XTAL_IN to ground.

Termination for 3.3V LVPECL Outputs

The clock layout topology shown below is a typical termination for

LVPECL outputs. The two different layouts mentioned are

recommended only as guidelines.

transmission lines. Matched impedance techniques should be used

to maximize operating frequency and minimize signal distortion.

Figures 5A and 5B show two different layouts which are

recommended only as guidelines. Other suitable clock layouts may

exist and it would be recommended that the board designers

simulate to guarantee compatibility across all printed circuit and clock

component process variations.

The differential outputs are low impedance follower outputs that

generate ECL/LVPECL compatible outputs. Therefore, terminating

resistors (DC current path to ground) or current sources must be

used for functionality. These outputs are designed to drive 50

3.3V

R3

R4

125

3.3V

Z

_o= 50

+

_

LVPECL

Input

_o= 50

R1

84

R2

84

Figure 5A. 3.3V LVPECL Output Termination

Figure 5B. 3.3V LVPECL Output Termination

IDT8V89704ANLGI REVISION A APRIL 3, 2013

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IDT8V89704I Data Sheet

FEMTOCLOCK^®NG CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR

Termination for 2.5V LVPECL Outputs

Figure 6A and Figure 6B show examples of termination for 2.5V

LVPECL driver. These terminations are equivalent to terminating 50

to V_CCO– 2V. For V_CCO= 2.5V, the V_CCO– 2V is very close to ground

level. The R3 in Figure 6B can be eliminated and the termination is

shown in Figure 6C.

2.5V

V_CCO= 2.5V

2.5V

V_CCO= 2.5V

R1

R3

50

250

+

50

+

–

50

–

2.5V LVPECL Driver

R1

50

R2

50

2.5V LVPECL Driver

R2

62.5

R4

62.5

R3

18

Figure 6A. 2.5V LVPECL Driver Termination Example

Figure 6B. 2.5V LVPECL Driver Termination Example

2.5V

V_CCO= 2.5V

50

+

50

–

2.5V LVPECL Driver

R1

50

R2

50

Figure 6C. 2.5V LVPECL Driver Termination Example

IDT8V89704ANLGI REVISION A APRIL 3, 2013

16

IDT8V89704I Data Sheet

FEMTOCLOCK^®NG CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR

VFQFN EPAD Thermal Release Path

In order to maximize both the removal of heat from the package and

the electrical performance, a land pattern must be incorporated on

the Printed Circuit Board (PCB) within the footprint of the package

corresponding to the exposed metal pad or exposed heat slug on the

package, as shown in Figure 7. The solderable area on the PCB, as

defined by the solder mask, should be at least the same size/shape

as the exposed pad/slug area on the package to maximize the

thermal/electrical performance. Sufficient clearance should be

designed on the PCB between the outer edges of the land pattern

and the inner edges of pad pattern for the leads to avoid any shorts.

and dependent upon the package power dissipation as well as

electrical conductivity requirements. Thus, thermal and electrical

analysis and/or testing are recommended to determine the minimum

number needed. Maximum thermal and electrical performance is

achieved when an array of vias is incorporated in the land pattern. It

is recommended to use as many vias connected to ground as

possible. It is also recommended that the via diameter should be 12

to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is

desirable to avoid any solder wicking inside the via during the

soldering process which may result in voids in solder between the

exposed pad/slug and the thermal land. Precautions should be taken

to eliminate any solder voids between the exposed heat slug and the

land pattern. Note: These recommendations are to be used as a

guideline only. For further information, please refer to the Application

Note on the Surface Mount Assembly of Amkor’s Thermally/

Electrically Enhance Leadframe Base Package, Amkor Technology.

While the land pattern on the PCB provides a means of heat transfer

and electrical grounding from the package to the board through a

solder joint, thermal vias are necessary to effectively conduct from

the surface of the PCB to the ground plane(s). The land pattern must

be connected to ground through these vias. The vias act as “heat

pipes”. The number of vias (i.e. “heat pipes”) are application specific

SOLDER

EXPOSED HEAT SLUG

PIN PAD

GROUND PLANE

LAND PATTERN

(GROUND PAD)

PIN PAD

THERMAL VIA

Figure 7. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)

IDT8V89704ANLGI REVISION A APRIL 3, 2013

17

IDT8V89704I Data Sheet

FEMTOCLOCK^®NG CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR

Schematic Example

Figure 8 (next page) is an IDT8V89704I application example

schematic. schematic focuses on functional connections and is not

configuration specific. Refer to the pin description and functional

tables in the datasheet to ensure that the logic control inputs are

properly set.

The schematic indicates components that are to be placed close to

the IDT8V89704I. Specifically the 0.1uF V_CC, V_CCAand V_CCO

bypass capacitors, the 180 ohm Q3, nQ3 LVPECL bias resistors R11

and R12 and the REF_OUT LVCMOS source termination resistor R1.

Similarly the 25MHz crystal and its associated load capacitors should

also be close to the device.

In this example the device is operated at V_CC= V_CCA= V_CCO= 3.3V

rather than 2.5V. The CLK, nCLK inputs are provided by a 3.3V

LVPECL driver and depicted with a Y-termination rather than the

standard four resistor V_CC- 2V Thevinin termination for reasons of

minimum termination power and layout simplicity. Three examples of

LVPECL terminations are shown for the outputs to demonstrate

mixing of PECL termination design options. For further options and a

more detailed discussion of LVPECL terminations, consult the IDT

application note “Termination – LVPECL”.

In order to achieve the best possible filtering, it is recommended that

the placement of the filter components be on the device side of the

PCB as close to the power pins as possible. The 0.1uF capacitors in

each power pin filter must be placed on the device side. If space is

limited, the other components can be on the opposite side of the

PCB. Power supply filter recommendations are a general guideline to

be used for reducing external noise from coupling into the devices.

The V_CCand V_CCOfilters start to attenuate noise at approximately

10kHz. If a specific frequency noise component is known, such as

switching power supplies frequencies, it is recommended that

component values be adjusted and if required, additional filtering be

added. Additionally, good general design practices for power plane

voltage stability suggests adding bulk capacitance in the local area of

all devices.

As with any high speed analog circuitry, the power supply pins are

vulnerable to random noise. To achieve optimum jitter performance,

power supply isolation is required. The IDT8V89704i provides

separate power supply pins to isolate any high switching noise from

coupling into the internal PLL.

IDT8V89704ANLGI REVISION A APRIL 3, 2013

18

IDT8V89704I Data Sheet

FEMTOCLOCK^®NG CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR

U1

17

R1

33

Z o = 50

F SE L1

F SE L0

32

FSE L1

FSE L0

REF _OUT

LVCMOS Receiver

14

3. 3 V

29

C LK _SEL

CLK _SE L

8

nc

RE SE RVED

25

R7

R8

26

13 3

133

Z o = 50 Ohm

9

XT A L _I N

+

25MHz(12pf )

10

2

3

Q0_P

Q0_N

XT A L _O U T

Q0

nQ0

X1

Z o = 50 Ohm

-

C18

9pF

C23

9pF

5

6

Q1_P

Q1_N

Q1

nQ1

R9

82.5

R10

82. 5

+3. 3V PE CL Rec eiv er

Zo = 50 Ohm

R3 50

R4 50

12

13

23

22

Q2_P

Q2_N

CLK

Q2

nQ2

nC L K

20

19

Q3_P

Q3_N

Q3

nQ3

PE CL Driver

R5

50

R11

180

R12

180

16

V CC_16

VCC

C15

0. 1uF

Zo = 50 Ohm

+

31

28

VCC_38

C10

VCC

1

7

11

15

18

24

27

30

V EE

-

0. 1uF

V CCA

VCC A

R13

50

R14

50

+3.3V P ECL Receiv er

C7

0. 1uF

V EE

4

21

VCC O

V CCO

33

R15

50

ePAD

C17

C9

0. 1uF

0.1uF

2. 5V

3. 3V

FB 1

C11 Zo = 50 Ohm

0. 1u

1

2

V CC_16

IN

50

BLM18BB 221SN1

C14

C6

0.1uF

10uF

C12 Zo = 50 Ohm

0. 1u

50

IN

3. 3V

FB 2

Optional AC Term ination

for 2. 5V CML Receiver

1

2

VCC_38

CML Receiv er

BLM18BB 221SN1

C16

C19

0.1uF

10uF

For o ther DC an d AC ter min ation option s co ns ult th e IDT A pplications No te

"Te rmination - LV PECL"

R16

10

Logic Control Input E xamples

V CCA

Set Logic

Input to '1'

Set Logic

Input to '0'

C8

10uF

V CC

VC C

3. 3V

RU1

1K

RU2

Not Inst al l

FB3

1

2

V CCO

To Logic

Input

pins

To Logic

Input

pins

B LM18B B221SN1

C21

10uF

C22

0.1uF

RD1

RD2

1K

Not Install

Figure 8. IDT8V89704I Schematic Layout

IDT8V89704ANLGI REVISION A APRIL 3, 2013

19

IDT8V89704I Data Sheet

FEMTOCLOCK^®NG CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR

Power Considerations

This section provides information on power dissipation and junction temperature for the IDT8V89704I.

Equations and example calculations are also provided.

1. Power Dissipation.

The total power dissipation for the IDT8V89704I is the sum of the core power plus the power dissipated due to the load.

The following is the power dissipation for V_CC= 3.3V + 5% = 3.465V, which gives worst case results.

NOTE: Please refer to Section 3 for details on calculating power dissipated due to the load.

•

Power (core)_MAX= V_{CC_ MAX}* I_{EE_MAX}= 3.465V * 204mA = 706.86mW

Power (LVPECL outputs)_MAX= 31.55mW/Loaded Output pair

Power (LVPECL output) = 4 * 31.55mW = 126.2mW

LVCMOS Output

•

Output Impedance R_OUTPower Dissipation due to Loading 50 to V_CCO/2

Output Current I_OUT= V_{CCO_MAX}/ [2 * (50 + R_OUT)] = 3.465V / [2 * (50 + 20)] = 24.75mA

•

Power Dissipation on the R_OUTper LVCMOS output

Power (R_OUT) = R_OUT* (I_OUT)²= 20 * (24.75mA)²= 12.251mW

Dynamic Power Dissipation at 25MHz

Power (25MHz) = C_PD* Frequency * (V_CCO)²= 10pF * 25MHz * (3.465V)²= 3mW

•

Total Power Dissipation

•

Total Power

= Power (core) + Power (LVPECL) + Power (R_OUT) + Power (25MHz)

= 706.86mW + 126.2mW + 12.251mW + 3mW = 848.31mW

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The

maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond

wire and bond pad temperature remains below 125°C.

The equation for Tj is as follows: Tj = _JA* Pd_total + T_A

Tj = Junction Temperature

_JA= Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

T_A= Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance _JAmust be used. Assuming no air flow and

a multi-layer board, the appropriate value is 65.7°C/W per Table 7 below.

Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:

85°C + 848W * 33.1°C/W = 113.1.°C. This is below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of

board (multi-layer).

Table 7. Thermal Resistance _JAfor 32 Lead VFQFN, Forced Convection

_JAby Velocity

Meters per Second

0

1

3

Multi-Layer PCB, JEDEC Standard Test Boards

33.1°C/W

28.1°C/W

25.4°C/W

IDT8V89704ANLGI REVISION A APRIL 3, 2013

20

IDT8V89704I Data Sheet

FEMTOCLOCK^®NG CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR

3. Calculations and Equations.

The purpose of this section is to calculate the power dissipation for the LVPECL output pair.

LVPECL output driver circuit and termination are shown in Figure 8.

V_CCO

Q1

V_OUT

RL

50Ω

V_CCO- 2V

Figure 9. LVPECL Driver Circuit and Termination

To calculate power dissipation due to the load, use the following equations which assume a 50 load, and a termination voltage of V_CC– 2V.

•

For logic high, V_OUT= V_{OH_MAX}= V_{CCO_MAX}– 0.75V

(V_{CCO_MAX}– V_{OH_MAX}) = 0.75V

For logic low, V_OUT= V_{OL_MAX}= V_{CCO_MAX}– 1.6V

(V_{CCO_MAX}– V_{OL_MAX}) = 1.6V

Pd_H is power dissipation when the output drives high.

Pd_L is the power dissipation when the output drives low.

Pd_H = [(V_{OH_MAX}– (V_{CCO_MAX}– 2V))/R_L] * (V_{CCO_MAX}– V_{OH_MAX}) = [(2V – (V_{CCO_MAX}– V_{OH_MAX}))/R_L] * (V_{CCO_MAX}– V_{OH_MAX}) =

[(2V – 0.75V)/50] * 0.75V = 18.75mW

Pd_L = [(V_{OL_MAX}– (V_{CCO_MAX}– 2V))/R_L] * (V_{CCO_MAX}– V_{OL_MAX}) = [(2V – (V_{CCO_MAX}– V_{OL_MAX}))/R_L] * (V_{CCO_MAX}– V_{OL_MAX}) =

[(2V – 1.6V)/50] * 1.6V = 12.80mW

Total Power Dissipation per output pair = Pd_H + Pd_L = 31.55mW

IDT8V89704ANLGI REVISION A APRIL 3, 2013

21

IDT8V89704I Data Sheet

FEMTOCLOCK^®NG CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR

Reliability Information

Table 8. _JAvs. Air Flow Table for a 32 Lead VFQFN

_JAvs. Air Flow

Meters per Second

0

1

3

Multi-Layer PCB, JEDEC Standard Test Boards

33.1°C/W

28.1°C/W

25.4°C/W

Transistor Count

The transistor count for IDT8V89704I is: 26,859.

IDT8V89704ANLGI REVISION A APRIL 3, 2013

22

IDT8V89704I Data Sheet

FEMTOCLOCK^®NG CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR

32 Lead VFQFN Package Outline and Dimensions

IDT8V89704ANLGI REVISION A APRIL 3, 2013

23

IDT8V89704I Data Sheet

FEMTOCLOCK^®NG CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR

Ordering Information

Table 9. Ordering Information

Part/Order Number

8V89704ANLGI

8V89704ANLGI8

Marking

IDT8V89704ANLGI

Package

“Lead-Free” 32 Lead VFQFN

Shipping Packaging

Tray

Temperature

-40C to 85C

Tape & Reel

IDT8V89704ANLGI REVISION A APRIL 3, 2013

24

IDT8V89704I Data Sheet

FEMTOCLOCK^®NG CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR

We’ve Got Your Timing Solution

6024 Silver Creek Valley Road Sales

Technical Support

netcom@idt.com

800-345-7015 (inside USA)

+408-284-8200 (outside USA) +480-763-2056

Fax: 408-284-2775

San Jose, California 95138

www.IDT.com/go/contactIDT

DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document,

including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not

guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the

suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any

license under intellectual property rights of IDT or any third parties.

IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to signifi-

cantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.

Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third

party owners.


型号：	8V89704ANLGI
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	FemtoClock NG Crystal-to-3.3V, 2.5V LVPECL Clock Generator w/Fanout Buffer
文件：	总25页 (文件大小：315K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

8V89704ANLGI [IDT]

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