9112AG-16-T [IDT]
PLL Based Clock Driver, 9112 Series, 4 True Output(s), 0 Inverted Output(s), PDSO8, 4.40 MM, 0.65 MM PITCH, MO-153, TSSOP-8;
| 型号： | 9112AG-16-T |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PLL Based Clock Driver, 9112 Series, 4 True Output(s), 0 Inverted Output(s), PDSO8, 4.40 MM, 0.65 MM PITCH, MO-153, TSSOP-8 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总8页 (文件大小：119K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS9112A-16
Integrated
Circuit
Systems, Inc.
Low Skew Output Buffer
General Description
Features
The ICS9112A-16 is a high performance, low skew, low
jitter clock driver. It uses a phase lock loop (PLL)
technologytoalign, inbothphaseandfrequency, theREF
input with the CLKOUT signal. It is designed to distribute
high speed clocks in PC systems operating at speeds
from 25 to
•
•
•
Zero input - output delay
Frequency range 25 - 133 MHz (3.3V)
High loop filter bandwidth ideal for Spread
Spectrum applications.
•
•
•
•
Less than 200 ps Jitter between outputs
Skew controlled outputs
Skew less than 250 ps between outputs
Available in 8 pin 150 mil SOIC
or 173 mil TSSOP package.
3.3V 10ꢀ operation
133 MHz.
ICS9112A-16 is a zero delay buffer that provides
synchronization between the input and output. The
synchronization is established via CLKOUT feed back to
theinputofthePLL. Sincetheskewbetweentheinputand
outputislessthan+/-350pS, thepartactsasazerodelay
buffer.
•
The ICS9112A-16 comes in an eight pin 150 mil SOIC or
173 milTSSOP package. It has five output clocks. In the
absence of REF input, will be in the power down mode. In
this mode, the PLL is turned off and the output buffers are
pulled low. Power down mode provides the lowest power
consumption for a standby condition.
Block Diagram
Pin Configuration
8 pin SOIC,TSSOP
1337K—08/03/07
ICS9112A-16
Pin Descriptions
PIN NUMBER
PIN NAME
TYPE
IN
DESCRIPTION
1
2
3
4
5
6
7
8
REF2
CLK23
CLK13
GND
Input reference frequency.
Buffered clock output
Buffered clock output
Ground
OUT
OUT
PWR
OUT
PWR
OUT
OUT
CLK33
Buffered clock output
Power Supply (3.3V)
Buffered clock output
VDD
CLK43
CLKOUT3
Buffered clock output. Internal feedback on this pin
Notes:
1. Guaranteed by design and characterization. Not subject to 100ꢀ test.
2. Weakpull-down
3. Weak pull-down on all outputs
1337K—08/03/07
2
ICS9112A-16
Absolute Maximum Ratings
SupplyVoltage . . . . . . . . . . . . . . . . . . . . . . . 7.0 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient OperatingTemperature . . . . . . . . . . 0°C to +70°C
StorageTemperature. . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.These
ratingsarestressspecificationsonlyandfunctionaloperationofthedeviceattheseoranyotherconditionsabovethose
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics at 3.3V
VDD = 3.0 – 3.6V, TA = 0 –70°C unless otherwise stated
DC Characteristics
PARAMETER
Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
Output Low Voltage
SYMBOL
TEST CONDITIONS
MIN
2.0
TYP
MAX
0.8
UNITS
V
IL
V
V
V
IH
I
IL
V =0V
19
0.10
0.25
2.9
50.0
100.0
0.4
µA
µA
V
IN
I
IH
V =V
IN DD
1
V
OL
OH
DD
I
I
= 25mA
= 25mA
OL
1
V
Output High Voltage
2.4
V
OH
Power Down Supply
Current
I
I
REF = 0 MHz
0.3
50.0
40.0
µA
Unloaded oututs at 66.66 MHz
DD
Supply Current
30.0
mA
SEL inputs at V or GND
DD
Notes:
1. Guaranteed by design and characterization. Not subject to 100ꢀ test.
2. All Skew specifications are mesured with a 50Ω transmission line, load teminated with 50Ω to 1.4V.
3. Duty cycle measured at 1.4V.
4. Skew measured at 1.4V on rising edges. Loading must be equal on outputs.
1337K—08/03/07
3
ICS9112A-16
Switching Characteristics
PARAMETER
Output period
SYMBOL
t1
CONDITION
With CL=30pF
MIN
TYP
MAX
UNITS
40.00
(25)
7.5
(133)
ns
(MHz)
40.00
(25)
7.5
(133)
ns
(MHz)
Input period
Duty Cycle1
Duty Cycle1
t1
With CL=30pF
Dt1
Dt2
Measured at 1.4V; CL=30pF
40.0
45
50
50
60
55
ꢀ
ꢀ
Measured at VDD/2 Fout
<66.6MHz
Measured between 0.8V and 2.0V:
CL=30pF
Rise Time1
Fall Time1
Rise Time1
Fall Time1
tr1
tf1
tr1
tf1
1.2
1.2
1.5
1.5
ns
ns
ns
ns
Measured between 2.0V and 0.8V;
CL=30pF
Measured between 0.8V and 2.0V:
CL=5pF
1
1
Measured between 2.0V and 0.8V;
CL=5pF
Delay, REF Rising
Edge to CLKOUT
Rising Edge1, 2
Dr1
Measured at 1.4V
0
0
350
ps
Output to Output
Skew1
All outputs equally loaded,
CL=20pF
Tskew
Tdsk-Tdsk
Tcyc-Tcyc
tLOCK
250
700
200
1.0
ps
ps
ps
ms
ps
ps
Device to Device
Skew1
Measured at VDD/2 on the
CLKOUT pins of devices
Cycle to Cycle
Jitter1
Measured at 66.66 MHz, loaded
outputs
Stable power supply, valid clock
presented on REF pin
PLL Lock Time1
Jitter; Absolute
Jitter1
@ 10,000 cycles
CL=30pF
Tjabs
-100
70
14
100
30
@ 10,000 cycles
CL=30pF
Jitter; 1 - Sigma1
Tj1s
Notes:
1. Guaranteed by design and characterization. Not subject to 100ꢀ test.
2. REF input has a threshold voltage of 1.4V
3. All parameters expected with loaded outputs
1337K—08/03/07
4
ICS9112A-16
Output to Output Skew
The skew between CLKOUT and the CLK(1-4) outputs is not dynamically adjusted by the PLL.Since CLKOUT is one
of the inputs to the PLL, zero phase difference is maintained from REF to CLKOUT. If all outputs are equally loaded,
zero phase difference will maintained from REF to all outputs.
If applications requiring zero output-output skew, all the outputs must equally loaded.
If the CLK(1-4) outputs are less loaded than CLKOUT, CLK(1-4) outputs will lead it;and if the CLK(1-4) is more loaded
than CLKOUT, CLK(1-4) will lag the CLKOUT.
Since the CLKOUT and the CLK(1-4) outputs are identical, they all start at the same time, but different loads cause
them to have different rise times and different times crossing the measurement thresholds.
REF input and
all outputs
loadedEqually
REF input and CLK(1-4)
outputsloadedequally,with
CLKOUT loaded More.
REF input and CLK(1_4)
outputsloadedequally,with
CLKOUT loaded Less.
Timing diagrams with different loading configurations
1337K—08/03/07
5
ICS9112A-16
150 mil (Narrow Body) SOIC
In Millimeters
COMMON DIMENSIONS
In Inches
COMMON DIMENSIONS
C
N
SYMBOL
MIN
1.35
0.10
0.33
0.19
MAX
1.75
0.25
0.51
0.25
MIN
.0532
.0040
.013
MAX
.0688
.0098
.020
A
A1
B
C
D
E
e
L
INDEX
AREA
.0075
.0098
H
E
SEE VARIATIONS
3.80
SEE VARIATIONS
.1497 .1574
0.050 BASIC
4.00
1.27 BASIC
H
h
L
5.80
0.25
0.40
6.20
0.50
1.27
.2284
.010
.016
.2440
.020
.050
h x 45°
1
2
N
a
SEE VARIATIONS
SEE VARIATIONS
D
α
A
0°
8°
0°
8°
VARIATIONS
A1
D mm.
D (inch)
N
8
MIN
4.80
MAX
5.00
MIN
.1890
MAX
.1968
SEATING
PLANE
e
B
Reference Doc.: JEDEC Publication 95, MS-012
10-0030
.10 (.004)
150 mil (Narrow Body) SOIC
Ordering Information
ICS9112AM-16LF-T
Example:
ICS XXXX A M PPP LF-T
Designation for tape and reel packaging
Lead Option(optional)
LF = Lead Free, RoHS Compliant
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
M = SOIC
RevisionDesignator
Device Type
Prefix
ICS, AV = Standard Device
1337K—08/03/07
6
ICS9112A-16
In Millimeters
In Inches
SYMBOL
COMMON DIMENSIONS COMMON DIMENSIONS
c
N
MIN
--
MAX
1.20
0.15
1.05
0.30
0.20
MIN
--
MAX
.047
.006
.041
.012
.008
A
A1
A2
b
L
0.05
0.80
0.19
0.09
.002
.032
.007
.0035
E1
E
INDEX
AREA
c
D
E
SEE VARIATIONS
6.40 BASIC
SEE VARIATIONS
0.252 BASIC
E1
e
L
4.30
0.65 BASIC
0.45
4.50
.169
0.0256 BASIC
.018
.177
1
2
α
0.75
.030
D
N
SEE VARIATIONS
SEE VARIATIONS
α
aaa
0°
--
8°
0.10
0°
--
8°
.004
A
A2
VARIATIONS
D mm.
D (inch)
A1
N
MIN
2.90
MAX
3.10
MIN
.114
MAX
.122
- C -
8
e
SEATING
PLANE
Reference Doc.: JEDEC Publication 95, MO-153
b
10-0035
aaa
C
4.40 mm. Body, 0.65 mm. pitch TSSOP
(0.0256Inch)
(173 mil)
Ordering Information
9112AG-16LF-T
Example:
XXXX A G PPP LF-T
Designation for tape and reel packaging
Lead Option(optional)
LF = Lead Free, RoHS Compliant
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
G = TSSOP
RevisionDesignator
Device Type
1337K—08/03/07
7
ICS9112A-16
Revision History
Rev.
Issue Date Description
Page #
6-7
6-7
H
I
09/01/04 Updated Lead Free information
11/02/04 Added LN option
J
K
04/26/07 Removed LN option superceded by LF.
08/03/07 Updated Switching Characteristics Rise/Fall time.
6-7
4
1337K—08/03/07
8
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