91309MILF-T [IDT]
Clock Driver;
| 型号： | 91309MILF-T |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Driver |
| 文件： | 总9页 (文件大小：106K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS91309I
Integrated
Circuit
Systems,Inc.
High Performance Communication Buffer
General Description
Features
The ICS91309I is a high performance, low skew, low jitter
zero delay buffer. It uses a phase lock loop (PLL)
technologytoalign, inbothphaseandfrequency, theREF
input with the CLKOUT signal. It is designed to distribute
high speed clocks in communication systems operating
at speeds from 10 to 133 MHz.
•
•
•
•
Zero input - output delay
Frequency range 10 - 133 MHz (3.3V)
5V tolerant input REF
High loop filter bandwidth ideal for Spread Spectrum
applications.
Less than 125 ps cycle to cycle Jitter
Skew controlled outputs
Available in 16 pin, 150 mil SSOP, SOIC & 4.40mm
TSSOP packages
•
•
•
The ICS91309I provides synchronization between the
input and output. The synchronization is established via
CLKOUTfeedbacktotheinputofthePLL. Sincetheskew
between the input and output is less than +/- 350 pS, the
part acts as a zero delay buffer.
•
•
•
Skew:Group-to-Group:<215ps
Skew within Group: <100 ps
Industrial temperature range: -40°C to +85°C
ICS91309I has two banks of four outputs controlled by
two address lines. Depending on the selected address
line, bank B or both banks can be put in a tri-state mode.
In this mode, the PLL is still running and only the output
buffers are put in a high impedance mode. The test mode
shuts off the PLL and connects the input directly to the
output buffers (see table below for functionality).
Pin Configuration
REF
CLKA1
CLKA2
VDD
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CLKOUT
CLKA4
CLKA3
VDD
ICS91309I comes in a 16-pin 150 mil SOIC, SSOP or
4.40mm TSSOP package. In the absence of REF input,
thedevicewillenterapowerdownmode. Inthismode, the
PLL is turned off and the output buffers are pulled low.
Powerdownmodeprovidesthelowestpowerconsumption
for a standby condition.
GND
GND
CLKB1
CLKB2
FS2
CLKB4
CLKB3
FS1
16 pin SSOP, SOIC & TSSOP
Block Diagram
Functionality
Ouput
Source Shutdown
PLL
FS2 FS1 CLKA(1:4) CLKB(1:4) CLKOUT
0
0
0
1
Tristate
Driven
PLL
Tristate
Tristate
PLL
Driven
Driven
PLL
PLL
PLL
N
N
1
1
0
1
Bypass
Mode
Driven
Bypass
Mode
Driven
Bypass
Mode
Driven
REF
PLL
Y
N
0770B—02/02/04
ICS91309I
Pin Descriptions
PIN # PIN NAME
PIN TYPE DESCRIPTION
REF1
1
IN
Input reference frequency, 5V tolerant input
CLKA12
2
OUT
OUT
PWR
PWR
OUT
OUT
IN
Buffered clock output, Bank A
Buffered clock output, Bank A
Power Supply
CLKA22
VDD
3
4
5
GND
Ground
CLKB12
CLKB22
FS23
6
Buffered clock output, Bank B
Buffered clock output, Bank B
Function select input, bit 2
Function select input, bit 1
Buffered clock output, Bank B
Buffered clock output, Bank B
Ground
7
8
FS13
CLKB32
CLKB42
9
IN
10
11
OUT
OUT
PWR
PWR
OUT
OUT
OUT
12 GND
13 VDD
14
Power Supply
CLKA32
Buffered clock output, Bank A
Buffered clock output, Bank A
Buffered clock output, internal feedback
CLKA42
15
16
CLKOUT2
Notes:
1. Weak pull-down
2. Weak pull-down on all outputs
3. Weak pull-ups on these inputs
0770B—02/02/04
2
ICS91309I
Absolute Maximum Ratings
SupplyVoltage . . . . . . . . . . . . . . . . . . . . . . . 7.0 V
Logic Inputs (Except REF) . . . . . . . . . . . . . . GND –0.5 V to VDD + 0.5 V
Logic Input REF . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to GND + 5.5 V
Ambient OperatingTemperature . . . . . . . . . . -40°C to +85°C
StorageTemperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.These
ratingsarestressspecificationsonlyandfunctionaloperationofthedeviceattheseoranyotherconditionsabovethose
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input & Supply
TA = -40 - 85°C; Supply Voltage VDD = 3.3 V +/-10%
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Output High Voltage
Output Low Voltage
Operating Supply
Current
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX
UNITS
V
V
VIL
0.8
250
100
IIH
VIN = VDD
0.1
19
uA
uA
V
IIL
VIN = 0 V
VoH
VoL
IoH = -12 mA
IoL = 12 mA
2.4
10
0.4
45
V
IDD
mA
Outputs Unloaded; REF = 66 MHz
REF = 0 Mhz
30
IDD
Fi
CIN
Powerdown Current
Input Frequency
Input Capacitance1
uA
MHz
pF
0.3
50
133
5
Notes:
1. Guaranteed by design and characterization, not 100% tested in production.
0770B—02/02/04
3
ICS91309I
Electrical Characteristics - Outputs
TA = -40 - 85°C; VDD = 3.3 V +/-10%; CL = 30 pF (unless otherwise specified)
PARAMETER
Output High Voltage
SYMBOL
VOH
CONDITIONS
MIN
2.4
TYP
MAX
UNITS
V
IOH = -12 mA
IOL = 12 mA
VOL
Output Low Voltage
0.4
2
V
Rise Time1
Fall Time1
tr
Measure between 0.8 V and 2.0 V
Measure between 2.0 V and 0.8 V
Stable VDD, valid clock on REF
CL = 30 pF
1.2
1.2
ns
tf
2
ns
PLL Lock Time1
TLOCK
f1
1
mS
MHz
MHz
%
10
10
40
45
100
133
60
Output Frequency
f1
Dt1
Dt2
CL = 10 pF
Measured at 1.4 V, Fout = 66.7 MHz
Measured at VDD/2, Fout < 50.0 MHz
50
50
Duty Cycle1
55
%
Jitter, Cycle-to-cycle1
Jitter, Absolute1
tjcyc-cyc
Tjabs
Tj1s
Tsk
Measured at 66.7 MHz, loaded outputs
10,000 cycles, CL = 30 pF
10,000 cycles, CL = 30 pF
Measured at 1.4 V
125
100
30
ps
-100
70
14
ps
Jitter, 1-Sigma1
ps
Skew, Group-to-Group1
Skew, Output-to-Output1
Skew, Device-to-Device1
Delay, Input-to-Output1
215
100
700
700
ps
Tsk
Measured at 1.4 V, within a group
Measured at VDD/2,on CLKOUT pins
Measured at 1.4 V
ps
Tdsk-Tdsk
Dr1
ps
ps
Notes:
1. Guaranteed by design and characterization, not 100% tested in production.
0770B—02/02/04
4
ICS91309I
Output to Output Skew
The skew between CLKOUT and the CLKA/B outputs is not dynamically adjusted by the PLL.Since CLKOUT is one
of the inputs to the PLL, zero phase difference is maintained from REF to CLKOUT. If all outputs are equally loaded,
zero phase difference will maintained from REF to all outputs.
If applications requiring zero output-output skew, all the outputs must equally loaded.
If the CLKA/B outputs are less loaded than CLKOUT, CLKA/B outputs will lead it; and if the CLKA/B is more loaded
than CLKOUT, CLKA/B will lag the CLKOUT.
SincetheCLKOUTandtheCLKA/Boutputsareidentical, theyallstartatthesametime, butdifferentloadscausethem
to have different rise times and different times crossing the measurement thresholds.
REF input and
all outputs
loadedEqually
REF input and CLKA/B
outputsloadedequally,with
CLKOUT loaded More.
REF input and CLKA/B
outputsloadedequally,with
CLKOUT loaded Less.
Timing diagrams with different loading configurations
0770B—02/02/04
5
ICS91309I
Application Suggestion:
ICS91309I is a mixed analog/digital product. The analog portion of the PLL is very sensitive to any random noise
generated by charging or discharging of internal or external capacitor on the power supply pins. This type of noise will
cause excess jitter to the outputs of ICS91309I. Below is a recommended lay out to alleviate any addition noise. For
additional information on FT.layout, please refer to our AN07.The 0.1 uF capacitors should be connected as close as
possible to power pins (4 & 13). An Isolated power plane with a 2.2 uF capacitor to ground will enhance the power line
stability.
33Ω
1 REF
CLKOUT 16
CLKA4 15
CLKA3 14
VDD 13
33Ω
33Ω
33Ω
33Ω
2 CLKA1
3 CLKA2
4 VDD
0.1µF
0.1µF
5 GND
GND 12
33Ω
33Ω
33Ω
33Ω
6 CLKB1
7 CLKB2
8 FS2
CLKB4 11
CLKB3 10
FS1
9
10KΩ
10KΩ
GND
VDD
GND
VDD
0770B—02/02/04
6
ICS91309I
SYMBOL
In Millimeters
In Inches
COMMON DIMENSIONS
COMMON DIMENSIONS
MIN
1.35
0.1
MAX
1.75
0.25
1.50
0.30
0.25
MIN
.053
.0040
—
MAX
.069
.010
.059
.012
.010
A
A1
A2
b
—
0.20
0.18
.008
.007
c
SEEVARIATIONS
SEEVARIATIONS
D
E
5.80
3.80
6.20
4.00
.228
.150
.244
.157
E1
e
0.635 BASIC
0.025 BASIC
L
0.40
1.27
.016
.050
SEEVARIATIONS
SEEVARIATIONS
N
0°
8°
0°
8°
α
SEEVARIATIONS
SEEVARIATIONS
ZD
VARIATIONS
D mm.
MIN
4.80
ZD
(Ref)
0.23
D (inch)
ZD
(Ref)
N
MAX
5.00
MIN
MAX
16
.189
.197
.009
6/1/00
REV B
JEDEC MO-137
DOC# 10-0032
Ordering Information
ICS91309yFILF-T
Example:
ICS XXXX y F LF- T
Designation for tape and reel packaging
Lead Free (Optional)
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
0770B—02/02/04
7
ICS91309I
SYMBOL
In Millimeters
In Inches
C
COMMON DIMENSIONS
COMMON DIMENSIONS
N
MIN
1.35
0.10
0.33
0.19
MAX
1.75
0.25
0.51
0.25
MIN
.0532
.0040
.013
MAX
.0688
.0098
.020
A
A1
B
C
D
E
e
L
INDEX
AREA
H
E
.0075
.0098
SEE VARIATIONS
SEE VARIATIONS
3.80
4.0
.1497
.1574
1.27 BASIC
0.050 BASIC
H
h
5.80
0.25
0.40
6.20
0.50
1.27
.2284
.010
.016
.2440
.020
.050
h xx 4455°°
1
2
D
α
A
L
SEE VARIATIONS
SEE VARIATIONS
N
α
A1
0°
8°
0°
8°
SEATING
PLANE
e
VARIATIONS
B
D mm.
D (inch)
.10 ((..000044))
N
MIN
9.80
MAX
MIN
MAX
16
10.00
.3859
.3937
150 mil (Narrow Body) SOIC
Ordering Information
ICS91309yMILF-T
Example:
ICS XXXX y M LF- T
Designation for tape and reel packaging
Lead Free (Optional)
Package Type
M = SOIC
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
0770B—02/02/04
8
ICS91309I
4.40 mm. Body, 0.65 mm. Pitch TSSOP
(173 mil)
In Millimeters
(25.6 mil)
c
N
In Inches
SYMBOL
COMMON DIMENSIONS COMMON DIMENSIONS
L
MIN
--
0.05
0.80
0.19
0.09
MAX
1.20
0.15
1.05
0.30
0.20
MIN
--
.002
.032
.007
.0035
MAX
.047
.006
.041
.012
.008
A
A1
A2
b
E1
E
INDEX
AREA
c
D
E
E1
e
SEE VARIATIONS
6.40 BASIC
SEE VARIATIONS
0.252 BASIC
1
22
α
4.30
4.50
.169
.177
D
0.65 BASIC
0.0256 BASIC
L
0.45
0.75
.018
.030
N
SEE VARIATIONS
SEE VARIATIONS
A
α
aaa
0°
--
8°
0.10
0°
--
8°
.004
A2
A1
- C -
VARIATIONS
D mm.
D (inch)
e
SEATING
PLANE
N
b
MIN
4.90
MAX
5.10
MIN
.193
MAX
.201
16
aaa
C
Reference Doc.: JEDEC Publication 95, MO-153
10-0035
Ordering Information
ICS91309yGILF-T
Example:
ICS XXXX y G LF- T
Designation for tape and reel packaging
Lead Free (Optional)
Package Type
G = TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
0770B—02/02/04
9
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