9176Q-01 [IDT]
PLL Based Clock Driver, PQCC28, PLASTIC, LCC-28;
| 型号： | 9176Q-01 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PLL Based Clock Driver, PQCC28, PLASTIC, LCC-28 驱动 逻辑集成电路 |
| 文件： | 总8页 (文件大小：379K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS9176-01
Integrated
Circuit
Systems, Inc.
Low Skew Output Buffer
General Description
Features
•
•
•
•
•
ICS9176-01-01 is pin compatible with Triquint GA1086
±500ps skew (max) between input and outputs
±250ps skew (max) between outputs
10 symmetric, TLL-compatible outputs
28-pin PLCC or 28-pin wide SOIC surface mount
package
the ICS9176-01 is designed specifically to support the tight
timing requirements of high-performance microprocessors
and chip sets. Because the jitter of the device is limited to
±250ps, the ICS9176-01 is ideal for clocking Pentium™
systems. The 10 high drive (40mA), low-skew (±250ps)
outputs make the ICS9176-01 a perfect fit for PCI clocking
requirements.
•
•
•
•
•
High drive, 40mA outputs
Power-down option
Output frequency range 20 MHz to 120 MHz
Input frequency range 20 MHz to 100 MHz
Ideal for PCI bus applications
The ICS9176-01 has 10 outputs synchronized in phase and
fre-quency to an input clock. The internal phase locked loop
(PLL) acts either as a 1X clock multiplier or a 1/2X clock
multiplier depending on the state of the input control pins T0
and T1. With metal mask options, any type of ratio between
the input clock and output clock can be achieved, including
2X.
Functionality
The PLL maintains the phase and frequency relationship be-
tween the input clock and the outputs by externally feeding
back FBOUT to FBIN. Any change in the input will be tracked
by all 10 outputs. However, the change at the outputs will
happen smoothly so no glitches will be present on any driven
input. The PLL circuitry matches rising edges of the input
clock and the output clock. Since the input to FBIN skew is
guaran-teed to ±500ps, the part acts as a “zero delay” buffer.
FS1
0
FS0
0
DESCRIPTION
Power-down
0
1
Test Mode (PLL Off CLK=outputs)
Normal (PLL On)
1
0
1
1
Divide by 2 Mode
The ICS9176-01 has a total of eleven outputs. Of these,
FBOUT is dedicated as the feedback into the PLL and another,
Q/2, has an output frequency half that of the remaining nine.
These nine outputs can either be running at the same speed as
the input, or at half the frequency of the input. With Q/2 as the
feedback to FBIN, the nine ‘Q’ outputs will be running at twice
the input frequency in the normal divide-by-1 mode. In this
case, the output can go to 120 MHz with a 60 MHz input clock.
The maximum rise and fall time of an output is 1ns and each is
TTL-compatible with a 40mA symmetric drive.
Block Diagram
TheICS9176-01is fabricated using CMOS technology which
results in much lower power consumption and cost compared
with the gallium arsenide based 1086E. The typical operating
current for the ICS9176-01 is 60mA versus 115mA for the
GA1086E.
Pentium is a trademark of Intel Corporation.
ICS9176-01-01RevB061297P
ICS reserves the right to make changes in the device data identified in this publication
without further notice. ICS advises its customers to obtain the latest version of all
device data to verify that any information being relied upon by the customer is current
and accurate.
ICS9176-01
Pin Configuration
28-Pin PLCC
28-Pin SOIC
Pin Description
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
1
2
GND
-
GROUND.
Q8
Output
Output clock 8
Output clock 9.
Power supply (+5V).
GROUND.
3
Q9
Output
4
VDD
GND
NC
-
5
-
6
-
No Connect.
7
NC
-
No Connect.
8
VDD
CLK
FS1
FBIN
FS0
VDD
Q/2
-
Power supply (+5V).
Input for reference clock.
9
Input
Input
Input
Input
-
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
FS1 selects normal operation, power-down, or test mode.
FEEDBACK INPUT from output FBOUT.
FS0 selects normal operation, power-down, or test mode.
Power Supply (+5V).
Half-clock output.
Output
-
GND
FBOUT
Q1
GROUND.
Output
Output
-
FEEDBACK OUTPUT to Input FBIN.
Output clock 1.
VDD
GND
Q2
Power Supply (+5V).
GROUND.
-
Output
Output
-
Output clock 2.
Q3
Output clock 3.
VDD
Q4
Power supply (+5V).
Output
Output
-
Output clock 4.
Q5
Output clock 5.
GND
VDD
Q6
GROUND.
-
Power Supply (+5V).
Output clock 6.
Output
Output
Q7
Output clock 7.
2
ICS9176-01
Timing Diagrams
Timing in Divide by 1 Mode
Timing in Divide by 2 Mode
Timing in Eliminate by Test Mode
Note: In test mode, the VCOs are bypassed. The test clock input is simply buffered, then output. The part is transparent. Damage
to the device may occur if an output is shorted or forced to ground or VDD.
Timing in Power-down Mode
3
ICS9176-01
Absolute Maximum Ratings
VDD referenced to GND . . . . . . . . . . . . . . . . . . . . . . 7V
Operating temperature under bias. . . . . . . . . . . . . . . . 0°C to +70°C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
Voltage on I/O pins referenced to GND. . . . . . . . . . . GND -0.5V to VDD +0.5V
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 Watts
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections
of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product
reliability.
Electrical Characteristics
DC Characteristics
VDD =+5V±5%, TA=0°C to 70°C unless otherwise stated
PARAMETER
Input Low Voltage
Input High Voltage
Input Current
SYMBOL
VIL
TEST CONDITIONS
VDD=5V
MIN
-
TYP
MAX
UNITS
V
-
-
0.8
-
VIH
VDD=5V
2.0
-5
-
V
Ii
VIN=0V, 5V
@IOL=14mA
@VOL=0.8V
@IOH=-38mA
@VOH=2.0V
-
5
µA
V
Output Low Voltage
Output Low Current
Output High Voltage
Output High Current
VOL
IOL
0.25
42
-
0.4
-
33
2.4
-
mA
V
1
1
VOH
IOH
-
-59
-41
mA
Supply Current, Normal
Mode
Unloaded outputs,
@ 66.6 Mhz
IDD
-
-
55
75
mA
mA
Supply Current, Power-
down Mode
IDD-PD
T1, T0=0, 0
2.0
10.0
Note:
1. Guaranteed by design and characterization. Not subject to 100% test.
4
ICS9176-01
AC Characteristics
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
2.5
TYP
-
MAX
7.5
UNITS
ns
1
Input Clock Pulse Width
CLKW
VDD=4.5V, fCLK=100 MHz
Output Rise time, 0.8 to
2.0V 1
tr
15pF load
15pF load
15pF load
-
-
-
-
0.7
1.5
0.7
1.2
1
2
1
2
ns
ns
ns
ns
Rise time, 20% to 80%
tr
tf
tf
1
VDD
Output Fall time, 2.0V to
0.8V 1
Fall time, 80% to 20%
15pF load
1
VDD
1
Output Duty cycle
dt
Tls
Tabs
fi
15pF load, Note 3
45
-
49/51
60
55
-
%
ps
1
Jitter, 1 sigma
Jitter, absolute 1
-250
20
±100
-
250
100
ps
Input Frequency
MHz
Output Frequency
(Q outputs)
For outputs >100 MHz, use
Q/2 as feedback
fo
20
-500
-250
-3
-
120
0
MHz
ps
Note 2, 4. Input rise time <
3ns
FBIN to IN skew 1
tskew1
tskew2
tskew3
250
50
Skew between any 2 out-
puts at same frequency
Note 2, 4.
Note 2, 4
250
3
ps
1
Skew between any 1 out
±0.1
ns
1
put and Q/2
Notes:
1. Guaranteed by design and characterization. Not subject ot 100% test.
2. All skew specifications are measured with a 50W transmission line, load terminated with 50W to 1.4V.
3. Duty cycle measured at 1.4V.
4. Skew measured at 1.4V on rising edges. Loading must be equal on outputs.
5
ICS9176-01
Applications
FBOUT is normally connected to FBIN to facilitate input to
output skew control. However, there is no requirement that
the external feedback connection be a direct hardwire from an
output pin to the FBIN pin. As long as the signal at FBIN is
derived directly from the FBOUT pin and maintains its fre-
quency, additional delays can be accommodated. The clock
phase of the outputs (rising edge) will be adjusted so that the
phase of FBIN and the input clock will be the same. See Figure
1 for an example.
The ICS9176-01 is also ideal for clocking multi-processor
sys-tems. The 10 outputs can be used to synchronize the
operation of CPU cache and memory banks operating at
different speeds. Figure 2 depicts a 2-CPU system in which
processors and associated peripherals are operating at 66
MHz. Each of the nine outputs operating at 66 MHz are fully
utilizedtodrivetheappropriateCPU, cacheandmemorycontrol
logic. The 33 MHz output is used to synchronize the operation
of the slower memory bank to the restart of the system.
Figure 1
In Figure 1, the propagation delay through the divide by 2
circuit is eliminated. The internal phase-locked loop will
adjust the output clock on the ICS9176-01 to ensure zero
phase delay between the FBIN and CLK signals, as a result,
the rising edge at the output of the divide by two circuit will be
aligned with the rising edge of the 66 MHz input clock. This
type of configuration can be used to eliminate propagation
delay as long as the signal at FBIN is continuous and is not
gated or conditional.
Figure 2
6
ICS9176-01
PLCC Package
FRAME
THICKNESS
TF
PKG.
THICKNESS
TP
PKG. WIDTH
TOP
PKG. WIDTH
BOTTOM
WB
OVERALL
PKG. WIDTH
WO
CONTACT
WIDTH
WO
LEAD COUNT
28L
WT
±.004
±.0003
±.004
±.006
±.005
+.010/-.030
0.010
0.152
0.450
0.453
0.490
0.420
Ordering Information
ICS9176Q-01
Example:
ICS XXXX- M PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
Q=PLCC
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV=Standard Device
7
ICS9176-01
LEAD COUNT
DIMENSION L
28L
0.704
SOIC Package
Ordering Information
ICS9176M-01
Example:
ICS XXXX- M PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
M=SOIC
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV=Standard Device
ICS reserves the right to make changes in the device data identified in this publication
without further notice. ICS advises its customers to obtain the latest version of all
device data to verify that any information being relied upon by the customer is current
and accurate.
8
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