92HD89D1X5NDGXYYX8_技术文档

DATASHEET

EIGHT CHANNEL HD AUDIO CODEC

92HD89D

Low Power Optimized for ECR15b and EuP

Description

The 92HD89D is a low power optimized, high fidelity,

8-channel audio codec compatible with Intel’s High

Definition (HD) Audio Interface.

Features

•

8 Channels (4 stereo DACs and 2 stereo ADCs) with

24-bit resolution

•

Supports full-duplex 5.1 audio and simultaneous VoIP

•

ECR 15b and EuP low power support

The 92HD89D provides stereo 24-bit resolution with

sample rates up to 192kHz.

Microsoft WLP premium logo compliant, per Logo

Point

The 92HD89D provides high quality, HD Audio capability to

notebook and desktop PC applications

•

8 analog ports with port presence detect + CD In

3 integrated headphone amps

4 adjustable VREF Out pins for microphone bias

Dual SPDIF for WLP compliant support of

simultaneous HDMI and SPDIF output

•

SPDIF Input

Digital microphone input (mono or stereo or quad)

High performance analog mixer

Support for 1.5V and 3.3V HDA signaling

Digital and Analog PC Beep to all outputs

48-pin QFP and 40-pad QFN RoHS packages

Block Diagram

Port A

Port B

Port C

Port D

Port E

Port F

Port G

Port H

SPDIF IN

SPDIF Out 1

SPDIF

SPDIF Out 2

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Eight channel HD Audio codec optimized for low power

Software Support

•

Intuitive IDT HD Sound graphical user interface that allows configurability and preference set-

tings

•

12 band fully parametric equalizer

•

Constant, system-level effects tuned to optimize a particular platform can be combined with

user-mode “presets” tailored for specific acoustical environments and applications

System-level effects automatically disabled when external audio connections made

•

Dynamics Processing

•

Enables improved voice articulation

Compressor/limiter allows higher average volume level without resonances or damage to

speakers.

IDT Vista APO wrapper

Enables multiple APOs to be used with the IDT Driver

•

Microphone Beam Forming, Acoustic Echo Cancellation, and Noise Suppression

Dynamic Stream Switching

•

Improved multi-streaming user experience with less support calls

rd

•

Broad 3 party branded software including Creative, Dolby, DTS, and SRS

Smart Configuration Suite (SCS) improves time to market and software quality

•

Online pin and feature configuration tool generates BIOS verb table for Windows and Linux.

Downloadable WHQL compliant, self configurable driver for XP, Vista and Win7 based on

verb table and test files generated.

•

BIOS verb tables can be tested with the self configurable driver prior to flashing into BIOS.

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Eight channel HD Audio codec optimized for low power

TABLE OF CONTENTS

1. DESCRIPTION ........................................................................................................................ 12

1.1. Overview ..........................................................................................................................................12

1.2. Orderable Part Numbers ..................................................................................................................12

1.3. Block Diagram .................................................................................................................................13

2. DETAILED DESCRIPTION ..................................................................................................... 14

2.1. Port Functionality .............................................................................................................................14

2.1.1. Port Characteristics ............................................................................................................15

2.1.2. Vref_Out .............................................................................................................................16

2.1.3. Jack Detect ........................................................................................................................16

2.1.4. SPDIF Output .....................................................................................................................16

2.2. SPDIF Input .....................................................................................................................................18

2.3. Analog Mixer ....................................................................................................................................19

2.4. Input Multiplexers .............................................................................................................................20

2.5. ADC Multiplexers .............................................................................................................................20

2.6. Power Management .........................................................................................................................20

2.7. AFG D0 ............................................................................................................................................21

2.8. AFG D1 ............................................................................................................................................21

2.9. AFG D2 ............................................................................................................................................22

2.10. AFG D3 ..........................................................................................................................................22

2.10.1. AFG D3cold .....................................................................................................................22

2.11. Vendor Specific Function Group Power States D4/D5 ..................................................................22

2.12. Low-voltage HDA Signaling ...........................................................................................................23

2.13. Multi-channel capture ....................................................................................................................23

2.14. Digital Microphone Support ...........................................................................................................25

2.15. Analog PC-Beep ............................................................................................................................30

2.16. Digital PC-Beep .............................................................................................................................32

2.17. Headphone Drivers ........................................................................................................................32

2.18. EAPD .............................................................................................................................................33

2.19. GPIO ..............................................................................................................................................35

2.19.1. GPIO Pin mapping and shared functions .........................................................................35

2.19.2. SPDIF/GPIO Selection .....................................................................................................35

2.19.3. Digital Microphone/GPIO Selection .................................................................................36

2.19.4. Vref_Out/GPIO Selection .................................................................................................36

2.19.5. EAPD/SPDIF_IN/SPDIF_OUT/GPIO0 Selection .............................................................36

2.20. HD Audio ECR 15b support ...........................................................................................................36

2.21. Digital Core Voltage Regulator ......................................................................................................36

3. CHARACTERISTICS ............................................................................................................... 38

3.1. Electrical Specifications ...................................................................................................................38

3.1.1. Absolute Maximum Ratings ...............................................................................................38

3.1.2. Recommended Operating Conditions ................................................................................38

3.2. 92HD89D Analog Performance Characteristics ...............................................................................39

3.3. AC Timing Specs .............................................................................................................................43

3.3.1. HD Audio Bus Timing .........................................................................................................43

3.3.2. SPDIF Timing .....................................................................................................................43

3.3.3. Digital Microphone Timing .................................................................................................44

3.3.4. GPIO Characteristics .........................................................................................................44

4. FUNCTIONAL BLOCK DIAGRAMS ....................................................................................... 45

4.1. 48QFP .............................................................................................................................................45

4.2. 40QFN .............................................................................................................................................46

5. WIDGET INFORMATION AND SUPPORTED COMMAND VERBS ....................................... 47

6. PORT CONFIGURATIONS ..................................................................................................... 48

6.1. Pin Configuration Default Register Settings .....................................................................................49

7. WIDGET INFORMATION ........................................................................................................ 50

7.1. Widget List .......................................................................................................................................51

7.2. Root (NID = 00h): VendorID ............................................................................................................52

7.3. Root (NID = 00h): RevID ..................................................................................................................53

7.3.1. Root (NID = 00h): NodeInfo ...............................................................................................53

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Eight channel HD Audio codec optimized for low power

7.4. AFG (NID = 01h): NodeInfo .............................................................................................................54

7.4.1. AFG (NID = 01h): FGType .................................................................................................55

7.4.2. AFG (NID = 01h): AFGCap ................................................................................................55

7.4.3. AFG (NID = 01h): PCMCap ...............................................................................................56

7.4.4. AFG (NID = 01h): StreamCap ............................................................................................58

7.4.5. AFG (NID = 01h): InAmpCap .............................................................................................58

7.4.6. AFG (NID = 01h): PwrStateCap .........................................................................................59

7.4.7. AFG (NID = 01h): GPIOCnt ...............................................................................................60

7.4.8. AFG (NID = 01h): OutAmpCap ..........................................................................................61

7.4.9. AFG (NID = 01h): PwrState ...............................................................................................62

7.4.10. AFG (NID = 01h): UnsolResp ..........................................................................................63

7.4.11. AFG (NID = 01h): GPIO ...................................................................................................63

7.4.12. AFG (NID = 01h): GPIOEn ...............................................................................................64

7.4.13. AFG (NID = 01h): GPIODir ..............................................................................................65

7.4.14. AFG (NID = 01h): GPIOWakeEn .....................................................................................66

7.4.15. AFG (NID = 01h): GPIOUnsol ..........................................................................................68

7.4.16. AFG (NID = 01h): GPIOSticky .........................................................................................69

7.4.17. AFG (NID = 01h): SubID ..................................................................................................70

7.4.18. AFG (NID = 01h): GPIOPlrty ............................................................................................70

7.4.19. AFG (NID = 01h): GPIODrive ...........................................................................................72

7.4.20. AFG (NID = 01h): DMic ....................................................................................................73

7.4.21. AFG (NID = 01h): DACMode ...........................................................................................74

7.4.22. AFG (NID = 01h): ADCMode ...........................................................................................76

7.4.23. AFG (NID = 01h): EAPD ..................................................................................................76

7.4.24. AFG (NID = 01h): PortUse ...............................................................................................78

7.4.25. AFG (NID = 01h): VSPwrState .........................................................................................79

7.4.26. AFG (NID = 01h): AnaPort ...............................................................................................79

7.4.27. AFG (NID = 01h): AnaBeep .............................................................................................80

7.4.28. AFG (NID = 01h): Reset ...................................................................................................81

7.5. PortA (NID = 0Ah): WCap ................................................................................................................82

7.5.1. PortA (NID = 0Ah): PinCap ................................................................................................83

7.5.2. PortA (NID = 0Ah): ConLst .................................................................................................85

7.5.3. PortA (NID = 0Ah): ConLstEntry0 ......................................................................................85

7.5.4. PortA (NID = 0Ah): InAmpLeft ............................................................................................86

7.5.5. PortA (NID = 0Ah): InAmpRight .........................................................................................86

7.5.6. PortA (NID = 0Ah): ConSelectCtrl ......................................................................................87

7.5.7. PortA (NID = 0Ah): PwrState .............................................................................................87

7.5.8. PortA (NID = 0Ah): PinWCntrl ............................................................................................88

7.5.9. PortA (NID = 0Ah): UnsolResp ..........................................................................................89

7.5.10. PortA (NID = 0Ah): ChSense ...........................................................................................90

7.5.11. PortA (NID = 0Ah): EAPDBTLLR .....................................................................................90

7.5.12. PortA (NID = 0Ah): ConfigDefault ....................................................................................91

7.6. PortB (NID = 0Bh): WCap ................................................................................................................94

7.6.1. PortB (NID = 0Bh): PinCap ................................................................................................95

7.6.2. PortB (NID = 0Bh): ConLst .................................................................................................97

7.6.3. PortB (NID = 0Bh): ConLstEntry0 ......................................................................................97

7.6.4. PortB (NID = 0Bh): ConSelectCtrl ......................................................................................98

7.6.5. PortB (NID = 0Bh): InAmpLeft ............................................................................................98

7.6.6. PortB (NID = 0Bh): InAmpRight .........................................................................................99

7.6.7. PortB (NID = 0Bh): PwrState .............................................................................................99

7.6.8. PortB (NID = 0Bh): PinWCntrl ..........................................................................................100

7.6.9. PortB (NID = 0Bh): UnsolResp ........................................................................................101

7.6.10. PortB (NID = 0Bh): ChSense .........................................................................................102

7.6.11. PortB (NID = 0Bh): EAPDBTLLR ...................................................................................102

7.6.12. PortB (NID = 0Bh): ConfigDefault ..................................................................................103

7.7. PortC (NID = 0Ch): WCap .............................................................................................................106

7.7.1. PortC (NID = 0Ch): PinCap ..............................................................................................107

7.7.2. PortC (NID = 0Ch): ConLst ..............................................................................................108

7.7.3. PortC (NID = 0Ch): ConLstEntry0 ....................................................................................109

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Eight channel HD Audio codec optimized for low power

7.7.4. PortC (NID = 0Ch): InAmpLeft .........................................................................................110

7.7.5. PortC (NID = 0Ch): InAmpRight .......................................................................................110

7.7.6. PortC (NID = 0Ch): ConSelectCtrl ...................................................................................111

7.7.7. PortC (NID = 0Ch): PwrState ...........................................................................................111

7.7.8. PortC (NID = 0Ch): PinWCntrl .........................................................................................112

7.7.9. PortC (NID = 0Ch): UnsolResp ........................................................................................113

7.7.10. PortC (NID = 0Ch): ChSense .........................................................................................113

7.7.11. PortC (NID = 0Ch): EAPDBTLLR ...................................................................................114

7.7.12. PortC (NID = 0Ch): ConfigDefault ..................................................................................114

7.8. PortD (NID = 0Dh): WCap .............................................................................................................118

7.8.1. PortD (NID = 0Dh): PinCap ..............................................................................................119

7.8.2. PortD (NID = 0Dh): ConLst ..............................................................................................121

7.8.3. PortD (NID = 0Dh): ConLstEntry0 ....................................................................................121

7.8.4. PortD (NID = 0Dh): InAmpLeft .........................................................................................122

7.8.5. PortD (NID = 0Dh): InAmpRight .......................................................................................122

7.8.6. PortD (NID = 0Dh): ConSelectCtrl ...................................................................................123

7.8.7. PortD (NID = 0Dh): PwrState ...........................................................................................123

7.8.8. PortD (NID = 0Dh): PinWCntrl .........................................................................................124

7.8.9. PortD (NID = 0Dh): UnsolResp ........................................................................................125

7.8.10. PortD (NID = 0Dh): ChSense .........................................................................................125

7.8.11. PortD (NID = 0Dh): EAPDBTLLR ...................................................................................126

7.8.12. PortD (NID = 0Dh): ConfigDefault ..................................................................................126

7.9. PortE (NID = 0Eh): WCap ..............................................................................................................130

7.9.1. PortE (NID = 0Eh): PinCap ..............................................................................................131

7.9.2. PortE (NID = 0Eh): ConLst ...............................................................................................133

7.9.3. PortE (NID = 0Eh): ConLstEntry0 ....................................................................................133

7.9.4. PortE (NID = 0Eh): InAmpLeft ..........................................................................................134

7.9.5. PortE (NID = 0Eh): InAmpRight .......................................................................................134

7.9.6. PortE (NID = 0Eh): ConSelectCtrl ....................................................................................135

7.9.7. PortE (NID = 0Eh): PwrState ...........................................................................................135

7.9.8. PortE (NID = 0Eh): PinWCntrl ..........................................................................................136

7.9.9. PortE (NID = 0Eh): UnsolResp ........................................................................................137

7.9.10. PortE (NID = 0Eh): ChSense .........................................................................................137

7.9.11. PortE (NID = 0Eh): EAPDBTLLR ...................................................................................138

7.9.12. PortE (NID = 0Eh): ConfigDefault ..................................................................................138

7.10. PortF (NID = 0Fh): WCap ............................................................................................................142

7.10.1. PortF (NID = 0Fh): PinCap .............................................................................................143

7.10.2. PortF (NID = 0Fh): ConLst .............................................................................................145

7.10.3. PortF (NID = 0Fh): ConLstEntry0 ...................................................................................145

7.10.4. PortF (NID = 0Fh): InAmpLeft ........................................................................................146

7.10.5. PortF (NID = 0Fh): InAmpRight ......................................................................................146

7.10.6. PortF (NID = 0Fh): ConSelectCtrl ..................................................................................147

7.10.7. PortF (NID = 0Fh): PwrState ..........................................................................................147

7.10.8. PortF (NID = 0Fh): PinWCntrl ........................................................................................148

7.10.9. PortF (NID = 0Fh): UnsolResp .......................................................................................149

7.10.10. PortF (NID = 0Fh): ChSense ........................................................................................149

7.10.11. PortF (NID = 0Fh): EAPDBTLLR .................................................................................150

7.10.12. PortF (NID = 0Fh): ConfigDefault .................................................................................150

7.11. PortG (NID = 0Gh): WCap ...........................................................................................................153

7.11.1. PortG (NID = 0Gh): PinCap ...........................................................................................154

7.11.2. PortG (NID = 0Gh): ConLst ............................................................................................156

7.11.3. PortG (NID = 0Gh): ConLstEntry0 .................................................................................156

7.11.4. PortG (NID = 0Gh): InAmpLeft .......................................................................................157

7.11.5. PortG (NID = 0Gh): InAmpRight ....................................................................................157

7.11.6. PortG (NID = 0Gh): ConSelectCtrl .................................................................................158

7.11.7. PortG (NID = 0Gh): PwrState .........................................................................................158

7.11.8. PortG (NID = 0Gh): PinWCntrl .......................................................................................159

7.11.9. PortG (NID = 0Gh): UnsolResp ......................................................................................160

7.11.10. PortG (NID = 0Gh): ChSense ......................................................................................160

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Eight channel HD Audio codec optimized for low power

7.11.11. PortG (NID = 0Gh): EAPDBTLLR ................................................................................161

7.11.12. PortG (NID = 0Gh): ConfigDefault ...............................................................................161

7.12. ADC0 (NID = 1Ah): WCap ...........................................................................................................164

7.12.1. ADC0 (NID = 1Ah): ConLst ............................................................................................165

7.12.2. ADC0 (NID = 1Ah): ConLstEntry0 ..................................................................................166

7.12.3. ADC0 (NID = 1Ah): Cnvtr ...............................................................................................166

7.12.4. ADC0 (NID = 1Ah): ProcState ........................................................................................168

7.12.5. ADC0 (NID = 1Ah): PwrState .........................................................................................169

7.12.6. ADC0 (NID = 1Ah): CnvtrID ...........................................................................................169

7.13. ADC1 (NID = 1Bh): WCap ...........................................................................................................171

7.13.1. ADC1 (NID = 1Bh): ConLst ............................................................................................172

7.13.2. ADC1 (NID = 1Bh): ConLstEntry0 ..................................................................................173

7.13.3. ADC1 (NID = 1Bh): Cnvtr ...............................................................................................173

7.13.4. ADC1 (NID = 1Bh): ProcState ........................................................................................175

7.13.5. ADC1 (NID = 1Bh): PwrState .........................................................................................175

7.13.6. ADC1 (NID = 1Bh): CnvtrID ...........................................................................................176

7.14. DigBeep (NID = 1Ch): WCap .......................................................................................................178

7.14.1. DigBeep (NID = 1Ch): OutAmpCap ...............................................................................179

7.14.2. DigBeep (NID = 1Ch): OutAmpLeft ................................................................................179

7.14.3. DigBeep (NID = 1Ch): PwrState ....................................................................................180

7.14.4. DigBeep (NID = 1Ch): Gen ............................................................................................181

7.15. Mixer (NID = 1Dh): WCap ............................................................................................................182

7.15.1. Mixer (NID = 1Dh): InAmpCap .......................................................................................183

7.15.2. Mixer (NID = 1Dh): ConLst .............................................................................................184

7.15.3. Mixer (NID = 1Dh): ConLstEntry0 ..................................................................................185

7.15.4. Mixer (NID = 1Dh): InAmpLeft0 ......................................................................................185

7.15.5. Mixer (NID = 1Dh): InAmpRight0 ...................................................................................186

7.15.6. Mixer (NID = 1Dh): InAmpLeft1 ......................................................................................186

7.15.7. Mixer (NID = 1Dh): InAmpRight1 ...................................................................................187

7.15.8. Mixer (NID = 1Dh): InAmpLeft2 ......................................................................................188

7.15.9. Mixer (NID = 1Dh): InAmpRight2 ...................................................................................188

7.15.10. Mixer (NID = 1Dh): InAmpLeft3 ....................................................................................189

7.15.11. Mixer (NID = 1Dh): InAmpRight3 .................................................................................189

7.15.12. Mixer (NID = 1Dh): InAmpLeft4 ....................................................................................190

7.15.13. Mixer (NID = 1Dh): InAmpRight4 .................................................................................190

7.15.14. Mixer (NID = 1Dh): PwrState .......................................................................................191

7.16. MixerOutVol (NID = 1Eh): WCap .................................................................................................193

7.16.1. MixerOutVol (NID = 1Eh): ConLst ..................................................................................194

7.16.2. MixerOutVol (NID = 1Eh): ConLstEntry0 .......................................................................195

7.16.3. MixerOutVol (NID = 1Dh): OutAmpCap .........................................................................195

7.16.4. MixerOutVol (NID = 1Dh): OutAmpLeft ..........................................................................196

7.16.5. MixerOutVol (NID = 1Dh): OutAmpRight .......................................................................197

7.16.6. MixerOutVol (NID = 1Dh): PwrState ..............................................................................197

7.17. Vendor Reserved (NID = 1Fh) .....................................................................................................199

7.18. PortH (NID = 11h): WCap ............................................................................................................200

7.18.1. PortH (NID = 11h): PinCap ............................................................................................201

7.18.2. PortH (NID = 11h): ConLst .............................................................................................203

7.18.3. PortH (NID = 11h): ConLstEntry0 ..................................................................................203

7.18.4. PortH (NID = 11h): InAmpLeft ........................................................................................204

7.18.5. PortH (NID = 11h): InAmpRight .....................................................................................204

7.18.6. PortH (NID = 11h): ConSelectCtrl ..................................................................................205

7.18.7. PortH (NID = 11h): PwrState ..........................................................................................205

7.18.8. PortH (NID = 11h): PinWCntrl ........................................................................................206

7.18.9. PortH (NID = 11h): UnsolResp .......................................................................................207

7.18.10. PortH (NID = 11h): ChSense .......................................................................................207

7.18.11. PortH (NID = 11h): EAPDBTLLR .................................................................................208

7.18.12. PortH (NID = 11h): ConfigDefault ................................................................................208

7.19. CD (NID = 12h): WCap ................................................................................................................211

7.19.1. CD (NID = 12h): PinCap ................................................................................................212

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Eight channel HD Audio codec optimized for low power

7.19.2. CD (NID = 12h): PwrState ..............................................................................................214

7.19.3. CD (NID = 12h): PinWCntrl ............................................................................................214

7.19.4. CD (NID = 12h): ConfigDefault ......................................................................................215

7.20. DMic0 (NID = 13h): WCap ...........................................................................................................218

7.20.1. DMic0 (NID = 13h): PinCap ...........................................................................................219

7.20.2. DMic0 (NID = 13h): InAmpLeft .......................................................................................221

7.20.3. DMic0 (NID = 13h): InAmpRight ....................................................................................221

7.20.4. DMic0 (NID = 13h): PwrState .........................................................................................221

7.20.5. DMic0 (NID = 13h): PinWCntrl .......................................................................................222

7.20.6. DMic0 (NID = 13h): UnsolResp ......................................................................................223

7.20.7. DMic0 (NID = 13h): ConfigDefault .................................................................................223

7.21. DMic1 (NID = 14h): WCap ...........................................................................................................227

7.21.1. DMic1 (NID = 14h): PinCap ...........................................................................................228

7.21.2. DMic1 (NID = 14h): InAmpLeft .......................................................................................230

7.21.3. DMic1 (NID = 14h): InAmpRight ....................................................................................230

7.21.4. DMic1 (NID = 14h): PwrState .........................................................................................230

7.21.5. DMic1 (NID = 14h): PinWCntrl .......................................................................................231

7.21.6. DMic1 (NID = 14h): UnsolResp ......................................................................................232

7.21.7. DMic1 (NID = 14h): ConfigDefault .................................................................................232

7.22. DAC0 (NID = 15h): WCap ............................................................................................................236

7.22.1. DAC0 (NID = 15h): Cnvtr ...............................................................................................237

7.22.2. DAC0 (NID = 15h): OutAmpLeft .....................................................................................239

7.22.3. DAC0 (NID = 15h): OutAmpRight ..................................................................................239

7.22.4. DAC0 (NID = 15h): PwrState .........................................................................................240

7.22.5. DAC0 (NID = 15h): CnvtrID ............................................................................................240

7.22.6. DAC0 (NID = 15h): EAPDBTLLR ...................................................................................241

7.23. DAC1 (NID = 16h): WCap ............................................................................................................242

7.23.1. DAC1 (NID = 16h): Cnvtr ...............................................................................................243

7.23.2. DAC1 (NID = 16h): OutAmpLeft .....................................................................................245

7.23.3. DAC1 (NID = 16h): OutAmpRight ..................................................................................245

7.23.4. DAC1 (NID = 16h): PwrState .........................................................................................246

7.23.5. DAC1 (NID = 16h): CnvtrID ............................................................................................246

7.23.6. DAC1 (NID = 16h): EAPDBTLLR ...................................................................................247

7.24. DAC2 (NID = 17h): WCap ............................................................................................................248

7.24.1. DAC2 (NID = 17h): Cnvtr ...............................................................................................249

7.24.2. DAC2 (NID = 17h): OutAmpLeft .....................................................................................251

7.24.3. DAC2 (NID = 17h): OutAmpRight ..................................................................................251

7.24.4. DAC2 (NID = 17h): PwrState .........................................................................................252

7.24.5. DAC2 (NID = 17h): CnvtrID ............................................................................................252

7.24.6. DAC2 (NID = 17h): EAPDBTLLR ...................................................................................253

7.25. DAC3 (NID = 18h): WCap ............................................................................................................254

7.25.1. DAC3 (NID = 18h): Cnvtr ...............................................................................................255

7.25.2. DAC3 (NID = 18h): OutAmpLeft .....................................................................................257

7.25.3. DAC3 (NID = 18h): OutAmpRight ..................................................................................257

7.25.4. DAC3 (NID = 18h): PwrState .........................................................................................258

7.25.5. DAC3 (NID = 18h): CnvtrID ............................................................................................258

7.25.6. DAC3 (NID = 18h): EAPDBTLLR ...................................................................................259

7.26. Vendor Reserved (NID = 19h) .....................................................................................................260

7.27. ADC0Mux (NID = 20h): WCap .....................................................................................................261

7.27.1. ADC0Mux (NID = 20h): ConLst ......................................................................................262

7.27.2. ADC0Mux (NID = 17h): ConLstEntry4 ...........................................................................263

7.27.3. ADC0Mux (NID = 20h): ConLstEntry0 ...........................................................................263

7.27.4. ADC0Mux (NID = 20h): OutAmpCap .............................................................................264

7.27.5. ADC0Mux (NID = 20h): OutAmpLeft ..............................................................................265

7.27.6. ADC0Mux (NID = 20h): OutAmpRight ...........................................................................265

7.27.7. ADC0Mux (NID = 20h): ConSelectCtrl ...........................................................................266

7.27.8. ADC0Mux (NID = 20h): PwrState ..................................................................................266

7.27.9. ADC0Mux (NID = 20h): EAPDBTLLR ............................................................................267

7.28. ADC1Mux (NID = 21h): WCap .....................................................................................................269

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7.28.1. ADC1Mux (NID = 21h): ConLst ......................................................................................270

7.28.2. ADC1Mux (NID = 21h): ConLstEntry4 ...........................................................................271

7.28.3. ADC1Mux (NID = 21h): ConLstEntry0 ...........................................................................271

7.28.4. ADC1Mux (NID = 21h): OutAmpCap .............................................................................272

7.28.5. ADC1Mux (NID = 21h): OutAmpLeft ..............................................................................273

7.28.6. ADC1Mux (NID = 21h): OutAmpRight ...........................................................................273

7.28.7. ADC1Mux (NID = 21h): ConSelectCtrl ...........................................................................274

7.28.8. ADC1Mux (NID = 21h): PwrState ..................................................................................274

7.28.9. ADC1Mux (NID = 21h): EAPDBTLLR ............................................................................275

7.29. Dig0Pin (NID = 22h): WCap .........................................................................................................277

7.29.1. Dig0Pin (NID = 22h): PinCap .........................................................................................278

7.29.2. Dig0Pin (NID = 22h): ConLst .........................................................................................280

7.29.3. Dig0Pin (NID = 22h): ConLstEntry0 ...............................................................................280

7.29.4. Dig0Pin (NID = 22h): PwrState ......................................................................................281

7.29.5. Dig0Pin (NID = 22h): PinWCntrl .....................................................................................282

7.29.6. Dig0Pin (NID = 22h): UnsolResp ..................................................................................282

7.29.7. Dig0Pin (NID = 22h): ChSense ......................................................................................283

7.29.8. Dig0Pin (NID = 22h): ConfigDefault ...............................................................................283

7.30. Dig1Pin (NID = 23h): WCap .........................................................................................................286

7.30.1. Dig1Pin (NID = 23h): PinCap .........................................................................................287

7.30.2. Dig1Pin (NID = 23h): ConLst .........................................................................................289

7.30.3. Dig1Pin (NID = 20h): ConLstEntry0 ...............................................................................289

7.30.4. Dig1Pin (NID = 23h): PwrState ......................................................................................290

7.30.5. Dig1Pin (NID = 23h): PinWCntrl .....................................................................................291

7.30.6. Dig1Pin (NID = 20h): ConfigDefault ...............................................................................291

7.31. Dig2Pin (NID = 24h): WCap .........................................................................................................294

7.31.1. Dig2Pin (NID = 24h): PinCap .........................................................................................295

7.31.2. Dig2Pin (NID = 24h): ConLst .........................................................................................297

7.31.3. Dig1Pin (NID = 20h): ConLstEntry0 ...............................................................................297

7.31.4. Dig2Pin (NID = 24h): PwrState ......................................................................................298

7.31.5. Dig2Pin (NID = 24h): PinWCntrl .....................................................................................299

7.31.6. Dig1Pin (NID = 20h): ConfigDefault ...............................................................................299

7.32. SPDIFOut0 (NID = 25h): WCap ...................................................................................................302

7.32.1. SPDIFOut0 (NID = 25h): PCMCap ................................................................................303

7.32.2. SPDIFOut0 (NID = 25h): StreamCap .............................................................................305

7.32.3. SPDIFOut0 (NID = 25h): OutAmpCap ...........................................................................306

7.32.4. SPDIFOut0 (NID = 25h): Cnvtr ......................................................................................306

7.32.5. SPDIFOut0 (NID = 25h): OutAmpLeft ............................................................................308

7.32.6. SPDIFOut0 (NID = 25h): OutAmpRight .........................................................................308

7.32.7. SPDIFOut0 (NID = 25h): PwrState ................................................................................309

7.32.8. SPDIFOut0 (NID = 25h): CnvtrID ...................................................................................310

7.32.9. SPDIFOut0 (NID = 25h): DigCnvtr .................................................................................310

7.33. SPDIFOut1 (NID = 26h): WCap ...................................................................................................312

7.33.1. SPDIFOut1 (NID = 26h): PCMCap ................................................................................313

7.33.2. SPDIFOut1 (NID = 26h): StreamCap .............................................................................315

7.33.3. SPDIFOut1 (NID = 26h): OutAmpCap ...........................................................................316

7.33.4. SPDIFOut1 (NID = 26h): Cnvtr ......................................................................................316

7.33.5. SPDIFOut1 (NID = 26h): OutAmpLeft ............................................................................318

7.33.6. SPDIFOut1 (NID = 26h): OutAmpRight .........................................................................318

7.33.7. SPDIFOut1 (NID = 26h): PwrState ................................................................................319

7.33.8. SPDIFOut1 (NID = 26h): CnvtrID ...................................................................................320

7.33.9. SPDIFOut1 (NID = 26h): DigCnvtr .................................................................................320

7.34. SPDIFIn (NID = 27h): WCap ........................................................................................................322

7.34.1. SPDIFIn (NID = 27h): PCMCap .....................................................................................323

7.34.2. SPDIFIn (NID = 27h): StreamCap ..................................................................................325

7.34.3. SPDIFIn (NID = 27h): Cnvtr ...........................................................................................326

7.34.4. SPDIFIn (NID = 27h): ConLst ........................................................................................327

7.34.5. SPDIFIn (NID = 27h): ConLstEntry0 ..............................................................................327

7.34.6. SPDIFIn (NID = 27h): PwrState .....................................................................................328

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7.34.7. SPDIFIn (NID = 27h): CnvtrID ........................................................................................329

7.34.8. SPDIFIn (NID = 27h): DigCnvtr ......................................................................................329

7.34.9. SPDIFIn (NID = 27h): InAmpCap ...................................................................................331

7.34.10. SPDIFIn (NID = 27h): InAmpLeft .................................................................................332

7.34.11. SPDIFIn (NID = 27h): InAmpRight ...............................................................................332

7.34.12. SPDIFIn (NID = 27h): VS .............................................................................................332

7.35. InPort0Mux (NID = 28h): WCap ...................................................................................................336

7.35.1. InPort0Mux (NID = 28h): ConLst ....................................................................................337

7.35.2. InPort0Mux (NID = 28h): ConLstEntry0 .........................................................................338

7.35.3. InPort0Mux (NID = 28h): ConSelectCtrl .........................................................................338

7.35.4. InPort0Mux (NID = 28h): PwrState ................................................................................339

7.36. InPort1Mux (NID = 29h): WCap ...................................................................................................341

7.36.1. InPort1Mux (NID = 29h): ConLst ....................................................................................342

7.36.2. InPort1Mux (NID = 29h): ConLstEntry0 .........................................................................343

7.36.3. InPort1Mux (NID = 29h): ConSelectCtrl .........................................................................343

7.36.4. InPort1Mux (NID = 29h): PwrState ................................................................................344

7.37. InPort2Mux (NID = 2Ah): WCap ..................................................................................................346

7.37.1. InPort2Mux (NID = 2Ah): ConLst ...................................................................................347

7.37.2. InPort2Mux (NID = 2Ah): ConLstEntry0 .........................................................................348

7.37.3. InPort2Mux (NID = 2Ah): ConSelectCtrl ........................................................................348

7.37.4. InPort2Mux (NID = 2Ah): PwrState ................................................................................349

7.38. InPort3Mux (NID = 2Bh): WCap ..................................................................................................351

7.38.1. InPort3Mux (NID = 2Bh): ConLst ...................................................................................352

7.38.2. InPort3Mux (NID = 2Bh): ConLstEntry0 .........................................................................353

7.38.3. InPort3Mux (NID = 2Bh): ConSelectCtrl ........................................................................353

7.38.4. InPort3Mux (NID = 2Bh): PwrState ................................................................................354

8. PINOUTS AND PACKAGING ............................................................................................... 356

8.1. 48QFP ...........................................................................................................................................356

8.1.1. 48 QFP Pin Assignment ...................................................................................................356

8.1.2. 48QFP Pin Table .............................................................................................................357

8.1.3. 48QFP Package Outline and Package Dimensions ........................................................358

8.2. 40QFN ..........................................................................................................................................359

8.2.1. 40QFN Pin Assignment ...................................................................................................359

8.2.2. 40QFN Pin Table) ...........................................................................................................360

8.2.3. 40QFN Package Outline and Package Dimensions .......................................................361

8.3. 48QFP and 40QFN Standard Reflow Profile Data .........................................................................362

9. DISCLAIMER ......................................................................................................................... 363

10. DOCUMENT REVISION HISTORY ..................................................................................... 364

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LIST OF TABLES

Table 1. 48QFP Port Characteristics .............................................................................................................14

Table 2. 40QFN Port Characteristics .............................................................................................................14

Table 3. Analog Output Port Behavior ...........................................................................................................15

Table 4. 48pin Jack Detect ............................................................................................................................16

Table 5. 40pin Jack Detect ............................................................................................................................16

Table 6. SPDIF OUT 0 Behavior ....................................................................................................................17

Table 7. SPDIF OUT 1 Behavior ....................................................................................................................18

Table 8. SPDIF Behavior ...............................................................................................................................19

Table 9. Input Multiplexers .............................................................................................................................20

Table 10. Example channel mapping .............................................................................................................23

Table 12. Valid Digital Mic Configurations .....................................................................................................26

Table 13. DMIC_CLK and DMIC_0,1 Operation During Power State ............................................................26

Table 14. Headphone Amp Enable Configuration ..........................................................................................33

Table 15. EAPD Analog PC_Beep behavior ..................................................................................................34

Table 16. EAPD Behavior ..............................................................................................................................34

Table 17. GPIO Pin mapping .........................................................................................................................35

Table 18. Electrical Specification: Maximum Ratings ...................................................................................38

Table 19. Recommended Operating Conditions ............................................................................................38

Table 20. 92HD89D Analog Performance Characteristics .............................................................................39

Table 21. HD Audio Bus Timing .....................................................................................................................43

Table 22. SPDIF Timing .................................................................................................................................43

Table 23. Digital Mic timing ............................................................................................................................44

Table 24. GPIO Characteristics .....................................................................................................................44

Table 25. Pin Configuration Default Settings .................................................................................................49

Table 26. Command Format for Verb with 4-bit Identifier ..............................................................................50

Table 27. Command Format for Verb with 12-bit Identifier ............................................................................50

Table 28. Solicited Response Format ............................................................................................................50

Table 29. Unsolicited Response Format ........................................................................................................50

Table 30. Widget List .....................................................................................................................................51

Table 31. 48QFP Pin Table .........................................................................................................................357

Table 32. 40QFN Pin Table .........................................................................................................................360

Table 33. Standard Reflow Profile ...............................................................................................................362

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LIST OF FIGURES

Figure 1. 92HD89D Block Diagram ................................................................................................................13

Figure 2. System Diagram ............................................................................................................................13

Figure 3. Multi-channel capture ......................................................................................................................24

Figure 4. Multi-channel timing diagram ..........................................................................................................24

Figure 5. Single Digital Microphone (data is ported to both left and right channels .......................................27

Figure 6. Stereo Digital Microphone Configuration ........................................................................................28

Figure 7. Quad Digital Microphone Configuration ..........................................................................................29

Figure 8. HP EAPD Example to be replaced by single pin for internal amp ..................................................35

Figure 9. HD Audio Bus Timing ......................................................................................................................43

Figure 10. 48QFP Functional Block Diagram .................................................................................................45

Figure 11. 40QFN Functional Block Diagram ................................................................................................46

Figure 12. Widget Diagram (same for both package option) .........................................................................47

Figure 13. Port Configurations .......................................................................................................................48

Figure 14. Pin Assignment ...........................................................................................................................356

Figure 15. 48QFP Package Diagram ...........................................................................................................358

Figure 16. Pin Assignment ...........................................................................................................................359

Figure 17. 40QFN Package Diagram ...........................................................................................................361

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1. DESCRIPTION

1.1. Overview

The 92HD89D is a high fidelity, 8-channel audio codec compatible with the Intel High Definition (HD)

Audio Interface. The 92HD89D codec provides high quality, HD Audio capability notebooks and

desktops.

The 92HD89D is designed to meet or exceed premium logo requirements for Microsoft’s Windows

Logo Program (WLP) per Logo Point.

The 92HD89D provides stereo 24-bit, full duplex resolution supporting sample rates up to 192kHz by

the DAC and ADC. 92HD89D SPDIF outputs support sample rates of 192kHz, 176.4kHz, 96kHz,

88.2kHz, 48kHz, and 44.1kHz.

The 92HD89D supports a wide range of notebook and desktop 8-channel configurations. The 2 inde-

pendent SPDIF output interfaces provides connectivity to Consumer Electronic equipment like Dolby

Digital decoders, powered speakers, mini disk drives or to a home entertainment system. Simultane-

ous HDMI and SPDIF output is possible.

MIC inputs can be programmed with 0/10/20/30dB boost. For more advanced configurations, the

92HD89D has up to 7 General Purpose I/O (GPIO).

The port presence detect capabilities allow the codecs to detect when audio devices are connected

to the codec. The fully parametric IDT SoftEQ can be initiated upon headphone jack insertion and

removal for protection of notebook speakers.

The 92HD89D operates with a 3.3V digital supply and a 5V analog supply. It can also work with 1.5V

and 3.3V HDA signaling.

The 92HD89D is available in a 48-pin QFP or 40-pad QFN Environmental (ROHS) package.

1.2. Orderable Part Numbers

92HD89D1X5NDGXyyX

92HD89D2X5NDGXyyX

92HD89D3X5PRGXyyX

5V Analog, 40QFN, 1.5V HDA Signaling

5V Analog, 40QFN, 3.3V HDA Signaling

5V Analog, 48QFP, switchable 1.5V or 3.3V HDA Signaling

yy = silicon stepping/revision, contact sales for current data.

Add an “8” to the end for tape and reel delivery.

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1.3. Block Diagram

Figure 1. 92HD89D Block Diagram

Port A

Port B

Port C

Port D

Port E

Port F

Port G

Port H

SPDIF IN

SPDIF Out 1

SPDIF

SPDIF Out 2

Figure 2. System Diagram

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2. DETAILED DESCRIPTION

2.1. Port Functionality

Multi-function (Input / output) ports allow for the highest possible flexibility. 8 bi-directional ports, 3

are headphone capable, support a wide variety of consumer desktop and mobile system use mod-

els.

Pins

Port

Input

Output

Headphone

Mic Bias

(Vref pin)

Input

boost amp

39/41

21/22

23/24

35/36

14/15

16/17

43/44

45/46

48

A

Yes

B

C

D

Yes

E

Yes

F

G

H

SPDIF_OUT0

SPDIF_OUT1

SPDIF_IN/OUT1

DMIC0

40

47

Yes

4 (CLK=2)

30 (CLK=2)

Yes

DMIC1

Table 1. 48QFP Port Characteristics

Pins

Port

Input

Output

Headphone

Mic Bias

(Vref pin)

Input

boost amp

33/34

18/19

20/21

29/30

11/12

13/14

36/37

38/39

1

A

Yes

B

C

D

Yes

E

Yes

F

G

H

SPDIF_OUT0

SPDIF_OUT1

40

Table 2. 40QFN Port Characteristics

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2.1.1.

Port Characteristics

Universal (Bi-directional) jacks are supported on ports A, B, C, D, E, F, G and H for all family mem-

bers. Ports A, B, and D are designed to drive 32 ohm (nominal) headphones or a 10K (nominal) load.

Line Level outputs are intended to drive an external 10K load (nominal) and an on board shunt resis-

tor of 20-47K (nominal). However, applications may support load impedances of 2.8K ohms and

above when implementing ports capable of operating as microphone inputs or line outputs. Input

ports are 75K (nominal) at the pin.

DAC full scale outputs and intended full scale input levels are greater than 1V rms at 5V (+5%/

-10%) to meet WLP requirements. Line output ports and Headphone output ports on the Yangtze

Series codec may be configured for +3dBV full scale output levels by using a vendor specific verb.

Output ports are always on to prevent pops/clicks associated with charging and discharging output

coupling capacitors. This maintains proper bias on output coupling caps even in power state D3 as

long as AVDD is available. Unused ports should be left unconnected. When updating existing

designs, ensure that there are no conflicts between the output ports on the codec and existing cir-

cuitry.

AFG Power State Input Enable

Output Enable

Port Behavior

D0-D1

1

0

1

0

1

0

Not allowed. Port is active as Input.

Active - Port enabled as input

Active - Port enabled as output

Inactive -port is powered on (low output impedance)

but drives silence only.

D2

1

0

1

0

1

0

Not allowed. Port is active as Input.

Inactive - Port enabled as input but powered down

Active - Port enabled as output

Inactive -port is powered on (low output impedance)

but drives silence only.

D3

1

0

Not allowed. Port is active as Input.

Inactive (lower power) - Port keeps output coupling

caps charged.

0

-

1

0

-

Low power state. If enabled, Beep will output from

the port

Inactive (lower power) - Port keeps output coupling

caps charged.

D3cold

D4

Inactive (lower power) - Port keeps output coupling

caps charged.

-

Inactive (lower power) - Port keeps output coupling

caps charged.

D5

-

Off - Charge on coupling caps will not be maintained.

Table 3. Analog Output Port Behavior

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2.1.2.

Vref_Out

Ports A, B, C (48-pin package only), & E support Vref_Out pins for biasing electret cartridge micro-

phones. Settings of 80% AVDD, 50% AVDD, GND, and Hi-Z are supported. Attempting to program a

pin widget control with a reserved or unsupported value will cause the associated Vref_Out pin to

assume a Hi-Z state and the pin widget control Vref_En field will return a value of ‘000’ (Hi-Z) when

read.

2.1.3.

Jack Detect

Plugs inserted to a jack are detected using SENSE inputs as described in the tables below. Per

ECR15-B, the detection circuit operates when the CODEC is in D0 - D3 and can also operate if both

the CODEC and Controller are in D3 (no bus clock.) Jack detection requires that all supplies (analog

and digital) are active and stable. When AVDD is not present, the value reported in the pin widget is

invalid.

When the HD Audio bus is in a low power state (reset asserted and clock stopped) the CODEC will

generate a Power State Change Request when a change in port connectivity is sensed and then

generate an unsolicited response after the HD Audio link has been brought out of a low power state

and the device has been enumerated. Per ECR015-B, this will take less than 10mS.

The following table summarizes the proper resistor tolerances for different analog supply voltages.

AVdd Nominal

Voltage (+/- 5%)

Resistor Tolerance Resistor Tolerance

Pull-Up

SENSE_A/B/C

4.75 or 5VV

1%

Resistor

SENSE_A

PORT A

PORT B

PORT C

PORT D

SENSE_B

SENSE_C

SPDIFOUT0

SPDIFOUT1(pin40)

DMIC0

39.2K

20.0K

10.0K

5.11K

2.49K

PORT E

PORT F

PORT G

SPDIFOUT0

Pull-up to AVDD

DMIC1

Pull-up to AVDD

Table 4. 48pin Jack Detect

Resistor

39.2K

20.0K

10.0K

5.11K

SENSE_A

PORT A

PORT B

PORT C

PORT D

SENSE_B

PORT E

PORT F

PORT G

PORT H

2.49K

Pull-up to AVDD

Table 5. 40pin Jack Detect

See reference design for more information on Jack Detect implementation.

2.1.4.

SPDIF Output

Both SPDIF Outputs can operate at 44.1kHz, 48kHz, 88.2kHz, 96kHz and 192KHz as defined in the

Intel High Definition Audio Specification with resolutions up to 24 bits. This insures compatibility with

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all consumer audio gear and allows for convenient integration into home theater systems and media

center PCs.

The two SPDIF output converters can not be aligned in phase with the DACs. Even when attached

to the same stream, the two SPDIF output converters may be misaligned with respect to their frame

boundaries.

Per the HDA015-B ECR, the SPDIF outputs support the ability to provide clocking information even

when no stream is selected for the converter, or when in a low power state. Also, as stated in the

ECR, the SPDIF output ports support port presence detect.

SPDIF Outputs are outlined in tables below.

Converter

Dig

Enable

AFG Power

State

Output

Enable

Keep Alive

Enable

Stream

ID

RESET#

Pin Behavior

Asserted

(Low)

Hi-Z¹immediately after power on, otherwise the

previous state is retained.

D0-D3

-

Disabled

Enabled

-

Hi-Z

Disabled

Enabled

Disabled

Enabled

Active - Pin drives 0

Disabled

Enabled

0

Active - Pin drives SPDIF-format, but data is zeroes

D0

1-15

Active - Pin drives SPDIFOut0 data

-

Active - Pin drives SPDIF-format, but data is zeroes

0

Active - Pin drives SPDIF-format, but data is zeroes

1-15

Active - Pin drives SPDIFOut0 data

Disabled

Enabled

Disabled

Enabled

-

Hi-Z

De-

Asserted

(High)

Disabled

Enabled

Disabled

Enabled

-

Active - Pin drives 0

Disabled

D1-D2

Active - Pin drives 0

Active - Pin drives SPDIF-format, but data is zeroes

Enabled

-

Active - Pin drives SPDIF-format, but data is zeroes

Hi-Z

Disabled

Enabled

Disabled

Enabled

-

Hi-Z

Disabled

D3

Hi-Z

Active - Pin drives SPDIF-format, but data is zeroes

Enabled

Active - Pin drives SPDIF-format, but data is zeroes

D3cold

D4

-

Hi-Z

-

D5

-

Table 6. SPDIF OUT 0 Behavior

1.Internal Pull-Down always enabled

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Eight channel HD Audio codec optimized for low power

Out

put

En

Conv

erter Strm Pin

Dig

En

AFG

Power

State

GPIO0 Input

Keep

Alive

En

RESET#

En

Pin Behavior

ID

Mode

able

Asserted

(Low)

EAPD (internal pull-up enabled) immediately after

power on, otherwise the previous state is retained.

D0-D4

-

De-Asserted

(High)

0

1

0

-

0

-

EAPD Pin functions as EAPD

De-Asserted

(High)

Active - Pin reflects GPIO0 configuration (internal

pull-down enabled)

GPIO

De-Asserted

(High)

SPDIF

IN

1

0

-

Pin functions as SPDIF input (internal bias enabled)

0

-

Active - Pin drives 0

0

1

0

Active - Pin drives SPDIF-format, but data is zeroes

Active - Pin drives SPDIFOut1 data

Active - Pin drives SPDIF-format, but data is zeroes

Active - Pin drives SPDIFOut1 data

Active - Pin drives 0

1

0

1

1-15

De-Asserted

(High)

D0

0

1

-

0

1-15

0

1

0

1

0

1

0

1

0

1

0

1

-

Active - Pin drives 0

De-Asserted

(High)

D1-D2

SPDIF

OUT

Active - Pin drives SPDIF-format, but data is zeroes

Hi-Z

De-Asserted

(High)

D3

0

1

Active - Pin drives SPDIF-format, but data is zeroes

De-Asserted

(High)

D3cold

-

Hi-Z

De-Asserted

(High)

D4

D5

0

-

0

-

1

-

Hi-Z

-

Table 7. SPDIF OUT 1 Behavior

2.2. SPDIF Input

SPDIF IN can operate at 44.1 KHz, 48 KHz, or 96 KHz, and implements internal Jack Sensing (Port

presence Detect).

A sophisticated digital PLL allows automatic rate detection and accurate data recovery. The ability to

directly accept consumer SPDIF voltage levels eliminates the need for costly external receiver ICs.

Status flags from the input stream are updated only after the entire valid block has been received (or

at least when all bits of a particular status flag have been received) to ensure that software does not

read an invalid mixture of old and new data.

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In general, the SPDIF input block does not alter the data received. However, it is sometimes neces-

sary to alter the data when the converter widget settings do not match the stream format. The follow-

ing table outlines a few cases and the expected behavior.

Port presence detect for SPDIF_IN operates differently from other ports. Once the PLL has locked

and valid framing (no errors) has been detected, then the port presence detect bit is set. In D3, and

D3 without a clock, it is not possible to check for proper framing. Monitoring of activity (rising and fall-

ing edges) is sufficient to verify a change in connectivity in D3. If no clock is present, then the internal

oscillator is used until a clock is restored. When the HD Audio bus is in a low power state (reset

asserted and clock stopped) the CODEC will generate a Power State Change Request when a

change in SPDIF_IN port connectivity is sensed and then generate an unsolicited response after the

HD Audio link has been brought out of a low power state and the device has been enumerated. Per

ECR015-B, this will take less than 10mS.

Conflict

Behavior

Resolution

Although the SPDIF input block is designed

to handle inputs slightly above or below the

programmed rate, samples may be lost if

the input rate is much higher than the rate

programmed into the converter widget.

Converter widget rate does not

equal the stream rate

Program the converter widget with the

same rate as indicated by the input stream.

If the input stream indicates non PCM data,

the data will be truncated to the requested

word length. If LPCM data is indicated in the

input stream, the CODEC will round the

received data to the requested length.¹

Converter widget programmed

for a word length less than the

word length provided by the

input stream

Program the converter widget with the word

length indicated in the input stream.

Program the converter widget with the word

length indicated in the input stream.

Regardless of content, 24 bits per channel

of data will be transferred from the SPDIF Although not recommended, application or

input stream to the HD Audio bus interface. driver software may program the converter

Converter widget programmed

with a word length greater than

the word length provided by

the input stream.

Truncation or rounding to the requested

word length will be handled as described as

above. Any non-zero data in the incoming

stream will cause problems.

widget with a word length of 24 bits,

truncate the input to the word length

indicated by the input stream, then right

extend the data using 0s to the desired

word length.

Table 8. SPDIF Behavior

1.Rounding may be disabled by setting the disable bit (AFG vendor specific verb -see widget list) or setting the

SPDIF_IN converter widget Frmt StrmType field to 1 (non-PCM)

2.3. Analog Mixer

The mixer supports independent gain (-34.5 to +12dB in 1.5dB steps) on each input as well as inde-

pendent mutes on each input. The following inputs are available: The output of the mixer may be

sent to the ADC where the ADC record gain can adjust the volume. If the output of the mixer is sent

to an analog port, then a separate volume control is provided to adjust the output volume. This mixer

output volume control supports a gain range of -46.5dB to 0dB in 1.5dB steps. (Selecting -46.5dB

will automatically mute the output.)

•

inMux0

inMux1

inMux2

inMux3

CD In

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2.4. Input Multiplexers

The codec implements 4 port input multiplexers. These multiplexers allow a preselection of one of

four possible inputs:

Inport0_Mux

Port A

Inport1_Mux

Port A

Inport2_Mux

Port B

Inport3_mux

DAC 0

Port B

Port E

Port C

DAC 1

Port D

Port G

DAC 2

Port F

Port H

DAC 3

Table 9. Input Multiplexers

2.5. ADC Multiplexers

The codec implements 2 ADC input multiplexers. These multiplexers incorporate the ADC record

gain function (0 to +22.5dB gain in 1.5dB steps) as an output amp and allow a preselection of one of

these possible inputs:

•

Port A

Port B

Port C

Port D

Port E

Port F

Port G

Port H

CD In

Mixer Output

DMIC 0 (only available in 48 pin package)

DMIC1 (only available in 48 pin package)

2.6. Power Management

The HD Audio specification defines power states, power state widgets, and power state verbs.

Power management is implemented at several levels. The Audio Function Group (AFG) , all con-

verter widgets, and all pin complexes support the power state verb F05/705. Converter widgets are

active in D0 and inactive in D1-D3.

The following table describes what functionality is active in each power state.

Vendor

D1¹

Specific

D4²

Off

Function

D0

D2

D3

D3cold

SpecificD5²

SPDIF Outputs

On

Off

On (idle)

Off

On (idle)⁶

Off

SPDIF Input

Off

Digital Microphone inputs

Off

DAC

D2S

ADC

Off

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Vendor

Specific

D4²

Vendor

SpecificD5²

D1¹

Function

D0

D2

D3

D3cold

ADC Volume Control

Ref ADC

On

Off

On

Off

On

Off

On

Off

Analog Clocks

GPIO pins

Off

On⁶

Off

On

VrefOut Pins

Off

Input Boost

Off

Analog mixer

Mixer Volumes

Analog PC_Beep

Digital PC_Beep

Lo/HP Amps

Off

On

On⁶

Low Drive³

Low Drive⁴

On⁵

Off

Low Drive³

Low Drive

Off

Low Drive³

Low Drive

Off

VAG amp

Port Sense

Reference Bias generator

Reference Bandgap core

HD Audio-Link

PLL

On

On⁶

Off⁸

On

Limited⁷

Off⁹

Off

1.No DAC or ADC streams are active. Analog mixing and loop thru are supported.

2.D4 and D5 power states are entered only when D3cold is requested. D4 and D5 may be viewed as D3cold behav-

ioral options.

3.VAG is kept active when ports are disabled or in D3/D3cold/D4. PC_Beep is supported in D3 but may be attenuated

and distorted depending on load impedance.

4.VAG is always ramped up and down gradually, except in the case of a sudden power removal. VAG is active in

D2/D3 but in a low power state.

5. Both AVDD and DVDD must be available for Port Sense to operate.

6.Not active if BITCLK is not running (Controller in D3), but can signal power state change request (PME)

7.Only double function group reset verbs and link reset supported per ECR15b

8.PLL remains on if SPDIF_Out Keep Alive is enabled. PLL disabled only after DAC fading is complete and SDM has

settled.

9.PLL disabled only after DAC fading is complete and SDM has settled.

The D3-default state is available for HD Audio compliance. The programmable values, exposed via

vendor-specific settings, are under IDT Device Driver control for further power reduction. The analog

mixer, line and headphone amps, port presence detect, and internal references may be disabled

using vendor specific verbs. Use of these vendor specific verbs will cause pops.

The default power state for the Audio Function Group after reset is D3.

2.7. AFG D0

The AFG D0 state is the active state for the device. All functions are active if their power state (if they

support power management at their node level) has been set to D0.

2.8. AFG D1

D1 is a lower power mode where all converter widgets are disabled. Analog mixer and port functions

are active. The part will resume from theD1 to theD0 state within 1 mS.

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2.9. AFG D2

The D2 state further reduces power by disabling the mixer and port functions. The port amplifiers

and internal references remain active to keep port coupling caps charged and the system ready for a

quick resume to either the D1 or D0 state. The part will resume from the D2 state to the D0 state

within 2mS.

2.10. AFG D3

The D3-default state is available for HD Audio compliance. All converters are shut down. Port ampli-

fiers and references are active but in a low power state to prevent pops. Resume times may be lon-

ger than those from D2, but still less than 10mS to meet Intel low power goals. The default power

state for the Audio Function Group after power is applied is D3.

The traditional use for D3 was as a transitional state before power was removed (D3 cold) before the

system entered into standby, hibernate, or shut-down. To conserve power, Intel now promotes using

D3 whenever there are no active streams or other activity that requires the part to consume full

power. The system remains in S0 during this time. When a stream request or user activity requires

the CODEC to become active, the driver will immediately transition the CODEC from D3 to D0. To

enable this use model, the CODEC must resume within 10mS and not pop. Intel HDA ECR-15b /

Low Power White paper power goals are < 30mW when analog PC_Beep is not enabled, and <

60mW when analog PC_Beep is enabled.

While in AFG D3, the HD Audio controller may be in a D0 state (HD Audio bus active) or in a D3

state (HD Audio bus held in reset with no Bit_Clk, SData_Out, or Sync activity.) The expected behav-

ior is as follows (see the ECR15b section for more information):

Function

HDA Bus active

HDA Bus stopped

Port Presence Detect

state change

Unsolicited Response

Wake Event followed by

an unsolicited response

GPIO state change

Unsolicited Response

Wake Event followed by

an unsolicited response

2.10.1. AFG D3cold

The D3cold power state is the lowest power state available that does not use vendor specific verbs.

While in D3cold, the CODEC will still respond to bus requests to revert to a higher power state (dou-

ble AFG reset, link reset). However, audio processing, port presence detect, and other functions are

disabled. Per the HD Audio bus ECR 015b, the D3cold state is intended to be used just prior to

removing power to the CODEC. Typically, power will be removed within 200mS. However, the codec

may exit from the D3cold state by generating 2, back-to-back, AFG reset events. Resume time from

D3cold is less than 200mS.

2.11. Vendor Specific Function Group Power States D4/D5

The codec introduces vendor specific power states. A vendor defined verb is added to the Audio

Function Group that combines multiple vendor specific power control bits into logical power states

for use by the audio driver. The 2 states defined offer lower power than the 5 existing states defined

in the HD Audio specification and ECR15b. The Vendor Specific D4 state provides lower digital

power consumption relative to D3cold by disabling HD Audio link responses. Vendor specific D5 fur-

ther reduces power consumption on the digital supply by turning off GPIO drivers, and reduces ana-

log power consumption by turning off all analog circuitry except for reset circuits.

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States D4/D5 are not entered until D3cold has been requested so are actually D3cold options rather

than true, independent, power states. Software can pre-program the D4 or D5 state as a re-definition

of how the part will behave when the D3cold power state is requested or software may enter D3cold,

then set the D4 or D5 before performing the power state get command. The preferred method is to

request D3cold, then select D4 or D5 as desired.This will reduce the severity of pops encountered

when entering D4 or D5.

Both power states require a link reset or removal of DVDD to exit.

The CODEC may pop when using these verbs and transition times to an active state (D1 or D0 for

example) may take several seconds.

2.12. Low-voltage HDA Signaling

The codec is compatible with either 1.5V or 3.3V HDA bus signaling; in the 48QFP package the volt-

age selection is done dynamically based on the input voltage of DVDD_IO. For the 40-QFN pack-

age, seperate orderable part numbers to use 1.5V or 3.3V HDA bus signaling.

DVDD_IO is currently not a logic configuration pin, but rather provides the digital power supply to be

used for the HDA bus signals.

When in 1.5V mode, the codec can correctly decode BITCLK, SYNC, RESET# and SDO as they

operate at 1.5V; additionally it will drive SDI and SDO at 1.5V. None of the GPIOs are affected, as

they always function at their nominal voltage (DVDD or AVDD).

2.13. Multi-channel capture

The capability to assign multiple “ADC Converters” to the same stream is supported to meet the

microphone array requirements of Vista and future operating systems. Single converter streams are

still supported this is done by assigning unique non zero Stream IDs to each converter. All capture

devices (ADCs 0 and 1) may be used to create a multi-channel input stream. There are no restric-

tions regarding digital microphones.

The ADC Converters can be associated with a single stream as long the sample rate and the bits per

sample are the same. The assignment of converter to channel is done using the “CnvtrID” widget

and is restricted to even values. The ADC converters will always put out a stereo sample and there-

fore require 2 channels per converter.

The stream will not be generated unless all entries for the targeted converters are set identically, and

the total number of assigned converter channels matches the value in the NmbrChan field. These

are listed the “Multi-Converter Stream Critical Entries.” table.

An example of a 4 Channel Steam with ADC0 supplying channels 0&1 and ADC1 supplying chan-

nels 2 & 3 is shown below. A 4 Channel stream can be created by assigning the same non-zero

stream id “Strm= N” to both ADC0 and ADC1. The sample rates must be set the same and the num-

ber of channels must be set to 4 channels “NmbrChan = 0011”.

ADC1 CnvtrID

ADC0 CnvtrID

(NID = 0x08)

[3:0]

(NID = 0x07)

[3:0]

Ch = 2

Ch=0

Table 10. Example channel mapping

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Figure 3. Multi-channel capture

ADC0.CnvrtID.Channel = 0

ADC1.CnvrtID.Channel = 2

Data

Length

ADC0

Left Channel

ADC0

Right Channel

ADC1

Left Channel

ADC1

Right Channel

Stream ID

ADC0.CnvrtID.Channel = 2

ADC1.CnvrtID.Channel = 0

Data

Length

ADC1

Left Channel

ADC1

Right Channel

ADC0

Left Channel

ADC0

Right Channel

The following figure describes the bus waveform for a 24-bit, 48KHz capture stream with ID set to 1.

Figure 4. Multi-channel timing diagram

BITCLK

SDI

ADC0

L23

ADC0

L0

ADC0

R23

ADC0

R0

ADC1

L23

ADC1

L0

ADC1

R23

ADC1

R0

0

1

0

1

0

STREAM ID

DATA LENGTH

LEFT

RIGHT

LEFT

RIGHT

STREAM TAG

ADC0

ADC1

DATA BLOCK

ADC[1:0] Cnvtr

Bit Number

[15]

Sub Field Name

Description

StrmType

Stream Type (TYPE):

0: PCM

1: Non-PCM (not supported)

Sample Base Rate

0= 48kHz

[14]

FrmtSmplRate

SmplRateMultp

1=44.1KHz

[13:11]

Sample Base Rate Multiple

000=48kHz/44.1kHz or less

001= x2

010= x3 (not supported)

011= x4 192kHz only, 176.4 not supported

100-111= Reserved

[10:8]

SmplRateDiv

Sample Base Rate Divisor

000= Divide by 1

001= Divide by 2 (not supported)

010= Divide by 3 (not supported)

011= Divide by 4 (not supported)

100= Divide by 5 (not supported)

101= Divide by 6 (not supported)

110= Divide by 7 (not supported)

111= Divide by 8 (not supported)

Table 11: Mult-channel

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[6:4]

BitsPerSmpl

Bits per Sample

000= 8 bits (not supported)

001= 16 bits

010= 20 bits

011= 24 bits

100-111= Reserved

[3:0]

NmbrChan

Number of Channels

Number of channels for this stream in each “sample

block” of the “packets” in each “frame” on the link.

0000=1 channel (not supported)

0001 = 2 channels

…

1111= 16 channels.

[7:4]

[3:0]

Strm

Ch

Software-programmable integer representing link

stream ID used by the converter widget. By conven-

tion stream 0 is reserved as unused.

Integer representing lowest channel used by con-

verter.

0 and 2 are valid Entries

If assigned to the same stream, one ADC must be

assigned a value of 0 and the other ADC assigned a

value of 2.

Table 11: Mult-channel

2.14. Digital Microphone Support

The digital microphone interface permits connection of a digital microphone(s) to the CODEC via the

DMIC0 and DMIC_CLK 2-pin interface. The DMIC0 signal is an input that carries individual channels

of digital microphone data to the ADC. In the event that a single microphone is used, the data is

ported to both ADC channels. This mode is selected using a vendor specific verb and the left time

slot is copied to the ADC left and right inputs.

The DMIC_CLK output is controllable from 4.704Mhz, 3.528Mhz, 2.352Mhz, 1.176Mhz and is syn-

chronous to the internal master clock. The default frequency is 2.352Mhz.

The DMIC data input is reported as a stereo input pin widget that incorporates a boost amplifier. The

pin widget is shown connected to the ADCs through the same multiplexors as the analog ports.

Although the internal implementation is different between the analog ports and the digital micro-

phones, the functionality is the same. In most cases, the default values for the DMIC clock rate and

data sample phase will be appropriate and an audio driver will be able to configure and use the digi-

tal microphones exactly like an analog microphone.

To conserve power, the analog portion of the ADC will be turned off if the D-mic input is selected.

When switching from the digital microphone to an analog input to the ADC, the analog portion of the

ADC will be brought back to a full power state and allowed to stabilize before switching from the dig-

ital microphone to the analog input. This should take less than 10mS.

DMIC pin widgets support port presence detect directly using SENSE-C input on 4/5 DAC parts in a

48-pin package.

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The codec supports the following digital microphone configurations:

Digital Mics

0

Data Sample

N/A

ADC Conn.

N/A

Notes

No Digital Microphones

Available on either DMIC_0 or DMIC_1

When using a microphone that supports multiplexed operation (2-mics can share

a common data line), configure the microphone for “Left” and select mono

operation using the vendor specific verb.

1

2

3

Single Edge

0, or 1

“Left” D-mic data is used for ADC left and right channels.

Available on either DMIC_0 or DMIC_1, External logic required to support

sampling on a single Digital Mic pin channel on rising edge and second Digital Mic

right channel on falling edge of DMIC_CLK for those digital microphones that

don’t support alternative clock edge (multiplexed output) capability.

Double Edge on

either DMIC_0 or 1

Requires both DMIC_0 and DMIC_1, External logic required to support sampling

on a single Digital Mic pin channel on rising edge and second Digital Mic right

channel on falling edge of DMIC_CLK for those digital microphones that don’t

support alternative clock edge (multiplexed output) capability. Two ADC units are

required to support this configuration

Double Edge on

one DMIC pin and

Single Edge on the

second DMIC pin.

Connected to DMIC_0 and DMIC_1, External logic required to support sampling

on a single Digital Mic pin channel on rising edge and second Digital Mic right

channel on falling edge of DMIC_CLK for those digital microphones that don’t

support alternative clock edge capability. Two ADC units are required to support

this configuration

4

Double Edge

0, or 1

Table 12. Valid Digital Mic Configurations

Power State DMIC Widget

Enabled?

DMIC_CLK

Output

DMIC_0,1

Notes

DMIC_CLK Output is Enabled when either DMIC_0 or DMIC_1

Input Widget is Enabled. Otherwise, the DMIC_CLK remains Low

D0

Yes

Clock Capable

Input Capable

D1-D3

D0-D3

D4

Yes

No

-

Clock Disabled Input Disabled

DMIC_CLK is HIGH-Z with Weak Pull-down

D5

-

Table 13. DMIC_CLK and DMIC_0,1 Operation During Power State

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Figure 5. Single Digital Microphone (data is ported to both left and right channels

Off-Chip

On-Chip

Digital

Microphone

Single Line In

DMIC_0

Stereo Channels

Output

STEREO

ADC0 or 1

PCM

DMIC_CLK

On-Chip

Multiplexer

Single Microphone not supporting multiplexed output.

Valid Data

DMIC_0

Right

Left

Channel Channel

DMIC_CLK

Single “Left” Microphone, DMIC input set to mono input mode.

Valid Data

DMIC_0

Left & Right

Channel

DMIC_CLK

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Figure 6. Stereo Digital Microphone Configuration

Off-Chip

On-Chip

External

Multiplexer

Digital

On-Chip

Multiplexer

Microphones

DMIC_0

Stereo Channels

Output

STEREO

ADC0 or 1

PCM

DMIC_CLK

Valid

Data R

Valid

Data L

Valid

Data R

Valid

Data L

Valid

Data R

DMIC_0

Right

Left

Channel Channel

DMIC_CLK

Note: Some Digital Microphone Implementations support data on either edge, therefore, the

external mux may not be required.

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Figure 7. Quad Digital Microphone Configuration

Off-Chip

On-Chip

Digital

Microphones

External

Multiplexer

On-Chip

Multiplexer

Stereo Channels

Output For

DMIC_0

DMIC_0 L&R

STEREO

ADC0

PCM

DMIC_CLK

On-Chip

Multiplexer

Stereo Channels

Output For

DMIC_1 L&R

DMIC_1

STEREO

ADC1

PCM

External

Multiplexer

Digital

Microphones

Valid

Data R0

Data L0

Data R0

Data L0

Data R0

DMIC_0

Valid

Data R1

Data L1

Data R1

Data L1

Data R1

DMIC_1

Right

Left

Right

Left

Channel

Channel Channel Channel

DMIC_CLK

Note: Some Digital Microphone Implementations support data on either edge, in this case the

external multiplexer is not required.

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2.15. Analog PC-Beep

The codec supports automatic routing of the PC_Beep pin to several outputs when the HD-Link is in

reset. Codec will route PC_Beep to ports A, B, D, and F by default when reset is applied. To prevent

pops, beep is not enabled immediately when power is applied. Codec will mute outputs and wait until

reference and ampliers have stabalized before enabling beep pass thru after power on reset. To pre-

vent pops when removing power, automatic routing of PC_Beep is not supported in D3cold, D4, or

D5.

Analog PC-Beep may also be supported during HD-Link Reset if analog PC_Beep is manually

enabled before entering reset. Analog PC_Beep is mixed at the port and only ports enabled as out-

puts will pass PC_Beep.

PC-Beep may be attenuated and distorted when the CODEC is in D3 depending on the load imped-

ance seen by the output amplifier since all ports are in a low power state while in D3. Load imped-

ances of 10K or larger can support full scale outputs but lower impedance loads will distort unless

the output amplitude is reduced.

Analog PC_Beep is not supported in D3 Cold, or the vendor specific states D4/D5.

Analog PC_Beep is typically used during POST to route error beep codes to internal speakers for

diagnostic purposes. When using a legacy OS such as DOS, analog PC_Beep routes “Bell” and

“Alarm” tones from the south bridge to internal speakers or headphones. Keyboard controller “Key-

click” sounds are also routed to internal speakers using the analog beep function in both Windows

and legacy operating systems

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Analog PC_Beep Behavior - Boot

Vista or Linux

OS Loads

Bus Driver Loads

Power

POST (Firmware)

Reset#

Beep Enabled

Beep enabled by

Reset

Beep settings cleared by double

AFG reset and re-enabled if

desired

Beep enabled by

Firmware

Legacy OS

Power

POST (Firmware)

OS Loads

Reset#

Beep Enabled

Beep support persists until

reboot

Beep enabled by

Firmware

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Analog PC_Beep Behavior – D3 clockless

Vista or Linux

Bus Driver sets

controller to D0

Bit_Clk

Reset#

Beep Enabled

Bus Driver sets

controller to D3

due to inactivity

Beep enabled by

Driver

2.16. Digital PC-Beep

This block uses an 8-bit divider value to generate the PC beep from the 48kHz HD Audio Sync

pulse. The digital PC_Beep block generates the beep tone on all Pin Complexes that are currently

configured as outputs. The HD Audio spec states that the beep tone frequency = (48kHz HD Audio

SYNC rate) / (4*Divider), producing tones from 47 Hz to 12 kHz (logarithmic scale). Other audio

sources are disabled when digital PC_Beep is active.

It should be noted that digital PC Beep is disabled if the divider = 00h.

PC-Beep may be attenuated and distorted when the CODEC is in D3 depending on the load imped-

ance seen by the output amplifier since all ports are in a low power state while in D3. Load imped-

ances of 10K or larger can support full scale outputs but lower impedance loads will distort unless

the output amplitude is reduced. Digital PC_Beep requires a clock to operate and the CODEC will

prevent the system from stopping the bus clock while in D3 by setting the Clock_Stop_OK bit to 0 to

indicate that the part requires a clock.

2.17. Headphone Drivers

The codec implements headphone capable outputs on some ports. The Microsoft Windows Logo

Program allows up to the equivalent of 100ohms in series. However, an output level of +3dBV at the

pin is required to support 300mV at the jack with a 32ohm load and 1V with a 320 ohm load. Micro-

soft allows device and system manufactures to limit output voltages to address EU safety require-

ments. (WLP 3.09 - please refer to the latest Windows Logo Program requirements from Microsoft.)

Power limiting may be implemented through the use of an external series resistance.

Although 3 Headphone amplifiers are present, only two may be used simultaneously. Headphone

performance will degrade if more than one port is driving a 32 ohm load.

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2.18. EAPD

The EAPD pin (pin 47) also supports SPDIF_OUT, SPDIF_IN, and GPIO functions. The pin defaults

to EAPD after power on reset and will remain in EAPD mode until either GPIO is enabled for pin 47

or the port I/O is enabled as an input to support SPDIF_IN or an output to support SPDIF_OUT.

Although named External Amplifier Power Down (EAPD) by the HD Audio specification, this pin

operates as an external amplifier power up signal. The EAPD value is reflected on the EAPD pin; a 1

causes the external amplifier to power up (equivalent to D0), and a 0 causes it to power down

(equivalent to D3.) When the EAPD value = 1, the EAPD pin must be placed in a state appropriate to

the current power state of the associated Pin Widget even though the EAPD value (in the register)

may remain 1. The pin defaults to an open-drain configuration (an external pull-up is recommended.)

Per the HD Audio specification and ECR15b, multiple ports may control EAPD. The EAPD pin

assumes the highest power state of all the the EAPD bits in all of the pin complexes. The default

value of EAPD is 1 (powered on), but the FG power state will override and the pin will be low.

Vendor specific verbs are available to configure this pin. These verbs retain their values across link

and single function group resets but are set to their default values by power on reset:

MODE1

MODE0

EAPD Pin Function

Open Drain I/O

CMOS Output

CMOS Input

Description

0

1

0

1

0

1

Value at pin is wired-AND of EAPD bit and external signal. (default)

Value of EAPD bit in pin widget is forced at pin

External signal controls internal amps. EAPD bit in pin widget ignored

CMOS Input

Control Flag

Description

EAPD PIN

MODE 1:0

Defines if EAPD pin is used as input, output, or bi-directional port (Open Drain)

HP SD

0 = Amp controlled by EAPD pin only (default) / 1 = Amp controlled by power state (pin and FG) only

HP SD MODE 0 = Amp will mute when disabled. (default) / 1 = Amp will shut down (enter a low power state) when disabled

0 = AMP will power down (or mute) when EAPD pin is low (default) / 1 = Amp will power down (or mute) when EAPD

HP SD INV

pin is high.

HP SD

MODE

HP SD INV

EAPD Pin

State

Headphone Amp State

Amplifier is mute (default¹)

0

1

0

1

0

1

0

1

0

1

Amplifier is active

Amplifier is mute

Amplifier is in a low power state

Amplifier is active

Table 14. Headphone Amp Enable Configuration

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92HD89D

Eight channel HD Audio codec optimized for low power

HP SD

MODE

HP SD INV

EAPD Pin

State

Headphone Amp State

Amplifier is active

0

1

0

1

Amplifier is in a low power state

Amplifier follows pin/function group power stateand will

mute when disabled

1

0

1

NA

Amplifier follows pin/function group power state and will

enter a low power state when disabled

Table 14. Headphone Amp Enable Configuration

1.EAPD bit is set to one by default but the EAPD state is 0 after power-on reset because the function group

is not in D0. The state after a single or double function group reset will be compliant with ECR15b.

Note: NOTE: Each Headphone port has its own configuration bits for SD, SD MODE, and SD INV.

Analog

BEEP

EAPD Pin value¹

Description

enabled

Follows description in HD Audio spec. External

amplifier is shut down when pin or function group

power state is D2 or D3 independent of value in

EAPD bit.

Forced to low when in D2

or D3

0

1

Forced low in D2 or D3

Power state is ignored if port is enabled as output

unless port is enabled as and port EAPD=1 to allow PC_Beep support in D2

output and D3

Table 15. EAPD Analog PC_Beep behavior

1.When pin is enabled as Open Drain or CMOS output.

AFG

Power

State

Analog

PC_BEEP

Port Power

State

RESET#

Pin Behavior

Active high immediately after power on, otherwise the previous

state is retained across FG and link reset events

D0-D3

Asserted (Low)

Enabled¹

-

D0-D3

D0

Asserted (Low)

De-Asserted (High)

Disabled

-

The previous state is retained across FG and link reset events

Active - Pin reflects EAPD bit unless held low by external source.

Pin forced low to disable external amp

-

D1

-

D0-D1

D0-D2

D2

Disabled

Active - EAPD Pin high if any port EAPD bit =1 and that port also

enabled as output.

D2

D3

De-Asserted (High)

Enabled

Disabled

Enabled

D0-D2

D0-D3

Pin forced low to disable external amp

Active - EAPD Pin high if any port EAPD bit=1 and that port also

enabled as output.

D3cold

D4

De-Asserted (High)

-

Pin forced low to disable external amp

Pin Hi-Z (off)

D5

Table 16. EAPD Behavior

1.PC_Beep is automatically routed to ports A, B, D, and F after power-on reset while link reset is active and EAPD will be high

to enable an external amplifier. This may be disabled using a vendor specific verb. If the automatic beep path is disabled,

beep will still be supportedwith EAPD active in link reset if Analog Beep is manually enabled and at least one port is config-

ured as an output before entering link reset. If the automatic Beep routing is disabled and Analog Beep has not been man-

ually configured before entering link reset, then the EAPD pin will retain its current state.

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Eight channel HD Audio codec optimized for low power

Figure 8. HP EAPD Example to be replaced by single pin for internal amp

HP AUDIO CONTROL BLOCK DIAGRAM

SYNC FROM KBC TO OS

OS

SCAN

CODES

SYNC FROM AUDIO GUI TO KBC

A_EAPD

GPIO_1

MUTE +

UP/DOWN

BUTTONS

KBC

CODEC

A_SD

(MUTE LED ON

SAME BOARD)

SPKR_EN#

SPKR AMP

2.19. GPIO

2.19.1. GPIO Pin mapping and shared functions

SPDIF SPDIF

Pull

Up

Pull

Down

GPIO# 48 QFN 40 QFN Supply

EAPD

GPI/O

YES

VrefOut DMIC

In

Out

0

1

2

3

4

5

6

47

37

31

2

40

31

26

-

DVDD YES

AVDD

YES

50K 50K

YES

CLK

IN

AVDD

DVDD

50K

4

-

DVDD

40

30

-

AVDD

YES

-

AVDD

IN

Table 17. GPIO Pin mapping

2.19.2. SPDIF/GPIO Selection

2 functions are available on the SPDIFOUT1/GPIO5 pin. To determine which function is enabled, the

order of precedence is followed:

1. If GPIO for that pin is enabled, it will override the SPDIF_OUT function.

2. If the GPIOs are not enabled through the AFG, then at reset, the pin is pulled low by an internal

pull-down resistor.

3. If the port is enabled as an output, the SPDIF output will be used.

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Eight channel HD Audio codec optimized for low power

2.19.3. Digital Microphone/GPIO Selection

2 functions are available on the DMIC_CLK/GPIO3, the DMIC_0/GPIO4, and the DMIC_1/GPIO6

pins. To determine which function is enabled, the order of precedence is followed:

1. If GPIOs are not enabled through the AFG, then at reset, the pins are pulled low by an internal

pull-down resistor.

2. If the port is not enabled as an input or if the pin is configured as a GPIO, the digital microphone

path will be mute.

2.19.4. Vref_Out/GPIO Selection

2 functions are available on the VrefOut-A/GPIO1 and VrefOut-E/GPIO2 pins. To determine which

function is enabled, the order of precedence is followed:

1. If GPIO is enabled for that pin, it overrides the VrefOut function for that pin.

2. If the GPIO function is not enabled for that pin, then the VrefOut function is enabled and in its

programmed state.

2.19.5. EAPD/SPDIF_IN/SPDIF_OUT/GPIO0 Selection

4 functions are available on the EAPD/SPDIF_IN/SPDIF_OUT1/GPIO0 pin. To determine which

function is enabled, the order of precedence is followed:

1. Default at power-on is EAPD

2. If GPIO is enabled for that pin, it overrides the SPDIF_IN, SPDIF_OUT and EAPD functions for

that pin.

3. If the GPIO function is not enabled for that pin, then the SPDIF_IN or SPDIF_OUT function may

be enabled by setting the pin input or output enable to 1, respectively. (Setting input and output

enable to 1 at the same time will only enable SPDIF_IN)

2.20. HD Audio ECR 15b support

Although ECR15b is not yet complete (not a DCN), the 92HD89D will implement complete support

for the specification building on the support already present in previous products. ECR 15b features

supported are:

•

Persistence of many configuration options through bus and function group reset.

The ability to support port presence detect in D3 even when the HD Audio bus is in a low power

state (no clock.)

•

Fast resume times from low power states: 1ms D1 to D0, 2ms D2 to D0, 10mS D3 to D0.

Notification if persistent register settings have been unexpectedly reset.

SPDIF active in D3 (required)

The ability to notify the driver that a clock is necessary so entering D3 with the clock stopped is

not permissible.

2.21. Digital Core Voltage Regulator

The digital core operates fat 1.5V. Many systems require that the CODEC use a single 3.3V digital

supply, so an integrated regulator is included on die. The regulator uses pin 9, DVDD, as its voltage

source. The output of the LDO is connected to pin 1 and the digital core. A 10uF capacitor must be

placed on pin 1 for proper load regulation and regulator stability.

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Eight channel HD Audio codec optimized for low power

The digital core voltage regulator is only dependent on DVDD. DVDDIO may be either 3.3 or 1.5V

and may precede or follow DVDD in sequence. The CODEC digital logic and I/O (unless referenced

to AVDD) will operate in the absence of AVDD. DVDD and AVDD supply sequencing for the applica-

tion of power and the removal of power is neither defined nor guaranteed. It is common for desktop

systems to supply AVDD from the system standby supply and the CODEC will tolerate, indefinitely,

the condition where AVDD is active but DVDD and DVDDIO are inactive.

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92HD89D

Eight channel HD Audio codec optimized for low power

3. CHARACTERISTICS

3.1. Electrical Specifications

3.1.1.

Absolute Maximum Ratings

Stresses above the ratings listed below can cause permanent damage to the 92HD89D. These rat-

ings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional

operation of the device at these or any other conditions above those indicated in the operational sec-

tions of the specifications is not implied. Exposure to absolute maximum rating conditions for

extended periods can affect product reliability. Electrical parameters are guaranteed only over the

recommended operating temperature range.

Item

Maximum Rating

Analog maximum supply voltage

Digital maximum supply voltage

VREFOUT output current

AVdd

DVdd

6 Volts

5.5 Volts

5 mA

Voltage on any pin relative to ground

Operating temperature

Vss - 0.3 V to Vdd + 0.3 V

0 ^oC to +70 ^oC

Storage temperature

-55 ^oC to +125 ^oC

Soldering temperature information for all available in the package

section of this datasheet.

Soldering temperature

Table 18. Electrical Specification: Maximum Ratings

3.1.2.

Recommended Operating Conditions

Parameter

Min.

1.4

Typ.

Max.

1.98

Units

V

Power Supplies

DVDD_Core

DVDD_IO (3.3V signaling)

DVDD_IO (1.5V signaling)

Digital - 3.3 V

3.135

1.418

3.135

4.75

0

3.3

1.5

3.3

5

3.465

1.583

3.465

5.25

V

Power Supply Voltage

V

Analog - 5 V

V

Ambient Operating Temperature

Case Temperature

+70

C

T_case(48-QFN)

+95

Table 19. Recommended Operating Conditions

ESD: The 92HD89D is an ESD (electrostatic discharge) sensitive device. The human body and test equipment can

accumulate and discharge electrostatic charges up to 4000 Volts without detection. Even though the 92HD89D implements

internal ESD protection circuitry, proper ESD precautions should be followed to avoid damaging the functionality or

performance.

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Eight channel HD Audio codec optimized for low power

3.2. 92HD89D Analog Performance Characteristics

(Tambient = 25 ºC, AVdd = Supply ± 5%, DVdd = 3.3V ± 5%, AVss=DVss=0V; 20Hz to 20KHz swept

sinusoidal input; Sample Frequency = 48 kHz; 0 dB = 1 VRMS, 10K//50pF load, Testbench Char-

acterization BW: 20 Hz – 20 kHz, 0 dB settings on all gain stages)

Conditions

Parameter

Digital to Analog Converters

Resolution

Min

Typ

Max

Unit

24

97

99

85

99

85

99

85

Bits

dB

Dynamic Range¹: PCM to All Analog

Outputs

-60dB FS signal level, Analog Mixer disabled

Analog Mixer Disabled, PCM data

93

95

83

95

83

95

68

-

SNR²- DAC to All Line-Out Ports

THD+N³- DAC to All Line-Out Ports

dB

Analog Mixer Disabled, 0/-1/-3dB FS Signal,

PCM data

dBr

dB

SNR²- DAC to All Headphone Ports

THD+N³- DAC to All Headphone Ports

Analog Mixer Disabled, 10K load, PCM data

Analog Mixer Disabled, 0/-1/-3dB FS Signal,

dBr

dB

10K load, PCM data

SNR²- DAC to All Headphone Ports

THD+N³- DAC to All Headphone Ports

Analog Mixer Disabled, 32 load, PCM data

Analog Mixer Disabled, 0/-1/-3dB FS Signal,

dBr

32 load, PCM data

Any Analog Input (ADC) to DAC Crosstalk 10KHz Signal Frequency. 0dBV signal applied

to ADC, DACs idle, ports enabled as output.

-65

-95

-97

-

dB

Any Analog Input (ADC) to DAC Crosstalk

1KHz Signal Frequency

see above

DAC L/R crosstalk

Gain Error

DAC to LO or HP 20-15KHz into 10K load

DAC to HP 20-15KHz into 32 load

Analog Mixer Disabled

65

81

72

dB

Hz

0.5

Interchannel Gain Mismatch

Analog Mixer Disabled

.016

-

D/A Digital Filter Pass Band⁴

20

21,000

D/A Digital Filter Pass Band Ripple⁵

D/A Digital Filter Transition Band

D/A Digital Filter Stop Band

0.1

+/- dB

21,000

31,000

-100

-

31,000

Hz

dB

-

D/A Digital Filter Stop Band Rejection⁶

-108

D/A Out-of-Band Rejection⁷

Group Delay (48KHz sample rate)

Attenuation, Gain Step Size DIGITAL

DAC Offset Voltage

-55

-50

-

1

dB

ms

-

0.75

0.4

1

-

dB

20

10

mV

deg.

Deviation from Linear Phase

Analog Outputs

Full Scale All Mono/Line-Outs

DAC PCM Data

1.00

2.83

1.08

3.05

-

Vrms

Vp-p

Table 20. 92HD89D Analog Performance Characteristics

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92HD89D

Eight channel HD Audio codec optimized for low power

Conditions

Parameter

Min

Typ

Max

Unit

All Headphone Capable Outputs

mW

(peak)

32load

40

47

-

Amplifier output impedance

External load Capacitance

Mono/Line Outputs

Headphone Outputs

150

0.1

Ohms

pF

Mono/Line Outputs

Headphone Outputs

220

Analog inputs

Full Scale Input Voltage

0dB Boost @4.75V

(input voltage required for 0dB FS output)

1.05

1.31

-

Vrms

All Analog Inputs with boost

Boost Gain Accuracy

Input Impedance

10dB Boost

20dB Boost

30dB Boost

0.320

0.42

0.136

0.042

0.6

-

Vrms

dB

0.105

0.032

-

-2

-

2

-

75

K

Input Capacitance

-

15

-

pF

Analog Mixer

Dynamic Range: PCM to All Analog

Outputs

-60dB FS signal level Analog Beep enabled all

other mixer inputs mute

93

85

65

85

75

93

85

83

94

81

SNR²- All Line-Inputs to all Line Outputs

All inputs unmuted, single line input driven by

ATE.

dB

dBr

dB

THD+N³- All Line-Inputs to all Line

Outputs

0dB Full Scale Input on one input, all others

silent.

SNR²- DAC to All Ports

Analog Mixer Enabled, PCM data, all others

inputes mute.

THD+N³- DAC to All Line-Out Ports

THD+N³- DAC to All Ports

Analog Mixer Enabled, 0/-1/-3dB FS signal,

PCM data, all others inputes unmute/silent

dBr

Analog Mixer Enabled, 0dB FS Signal, PCM

data, all others inputes unmute/silent

65

-

78

dBr

dB

Attenuation, Gain Step Size ANALOG

Analog to Digital Converter

Resolution

1.5

-

24

1.31

94

Bits

dB

Full Scale Input Voltage

0dB Boost

(input voltage required to generate 0dBFS per

AES 17)

1.05

86

Dynamic Range¹, All Analog Inputs to A/D

Full Scale Input Voltage

High Pass Filer Enabled, -60dB FS, No boost

20dB Boost

(input voltage required to generate 0dBFS per 0.105

AES 17)

0.136

Dynamic Range¹, All Analog Inputs to A/D

20dB Boost

High Pass Filter Enabled, -60dB FS

81

90

94

80

SNR²- All Analog Inputs to A/D

THD+N³All Analog Inputs to A/D

High Pass Filter Enabled

86

78

High Pass Filter enabled, -1/-3dB FS signal

level

dB

Table 20. 92HD89D Analog Performance Characteristics

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V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

Conditions

Parameter

Min

Typ

Max

Unit

THD+N³All Analog Inputs to A/D

20dB Boost, High Pass Filter enabled,

-1/-3dB FS signal level

72

80

dB

Analog Frequency Response⁸

A/D Digital Filter Pass Band⁴

10

20

-

30,000

21,000

Hz

A/D Digital Filter Pass Band Ripple⁵

A/D Digital Filter Transition Band

A/D Digital Filter Stop Band

0.1

+/- dB

Hz

21,000

31,000

-100

-

31,000

-

-127

-

Hz

A/D Digital Filter Stop Band Rejection⁶

Group Delay

dB

48 KHz sample rate

1

ms

Any unselected analog Input to ADC

Crosstalk

10KHz Signal Frequency

-65

-94

-

dB

Any unselected analog Input to ADC

Crosstalk

1KHz Signal Frequency

-65

-

-94

-84

dB

ADC L/R crosstalk

Any selected input to ADC 20-15Khz

DAC to ADC crosstalk

DAC output 0dBFS. All outputs loaded. Input

to ADC open. 20-15Khz

-90

Spurious Tone Rejection⁹

-102

1.5

-

Attenuation, Gain Step Size

(analog)

-

Interchannel Gain Mismatch ADC

Power Supply

Power Supply Rejection Ratio

D0 Didd¹⁰

-

0.161

0.5

10kHz

1kHz

-

-60

-70

-

dB

3.3V, 1.8V, 1.5V

4.75V

22

mA

D0 Aidd¹⁰

60

D0 Didd¹¹

3.3V, 1.8V, 1.5V

4.75V

11.5

33

D0 Aidd¹¹

D1 Didd¹²

3.3V, 1.8V, 1.5V

4.75V

6.35

27.5

6.33

15

D1 Aidd¹²

D2 Didd

3.3V, 1.8V, 1.5V

4.75V

D2 Aidd

D3 (Beep enabled) Didd¹³

D3 (Beep enabled) Aidd¹³

D3 Didd¹³

3.3V, 1.8V, 1.5V

4.75V

1.84

5.74

1

3.3V, 1.8V, 1.5V

4.75V,

D3 Aidd¹³

2.78

0.4

D3cold Didd¹³

3.3V, 1.8V, 1.5V

4.75V

D3cold Aidd¹³

2.78

0.4

Vendor D4 Didd

Vendor D4 Aidd

3.3V, 1.8V, 1.5V

4.75V

2.78

Table 20. 92HD89D Analog Performance Characteristics

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V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

Conditions

Parameter

Min

Typ

0.4

Max

Unit

mA

Vendor D5 Didd

Vendor D5 Aidd

3.3V, 1.8V, 1.5V

4.75V

0.25

3.63

4.13

2.41

5.33

One Stereo ADC Didd

One Stereo ADC Aidd

One Stereo DAC Didd

One Stereo DAC Aidd

Voltage Reference Outputs

3.3V, 1.8V, 1.5V

4.75

3.3V, 1.8V, 1.5V

4.75V

VREFOut¹⁴

0.5 X

AVdd

-

V

mA

V

VREFOut Drive

VREFILT (VAG)

1.6

0.45 X

AVdd

Phased Locked Loop

PLL lock time

96

200

500

usec

psec

PLL (or HD Audio Bit CLK) 24MHz clock

jitter

150

ESD / Latchup

IEC1000-4-2

1

2

4

Level

Class

JESD22-A114-B

JESD22-C101

Table 20. 92HD89D Analog Performance Characteristics

1.Dynamic Range is the ratio of the full scale signal to the noise output with a -60dBFS signal as defined in AES17 as SNR in

the presence of signal and outlined in AES6id, measured “A weighted” over 20 Hz to 20 kHz bandwidth

2.Ratio of Full Scale signal to idle channel noise output is measured “A weighted” over a 20 Hz to a 20 kHz bandwidth.

(AES17-1991 Idle Channel Noise or EIAJ CP-307 Signal-to-noise Ratio).

3.THD+N ratio as defined in AES17 and outlined in AES6id,non-weighted, over 20 Hz to 20 kHz bandwidth.Results at the jack

are dependent on external components and will likely be 1 - 2dB worse.

4.Peak-to-Peak Ripple over Passband meets ± 0.125dB limits, 48 kHz or 44.1 kHz Sample Frequency. 1dB limit.

5.Peak-to-Peak Ripple over Passband meets ± 0.125dB limits, 48 kHz or 44.1 kHz Sample Frequency. 1dB limit.

6.Stop Band rejection determines filter requirements. Out-of-Band rejection determines audible noise.

7.The integrated Out-of-Band noise generated by the DAC process, during normal PCM audio playback, over a bandwidth 28.8

to 100 kHz, with respect to a 1 Vrms DAC output.

8.± 1dB limits for Line Output & 0 dB gain, at -20dBV

9.Spurious tone rejection is tested with ADC dither enabled and compared to ADC performance without dither.

10.All functions/converters active, pin complexes enabled, two FDX streams, line (10Kohm) loads. Add 24mA analog current per

stereo 32 ohm headphone.

11.One stereo DAC and corresponding pin widgets enabled (playback mode)

12.Mixer enabled

13.Idle measurement D3 set for minimum clicks/pops (biases and min. amps. on)

14.Can be set to 0.5 or 0.8 AVdd.

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92HD89D

Eight channel HD Audio codec optimized for low power

3.3. AC Timing Specs

3.3.1.

HD Audio Bus Timing

Parameter

Definition

Symbol

Min

Typ

Max

Units

23.99

76

24.00

24

BCLK Frequency

Average BCLK frequency

24.0

Mhz

BCLK Period

Period of BCLK including jitter

High phase of BCLK

Low phase of BCLK

BCLK jitter

Tcyc

T_high

T_low

41.163 41.67 42.171

ns

ps

BCLK High Phase

BCLK Low Phase

BCLK jitter

17.5

24.16

500

150

Time after rising edge of BCLK

that SDI becomes valid

SDI delay

SDO setup

SDO hold

T_tco

T_su

T_h

3

5

11

ns

Setup for SDO at both rising and

falling edges of BCLK

Hold for SDO at both rising and

falling edges of BCLK

Table 21. HD Audio Bus Timing

Figure 9. HD Audio Bus Timing

3.3.2.

SPDIF Timing

Parameter

Definition

Symbol

Min

Typ

Max

Units

highest rate of encoded signal

64 times the sample rate

SPDIF_OUT Frequency

2.8224

177.15

3.072

12.288

MHz

SPDIF_OUT unit interval

SPDIF_OUT jitter

1/(128 times the sample rate)

SPDIF_OUT jitter

UI

162.76

40.69

4.43

ns

Table 22. SPDIF Timing

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Eight channel HD Audio codec optimized for low power

Parameter

SPDIF_OUT rise time

SPDIF_OUT fall time

Definition

Symbol

T_rise

T_fall

Min

Typ

Max

15

Units

ns

15

ns

Table 22. SPDIF Timing

3.3.3.

Digital Microphone Timing

Parameter

Definition

Average DMIC_CLK frequency

Period of DMIC_CLK

DMIC_CLK jitter

Symbol

Min

Typ

Max

4.704

212.59

5000

Units

MHz

ns

DMIC_CLK Frequency

DMIC_CLK Period

DMIC_CLK jitter

1.176

850.34

2.352

425.17

Tdmic_cyc

ps

Setup for the microphone data at

both rising and falling edges of

DMIC_CLK

DMIC Data setup

DMIC Data hold

Tdmic_su

Tdmic_h

5

ns

Hold for the microphone data at

both rising and falling edges of

DMIC_CLK

Table 23. Digital Mic timing

3.3.4.

GPIO Characteristics

Parameter

Definition

Symbol

Min

Typ

Max

Units

input level at or above which a 1 is

reliably recorded

0.6 x

VDD

Input High Voltage

Input Low Voltage

Vih

V

input level at or below which a 0 is

reliably recorded

0.35 x

VDD

Vil

V

VDD may be DVDD or AVDD

iout = 4mA

VDD may be DVDD or AVDD

depending on pin

0.9 x

VDD

Output High Voltage

Voh

iout = -4mA

VDD may be DVDD or AVDD

depending on pin

0.1 x

VDD

Output Low Voltage

Input rise/fall time

Vol

V

transition time between 10% and

90% of supply

T_rise/T_fall

10

ns

Vin = VDD

VDD may be DVDD or AVDD

depending on pin (does not

include pull-up or pull-down

resistor if present)

Input/Tristate High

Leakage Current

0.5

-50

uA

Vin = 0

VDD may be DVDD or AVDD

depending on pin (does not

include pull-up or pull-down

resistor if present)

Input/Tristate Low Leakage

Current

Table 24. GPIO Characteristics

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Eight channel HD Audio codec optimized for low power

4. FUNCTIONAL BLOCK DIAGRAMS

4.1. 48QFP

Digital PC Beep

MixerOutVol

DAC0

DAC1

DAC2

DAC3

Analog Beep

EAPD/

SPDIF_IN /

SPDIF OUT1

Pin 47

SPDIF IN to

PCM OR

PCM to

SPDIF OUT

ADC0

ADC1

HP



No Bias

Stream &

Channel

Select

Digital

Mute

Boost

+0/+10/+20/+30 dB

Port D

PORT D

Pin Complex

Pins 35/36

ADC0

ADC1

PCM to

SPDIF OUT

SPDIF OUT1

Pin 40

Digital PC Beep

Analog Beep

Stream &

Channel

Select

Digital

Mute

MixerOutVol

DAC0

HP

ADC0

ADC1

DAC1

PCM to

Mic Bias

Stream &

Channel

Select

SPDIF OUT0

Pin 48

DAC2

Digital

Mute

SPDIF OUT

DAC3

Boost

+0/+10/+20/+30 dB

Port A

PORT A

Pin Complex

Pins 39/41

Digital PC Beep

Analog Beep

Stream &

Channel

Select

Digital

Mute

vol

DAC0

DAC1

DAC2

DAC3

DAC 0

DAC 1

DAC 2

DAC 3

MixerOutVol

DAC0

HP

DAC1

Mic Bias

DAC2

DAC3

Boost

+0/+10/+20/+30 dB

Port B

PORT B

Pin Complex

Pins 21/22

Stream &

Channel

Select

Digital

Mute

Digital PC Beep

Analog Beep

MixerOutVol

DAC0

LO

DAC1

Stream &

Channel

Select

Digital

Mute

Mic Bias

DAC2

DAC3

Boost

+0/+10/+20/+30 dB

Port C

PORT C

Pin Complex

Pins 23/24

Digital PC Beep

Analog Beep

Stream &

Channel

Select

Digital

Mute

MixerOutVol

DAC0

LO

DAC1

Mic Bias

DAC2

DAC3

Boost

+0/+10/+20/+30 dB

Port E

PORT E

Pin Complex

Pins 14/15

Digital PC Beep

Analog Beep

MixerOutVol

DAC0

Mixer

Port A

Port B

Port C

Port D

Port E

Port F

Port G

Port H

CD

LO

DAC1

No Bias

DAC2

DAC3

+0 to +22.5 dB

In 1.5 dB steps

Boost

+0/+10/+20/+30 dB

Port F

PORT F

Pin Complex

Pins 16/17

Stream &

Channel

Select

mute

vol

Gain

ADC0

Digital PC Beep

Analog Beep

MixerOutVol

DAC0

LO

DAC1

No Bias

DAC2

DAC3

Mixer

mute

vol

InMUX0

Boost

+0/+10/+20/+30 dB

Port G

PORT G

Pin Complex

Pins 43/44

MixerOut

Vol

vol

InMUX1

InMUX2

InMUX3

CD

Digital PC Beep

Analog Beep

mute

Vol



MixerOutVol

DAC0

DMIC0

DMIC1

LO

-46.5 to 0 dB

In 1.5 dB steps

DAC1

No Bias

-34.5 to +12 dB

In 1.5 dB steps

DAC2

DAC3

Boost

+0/+10/+20/+30 dB

Port H

PORT H

Pin Complex

Pins 45/46

Mixer

Port A

Port B

Port C

Port D

Port E

Port F

Port G

Port H

CD

To all ports

enabled as

output

mute

vol

Analog PC_BEEP

(Vendor Specific)

CD

Pin Complex

Pins 18/19/20

-6,-12,-18, -24 dB

Port A

Port B

Port D

Port F

Port A

Port E

Port G

Port H

+0 to +22.5 dB

In 1.5 dB steps

InMUX0

InMUX2

InMUX1

Stream &

Channel

Select

mute

vol

Gain

ADC1

Port B

Port C

Port G

Port H

DAC0

DAC1

DAC2

DAC3

DMIC0

DMIC1

InMUX3

+0/+10/+20/+30 dB

Boost

DMIC_0

DMIC

DMIC_0

Pin 4

Digital Microphone volume and mute is done

after the ADC but shown here and in widget list

as same as analog path.

Boost

DMIC_1

Pin 30

+0/+10/+20/+30 dB

Figure 10. 48QFP Functional Block Diagram

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V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

4.2. 40QFN

Digital PC Beep

MixerOutVol

Analog Beep

DAC0

DAC1

DAC2

DAC3

HP



EAPD/

No Bias

SPDIF IN to

Stream &

SPDIF_IN /

SPDIF OUT1

Pin 40

Digital

Mute

ADC0

ADC1

Boost

+0/+10/+20/+30 dB

Port D

Channel

Select

PORT D

Pin Complex

Pins 29/30

PCM OR

PCM to

SPDIF OUT

Digital PC Beep

Analog Beep

Stream &

Channel

Select

Digital

Mute

MixerOutVol

DAC0

HP

ADC0

ADC1

DAC1

PCM to

SPDIF OUT

Mic Bias

Stream &

Channel

Select

SPDIF OUT0

Pin 1

DAC2

Digital

Mute

DAC3

Boost

+0/+10/+20/+30 dB

Port A

PORT A

Pin Complex

Pins 33/34

Digital PC Beep

Analog Beep

Stream &

Channel

Select

Digital

Mute

vol

DAC0

DAC1

DAC2

DAC3

DAC 0

DAC 1

DAC 2

DAC 3

MixerOutVol

DAC0

HP

DAC1

Mic Bias

DAC2

DAC3

Boost

+0/+10/+20/+30 dB

Port B

PORT B

Pin Complex

Pins 18/19

Stream &

Channel

Select

Digital

Mute

Digital PC Beep

Analog Beep

MixerOutVol

DAC0

LO

DAC1

Stream &

Channel

Select

No Bias

Digital

Mute

DAC2

DAC3

Boost

+0/+10/+20/+30 dB

Port C

PORT C

Pin Complex

Pins 20/21

Digital PC Beep

Analog Beep

Stream &

Channel

Select

Digital

Mute

MixerOutVol

DAC0

LO

DAC1

Mic Bias

DAC2

DAC3

Boost

+0/+10/+20/+30 dB

Port E

PORT E

Pin Complex

Pins 11/12

Digital PC Beep

Analog Beep

MixerOutVol

DAC0

Mixer

Port A

Port B

Port C

Port D

Port E

Port F

Port G

Port H

CD

LO

DAC1

No Bias

DAC2

+0 to +22.5 dB

In 1.5 dB steps

DAC3

Boost

+0/+10/+20/+30 dB

Port F

PORT F

Pin Complex

Pins 13/14

Stream &

Channel

Select

mute

vol

Gain

ADC0

Digital PC Beep

Analog Beep

MixerOutVol

DAC0

LO

DAC1

No Bias

DAC2

DAC3

Mixer

mute

vol

InMUX0

Boost

+0/+10/+20/+30 dB

Port G

PORT G

Pin Complex

Pins 36/37

MixerOut

Vol

vol

InMUX1

InMUX2

InMUX3

CD

Digital PC Beep

Analog Beep

mute

Vol



MixerOutVol

DAC0

LO

-46.5 to 0 dB

In 1.5 dB steps

DAC1

No Bias

-34.5 to +12 dB

In 1.5 dB steps

DAC2

DAC3

Boost

+0/+10/+20/+30 dB

Port H

PORT H

Pin Complex

Pins 38/39

Mixer

Port A

Port B

Port C

Port D

Port E

Port F

Port G

Port H

CD

To all ports

enabled as

output

mute

vol

Analog PC_BEEP

(Vendor Specific)

CD

Pin Complex

Pins 15/16/17

-6,-12,-18, -24 dB

Port A

Port B

Port D

Port F

Port A

Port E

Port G

Port H

+0 to +22.5 dB

In 1.5 dB steps

InMUX0

InMUX2

InMUX1

Stream &

Channel

Select

mute

vol

Gain

ADC1

Port B

Port C

Port G

Port H

DAC0

DAC1

DAC2

DAC3

InMUX3

Figure 11. 40QFN Functional Block Diagram

46

V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

5. WIDGET INFORMATION AND SUPPORTED COMMAND VERBS

-95.25 to 0dB

NID = 0Ah

NID = 15h

0.75dB step

DAC0

DAC1

DAC2

DAC3

HP

NID = 1Fh

DAC0

Port A

DAC0

IN VOL

BIAS

VSW0

MIXER

Port A

10/20/30

-95.25 to 0dB

NID = 16h

0.75dB step

NID = 0Bh

DAC0

DAC1

DAC2

DAC3

DAC1

HP

DAC1

NID = 1Ch

Port B

IN VOL

BIAS

Digital

PC_BEEP

MIXER

Port B

10/20/30

-95.25 to 0dB

0.75dB step

NID = 17h

DAC2

NID = 0Ch

DAC2

DAC3

DAC0

DAC1

DAC2

DAC3

LO

Port C

IN VOL

BIAS

-95.25 to 0dB

0.75dB step

MixerOutVol

Port C

10/20/30

NID = 18h

DAC3

NID = 0Dh

DAC0

DAC1

DAC2

DAC3

HP

Port D

IN VOL

10/20/30

NID = 19h

VSW1

NID = 20h

MixerOutVol

Port D

Port A

Port B

Port C

Port D

Port E

Port F

Port G

Port H

CD

NID = 0Eh

DAC0

DAC1

DAC2

DAC3

ADC0

MUX

LO

NID = 1Ah

Port E

IN VOL

BIAS

0 to 22.5dB

1.5dB step

DMIC0

DMIC1

Mixer

MixerOutVol

Port E

10/20/30

ADC0

NID = 0Fh

ADC0 MUX

NID = 21h

DAC0

DAC1

DAC2

DAC3

LO

Port A

Port B

Port C

Port D

Port E

Port F

Port G

Port H

CD

HDA

Link

NID = 1Bh

ADC1

Port F

IN VOL

10/20/30

MixerOutVol

Port F

NID = 28h

ADC1

MUX

Port A

INPORT0

MUX

Port B

Port D

Port F

NID = 10h

0 to 22.5dB

1.5dB step

DMIC0

DMIC1

Mixer

DAC0

DAC1

DAC2

DAC3

LO

Port G

IN VOL

10/20/30

NID = 29h

ADC1 MUX

NID = 1Dh

MixerOutVol

Port G

Port A

Port E

Port G

Port H

INPORT1

MUX

NID = 11h

DAC0

DAC1

DAC2

DAC3

LO

Mute Volume

NID = 1Eh

Mixer

NID = 2Ah

Port H

IN VOL

10/20/30

MixerOut

Vol

MixerOutVol

Mute Volume

Port B

Port C

Port G

Port H

MixerOutVol

Port H

INPORT2

MUX



NID = 12h

Mute Volume

-34.5 to +12dB

in 1.5dB steps

CD

-46.5 to 0dB

in 1.5dB steps

NID = 2Bh

CD

(Port I)

Mixer

DAC 0

DAC 1

DAC 2

DAC 3

INPORT3

MUX

NID = 13h

NID = 22h

Dig0Pin

DMIC0

10/20/30

NID = 25h

ADC0 MUX

ADC1 MUX

SPDIF

OUT0

NID = 14h

NID = 23h

Dig1Pin

NID = 26h

ADC0 MUX

ADC1 MUX

DMIC1

10/20/30

SPDIF

OUT1

NID = 24h

Dig2Pin

To all

output

enabled

ports

ADC0 MUX

ADC1 MUX

Mute Volume

-6,-12,-18, -24 dB

PC_BEEP (Pin 12)

NID = 27h

VSV

SPDIF

IN

Figure 12. Widget Diagram (same for both package option)

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92HD89D

Eight channel HD Audio codec optimized for low power

6. PORT CONFIGURATIONS

Entertainment PC (default configuration)

Front

Rear

ADC1

DAC 0

HP

DAC 3

C

D

E

LI

A

B

G

F

CTR/LFE

DAC 2

DAC 1

MIC,LI

ADC0

REAR SURR

FRONT

40-pin package can support 2 SPDIF outputs

or 1 SPDIF output + 1 SPDIF input

48-pin package can support 2 SPDIF outputs + 1 SPDIF input

SPDIF_OUT

MIC

ADC1

CD in

SPDIF_IN

HDMI

Consumer Desktop

Front

Rear

5-Stack Option

ADC1/DAC3

LI / CTR-LFE

DAC0 / ADC0

DAC 3

C

D

E

A

G

F

HP / MIC,LI

CTR/LFE

DAC 2

DAC 1

ADC0 / DAC0

B

REAR SURR

FRONT

MIC,LI / HP

40-pin package can support 2 SPDIF outputs

or 1 SPDIF output + 1 SPDIF input

48-pin package can support 2 SPDIF outputs + 1 SPDIF input

SPDIF_OUT

ADC1/DAC2

MIC / REAR SURR

ADC1

CD in

SPDIF_IN

HDMI/Display Port

Mobile

Side

Dock

DAC 0

HP

DAC 1

A

B

E

D

HP

ADC 0

HP, LI

DAC 0

ADC 1

C

MIC (fixed Bias)

ADC 0

MIC, LI

DAC 3

G

CTR/LFE

DAC 2

F

HDMI/Display Port

REAR SURR

SPDIF_OUT

Internal

4 stereo DACs / 2 stereo ADCs, 8 ports UJ. 9 stereo ports

total. Two SPDIF outputs. 3 HEADPHONE PORTS

DAC output can be mixed with inputs for record or playback.

DAC 3

A

M

P

CD

H

OR

EAPD

Digital Mic

Array

Mic Array

Figure 13. Port Configurations

48

V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

6.1. Pin Configuration Default Register Settings

The following table shows the Pin Widget Configuration Default settings. Consumer Desktop 5-jack

implementation with 2 jacks in front and 5 or 6 jacks in rear. The front panel headphone and mic are

dedicated to RTC as suggested by Microsoft. SPDIF_OUT is implemented as an SPDIF optical out

jack and a second port as HDMI. SPDIF_In is implemented as an optical input. Digital Microphones

are listed as part of the muxed capture device.

Pin Name

Port

Location

Device

Connection

Color

Misc

Assoc. Seq

Jack

00b

Main Front

2h

HP Out

2h

1/8 inch Jack

1h

Green

4h

Jack Detect

Override=0

PortAPin

1h

2h

4h

3h

4h

3h

0h

Eh

2h

Jack

00b

Main Front

2h

Mic In

Ah

1/8 inch Jack

1h

Pink

9h

Jack Detect

Override=0

PortBPin

PortCPin

PortDPin

PortEPin

PortFPin

Jack

00b

Main Rear

1h

Line In

8h

1/8 inch Jack

1h

Blue

3h

Jack Detect

Override=0

Jack

00b

Main Rear

1h

Line Out

0h

1/8 inch Jack

1h

Green

4h

Jack Detect

Override=0

Jack

00b

Main Rear

1h

Mic In

Ah

1/8 inch Jack

1h

Pink

9h

Jack Detect

Override=0

Jack

00b

Main Rear

1h

Line Out

0h

1/8 inch Jack

1h

Black

1h

Jack Detect

Override=0

Jack

00b

Main Rear

1h

Line Out

0h

1/8 inch Jack

1h

Orange

6h

Jack Detect

Override=0

PortGPin

PortHPin

3h

1h

4h

Jack

00b

Main Rear

1h

Line Out

0h

1/8 inch Jack

1h

Gray

2h

Jack Detect

Override=0

Internal

10b

Internal

010000b

Mic In

Ah

ATAPI

3h

Unknown Jack Detect

4h

2h

DMIC0 (48pin)

DMIC0 (40pin)

DMIC1 (48pin)

DMIC1 (40pin)

Dig0Pin

0h

Override=1

NA

4h

NA

3h

Internal

10b

Internal

010000b

Mic In

Ah

ATAPI

3h

Unknown Jack Detect

0h

Override=1

NA

5h

6h

NA

0h

Jack

00b

Main Rear

000001b

SPDIF Out

4h

optical

5h

Black

1h

Jack Detect

Override=1

DIG1pin(48pin)

Internal

10b

Internal

011000b

Dig Other

Out

Other Digital

6h

Unknown Jack Detect

0h

Override=1

5h

DIG1pin(40pin)

Dig2Pin

NA

7h

NA

0h

Jack

00b

Main Rear

000001b

SPDIF IN

Ch

optical

5h

Gray

2h

Jack Detect

Override=1

Internal

10b

Int ATAPI

011001b

CD

3h

ATAPI

3h

Unknown Jack Detect

0h Override=0

CDPin

4h

1h

Table 25. Pin Configuration Default Settings

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V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

7. WIDGET INFORMATION

Bits [39:32]

Bits [31:28]

BITS [27:20]

BITS[19:16]

BITS [15:0]

Reserved

CODEC Address

NID

Verb ID (4-bit)

Payload Data (16-bit)

Table 26. Command Format for Verb with 4-bit Identifier

Bits [39:32]

Bits [31:28]

BITS [27:20]

BITS[19:8]

BITS [7:0]

Payload Data (8-bit)

Reserved

CODEC Address

NID

Verb ID (12-bit)

Table 27. Command Format for Verb with 12-bit Identifier

There are two types of responses: Solicited and Unsolicited. Solicited responses are provided as a

direct response to an issued command and will be provided in the frame immediately following the

command. Unsolicited responses are provided by the CODEC independent of any command. Unso-

licited responses are the result of CODEC events such as a jack insertion detection. The formats for

Solicited Responses and Unsolicited Responses are shown in the tables below. The “Tag” field in

bits [31:28] of the Unsolicited Response identify the event.

Bit [35]

Bit [34]

BITS [33:32]

Reserved

BITS[31:0]

Valid (Valid = 1)

UnSol = 0

Response

Table 28. Solicited Response Format

Bit [35]

Bit [34]

BITS [33:32]

BITS[31:28]

Tag

BITS [27:0]

Response

Valid (Valid = 1)

UnSol = 1

Reserved

Table 29. Unsolicited Response Format

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V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

7.1. Widget List

ID

Widget Name

Root

Description

Root Node

00h

01h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

25h

26h

27h

28h

29h

2Ah

AFG

Audio Function Group

Port A Pin Widget

Port A

Port B

Port B Pin Widget

Port C

Port C Pin Widget

Port D

Port D Pin Widget

Port E

Port E Pin Widget

Port F

Port F Pin Widget

Port G

Port G Widget

Port H

Port H Pin Widget

CD

CD input

DigMic0

DigMic1

DAC0

Digital Microphone Pin Widget (48pin only, Rsvd in 40pin)

DAC

DAC1

DAC

DAC2

DAC

DAC3

DAC

DAC4

DAC

ADC0

ADC

ADC1

ADC

PCBeep

Mixer

Digital PC Beep Widget

Input Mixer (Input Ports, DACs, Analog PC_Beep)

Volume control for analog mixer

Vendor Specific Widget

ADC Mux with volume and mute

Digital I/O Pin

MixerOutVol

VSW

ADC0Mux

ADC1Mux

Dig0Pin

Dig1Pin

Dig2Pin

SPDIFOut0

SPDIFOut1

SPDIFIN

InPort0Mux

InPort1Mux

InPort2Mux

Digital I/O Pin (48pin only, Rsvd in 40pin)

Digital I/O Pin

Stereo Output for SPDIF_Out

SPDIF Input

Input port pre-select for mixer

Table 30. Widget List

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V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

ID

Widget Name

Description

2Bh

InPort3Mux

Input port pre-select for mixer

Table 30. Widget List

7.2. Root (NID = 00h): VendorID

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0000h

Field Name

Bits

R/W

Default

Reset

Vendor

31:16

R

111Dh

N/A

Vendor ID.

15:8

DeviceFix

R

see table

below

N/A

Device ID.

7:0

DeviceProg

see table

below

Device ID.

Device

Device ID

Package

HD Audio Bus Voltage

92HD89D3

92HD89D2

92HD89D1

76C9h

76CAh

76CBh

48QFP

40QFN

DVDDIO selectable

3.3V‘

1.5V

52

V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

7.3. Root (NID = 00h): RevID

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0002h

Field Name

Bits

R/W

Default

Reset

Rsvd

31:24

R

00h

N/A (Hard-coded)

Reserved.

23:20

Major

R

1h

N/A (Hard-coded)

Major rev number of compliant HD Audio spec.

19:16 0h N/A (Hard-coded)

Minor rev number of compliant HD Audio spec.

15:12 xh

Vendor's rev number for this device.

11:8 xh

Vendor's rev number for this device.

7:4 xh

Vendor stepping number within the Vendor RevID.

3:0 xh N/A (Hard-coded)

Vendor stepping number within the Vendor RevID.

Minor

R

RevisionFix

RevisionProg

SteppingFix

SteppingProg

R

N/A (Hard-coded)

R

7.3.1.

Root (NID = 00h): NodeInfo

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0004h

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V1.1 06/11

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:24

R

00h

N/A (Hard-coded)

Reserved.

23:16

StartNID

Rsvd1

R

01h

N/A (Hard-coded)

Starting node number (NID) of first function group

15:8

R

00h

01h

N/A (Hard-coded)

Reserved.

7:0

TotalNodes

R

Total number of nodes

7.4. AFG (NID = 01h): NodeInfo

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0004h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:24

R

00h

N/A (Hard-coded)

Reserved.

23:16

StartNID

Rsvd1

R

0Ah

N/A (Hard-coded)

Starting node number for function group subordinate nodes.

15:8

R

00h

N/A (Hard-coded)

Reserved.

7:0

TotalNodes

R

22h

Total number of nodes.

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Eight channel HD Audio codec optimized for low power

7.4.1.

AFG (NID = 01h): FGType

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0005h

Field Name

Bits

R/W

Default

Reset

Rsvd

31:9

R

000000h

N/A (Hard-coded)

Reserved.

8

UnSol

R

1h

N/A (Hard-coded)

Unsolicited response supported: 1 = yes, 0 = no.

7:0 1h N/A (Hard-coded)

NodeType

R

Function group type:

00h = Reserved

01h = Audio Function Group

02h = Vendor Defined Modem Function Group

03h-7Fh = Reserved

80h-FFh = Vendor Defined Function Group

7.4.2.

AFG (NID = 01h): AFGCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0008h

Field Name

Bits

R/W

Default

Reset

Rsvd3

31:17

Reserved.

16

R

00h

N/A (Hard-coded)

BeepGen

R

1h

N/A (Hard-coded)

Beep generator present: 1 = yes, 0 = no.

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

Rsvd2

15:12

Reserved.

11:8

R

0h

N/A (Hard-coded)

InputDelay

R

Dh

N/A (Hard-coded)

Typical latency in frames. Number of samples between when the sample is re-

ceived as an analog signal at the pin and when the digital representation is

transmitted on the HD Audio link.

Rsvd1

7:4

R

0h

N/A (Hard-coded)

Reserved.

3:0

OutputDelay

R

Dh

N/A (Hard-coded)

Typical latency in frames. Number of samples between when the signal is re-

ceived from the HD Audio link and when it appears as an analog signal at the

pin.

7.4.3.

AFG (NID = 01h): PCMCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Ah

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:21

Reserved.

20

R

000h

N/A (Hard-coded)

B32

B24

B20

R

0h

32 bit audio format support: 1 = yes, 0 = no.

19 1h

24 bit audio format support: 1 = yes, 0 = no.

18 1h

R

20 bit audio format support: 1 = yes, 0 = no.

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Field Name

Bits

R/W

Default

Reset

B16

17

R

1h

N/A (Hard-coded)

16 bit audio format support: 1 = yes, 0 = no.

16 0h

8 bit audio format support: 1 = yes, 0 = no.

B8

R

N/A (Hard-coded)

Rsvd1

R12

R11

R10

R9

15:12

Reserved.

11

R

0h

R

0h

384kHz rate support: 1 = yes, 0 = no.

10 1h

192kHz rate support: 1 = yes, 0 = no.

0h

176.4kHz rate support: 1 = yes, 0 = no.

1h

96kHz rate support: 1 = yes, 0 = no.

1h

88.2kHz rate support: 1 = yes, 0 = no.

1h

48kHz rate support: 1 = yes, 0 = no.

1h

44.1kHz rate support: 1 = yes, 0 = no.

0h

32kHz rate support: 1 = yes, 0 = no.

0h

22.05kHz rate support: 1 = yes, 0 = no.

0h

R

9

R

8

R

R8

7

R

R7

6

R

R6

5

R

R5

4

R

R4

3

R

R3

2

R

16kHz rate support: 1 = yes, 0 = no.

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Field Name

Bits

R/W

Default

Reset

R2

1

R

0h

N/A (Hard-coded)

11.025kHz rate support: 1 = yes, 0 = no.

0h

8kHz rate support: 1 = yes, 0 = no.

R1

0

R

N/A (Hard-coded)

7.4.4.

AFG (NID = 01h): StreamCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Bh

Field Name

Bits

R/W

Default

Reset

Rsvd

31:3

R

00000000h

N/A (Hard-coded)

Reserved.

2

AC3

R

0h

N/A (Hard-coded)

AC-3 formatted data support: 1 = yes, 0 = no.

0h

Float32 formatted data support: 1 = yes, 0 = no.

1h N/A (Hard-coded)

PCM-formatted data support: 1 = yes, 0 = no.

Float32

PCM

1

R

0

R

7.4.5.

AFG (NID = 01h): InAmpCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Dh

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Field Name

Bits

R/W

Default

Reset

Mute

31

R

0h

N/A (Hard-coded)

Mute support: 1 = yes, 0 = no.

Rsvd3

30:23

R

00h

N/A (Hard-coded)

Reserved.

22:16

StepSize

Rsvd2

R

27h

Size of each step in the gain range: 0 to 127 = .25dB to 32dB, in .25dB steps.

15

R

0h

N/A (Hard-coded)

Reserved.

14:8

NumSteps

Rsvd1

R

03h

N/A (Hard-coded)

Number of gains steps (number of possible settings - 1).

7

R

0h

N/A (Hard-coded)

Reserved.

6:0

Offset

R

00h

N/A (Hard-coded)

Indicates which step is 0dB

7.4.6.

AFG (NID = 01h): PwrStateCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Fh

Field Name

Bits

R/W

Default

1h

Reset

EPSS

31

R

N/A (Hard-coded)

Extended power states support: 1 = yes, 0 = no.

30 1h N/A (Hard-coded)

ClkStop

R

D3 clock stop support: 1 = yes, 0 = no.

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Field Name

Bits

R/W

Default

Reset

LPD3Sup

29

R

1h

N/A (Hard-coded)

Codec state intended during system S3 state: 0 = D3Hot, 1 = D3Cold

Rsvd

28:5

R

000000h

N/A (Hard-coded)

Reserved.

4

D3ColdSup

D3Sup

D2Sup

D1Sup

D0Sup

R

1h

D3Cold power state support: 1 = yes, 0 = no.

1h

D3 power state support: 1 = yes, 0 = no.

1h

D2 power state support: 1 = yes, 0 = no.

1h

D1 power state support: 1 = yes, 0 = no.

1h

D0 power state support: 1 = yes, 0 = no.

3

R

2

R

1

R

0

R

7.4.7.

AFG (NID = 01h): GPIOCnt

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0011h

Field Name

Bits

R/W

Default

Reset

GPIWake

31

R

1h

N/A (Hard-coded)

Wake capability. Assuming the Wake Enable Mask controls are enabled,

GPIO's configured as inputs can cause a wake (generate a Status Change

event on the link) when there is a change in level on the pin.

GPIUnsol

Rsvd

30

R

1h

N/A (Hard-coded)

GPIO unsolicited response support: 1 = yes, 0 = no.

29:24

R

00h

N/A (Hard-coded)

Reserved.

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Field Name

Bits

R/W

Default

Reset

NumGPIs

23:16

R

00h

N/A (Hard-coded)

Number of GPI pins supported by function group.

15:8 00h N/A (Hard-coded)

Number of GPO pins supported by function group.

NumGPOs

NumGPIOs

R

7:0

R

48QFN=07h

40QFN=03h

N/A (Hard-coded)

Number of GPIO pins supported by function group. Note different default by

package options.

7.4.8.

AFG (NID = 01h): OutAmpCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0012h

Field Name

Bits

R/W

Default

Reset

Mute

31

R

1h

N/A (Hard-coded)

Mute support: 1 = yes, 0 = no.

Rsvd3

30:23

R

00h

Reserved.

22:16

StepSize

Rsvd2

R

02h

Size of each step in the gain range: 0 to 127 = .25dB to 32dB, in .25dB steps.

15

R

0h

N/A (Hard-coded)

Reserved.

14:8

NumSteps

Rsvd1

R

7Fh

N/A (Hard-coded)

Number of gains steps (number of possible settings - 1).

7

R

0h

N/A (Hard-coded)

Reserved.

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Field Name

Bits

R/W

Default

Reset

Offset

6:0

R

7Fh

N/A (Hard-coded)

Indicates which step is 0dB

7.4.9.

AFG (NID = 01h): PwrState

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

705h

Get

F0500h

Field Name

Bits

R/W

Default

Reset

Rsvd3

31:11

Reserved.

10

R

000000h

N/A (Hard-coded)

SettingsReset

R

1h

POR - DAFG - ULR

Indicates if any persistent settings in this Function Group have been reset.

Cleared by PwrState 'Get' to this Widget.

ClkStopOK

Error

9

R

1h

Bit clock can currently be removed: 1 = yes, 0 = no.

0h POR - DAFG - ULR

POR - DAFG - ULR

8

R

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

Rsvd2

Act

7

R

0h

N/A (Hard-coded)

POR - DAFG - LR

N/A (Hard-coded)

POR - DAFG - LR

Reserved.

6:4

R

3h

Actual power state of this widget.

Rsvd1

Set

3

R

0h

Reserved.

2:0

RW

3h

Current power state setting for this widget.

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7.4.10. AFG (NID = 01h): UnsolResp

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

708h

Get

F0800h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

En

RW

0h

POR - DAFG - ULR

Unsolicited response enable: 1 = enabled, 0 = disabled.

Rsvd1

Tag

6

R

0h

N/A (Hard-coded)

Reserved.

5:0

RW

00h

POR - DAFG - ULR

Software programmable field returned in top six bits (31:26) of every Unsolicit-

ed Response generated by this node.

7.4.11. AFG (NID = 01h): GPIO

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

715h

Get

F1500h

Please note that the 40QFN package version only supports GPIO0, GPIO1 and GPIO2.

Field Name

Bits

R/W

Default

Reset

Rsvd

31:7

R

00000000h

N/A (Hard-coded)

Reserved.

6

Data6

RW

0h

POR-DAFG-ULR

Data for GPIO6. If this GPIO bit is configured as Sticky (edge-sensitive) imput,

it can be cleared by writing “0”. For details of read back value, refer to HD Audio

spec. section 7.3.3.22.

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Field Name

Bits

R/W

Default

Reset

Data5

5

RW

0h

POR-DAFG-ULR

Data for GPIO5. If this GPIO bit is configured as Sticky (edge-sensitive) imput,

it can be cleared by writing “0”. For details of read back value, refer to HD Audio

spec. section 7.3.3.22.

Data4

Data3

Data2

Data1

Data0

4

RW

0h

POR-DAFG-ULR

Data for GPIO4. If this GPIO bit is configured as Sticky (edge-sensitive) imput,

it can be cleared by writing “0”. For details of read back value, refer to HD Audio

spec. section 7.3.3.22.

3

RW

0h

POR-DAFG-ULR

Data for GPIO3. If this GPIO bit is configured as Sticky (edge-sensitive) imput,

it can be cleared by writing “0”. For details of read back value, refer to HD Audio

spec. section 7.3.3.22.

2

RW

0h

POR - DAFG - ULR

Data for GPIO2. If this GPIO bit is configured as Sticky (edge-sensitive) input,

it can be cleared by writing "0". For details of read back value, refer to HD Audio

spec. section 7.3.3.22.

1

RW

0h

POR - DAFG - ULR

Data for GPIO1. If this GPIO bit is configured as Sticky (edge-sensitive) input,

it can be cleared by writing "0". For details of read back value, refer to HD Audio

spec. section 7.3.3.22.

0

RW

0h

POR - DAFG - ULR

Data for GPIO0. If this GPIO bit is configured as Sticky (edge-sensitive) input,

it can be cleared by writing "0". For details of read back value, refer to HD Audio

spec. section 7.3.3.22.

7.4.12. AFG (NID = 01h): GPIOEn

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

716h

Get

F1600h

Please note that the 40QFN package version only supports GPIO0, GPIO1 and GPIO2.

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Field Name

Bits

R/W

Default

Reset

Rsvd

31:7

R

00000000h

N/A (Hard-coded)

Reserved.

6

Mask6

Mask5

Mask4

Mask3

Mask2

Mask1

Mask0

RW

0h

POR - DAFG - ULR

Enable for GPIO6: 0 = pin is disabled (Hi-Z state); 1 = pin is enabled; behavior

determined by GPIO Direction control.

5

RW

0h

POR - DAFG - ULR

Enable for GPIO5: 0 = pin is disabled (Hi-Z state); 1 = pin is enabled; behavior

determined by GPIO Direction control.

4

RW

0h

POR - DAFG - ULR

Enable for GPIO4: 0 = pin is disabled (Hi-Z state); 1 = pin is enabled; behavior

determined by GPIO Direction control.

3

RW

0h

POR - DAFG - ULR

Enable for GPIO3: 0 = pin is disabled (Hi-Z state); 1 = pin is enabled; behavior

determined by GPIO Direction control.

2

RW

0h

POR - DAFG - ULR

Enable for GPIO2: 0 = pin is disabled (Hi-Z state); 1 = pin is enabled; behavior

determined by GPIO Direction control.

1

RW

0h

POR - DAFG - ULR

Enable for GPIO1: 0 = pin is disabled (Hi-Z state); 1 = pin is enabled; behavior

determined by GPIO Direction control.

0

RW

0h

POR - DAFG - ULR

Enable for GPIO0: 0 = pin is disabled (Hi-Z state); 1 = pin is enabled; behavior

determined by GPIO Direction control.

7.4.13. AFG (NID = 01h): GPIODir

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

717h

Get

F1700h

Please note that the 40QFN package version only supports GPIO0, GPIO1 and GPIO2.

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Field Name

Bits

R/W

Default

Reset

Rsvd

31:7

R

00000000h

N/A (Hard-coded)

Reserved.

6

Control6

Control5

Control4

Control3

Control2

Control1

Control0

RW

0h

POR - DAFG - ULR

Direction control for GPIO6: 0 = GPIO is configured as input; 1 = GPIO is con-

figured as output.

5

RW

0h

POR - DAFG - ULR

Direction control for GPIO5: 0 = GPIO is configured as input; 1 = GPIO is con-

figured as output.

4

RW

0h

POR - DAFG - ULR

Direction control for GPIO4: 0 = GPIO is configured as input; 1 = GPIO is con-

figured as output.

3

RW

0h

POR - DAFG - ULR

Direction control for GPIO3: 0 = GPIO is configured as input; 1 = GPIO is con-

figured as output.

2

RW

0h

POR - DAFG - ULR

Direction control for GPIO2: 0 = GPIO is configured as input; 1 = GPIO is con-

figured as output.

1

RW

0h

POR - DAFG - ULR

Direction control for GPIO1: 0 = GPIO is configured as input; 1 = GPIO is con-

figured as output.

0

RW

0h

POR - DAFG - ULR

Direction control for GPIO0: 0 = GPIO is configured as input; 1 = GPIO is con-

figured as output.

7.4.14. AFG (NID = 01h): GPIOWakeEn

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

718h

Get

F1800h

Please note that the 40QFN package version only supports GPIO0, GPIO1 and GPIO2.

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Field Name

Bits

R/W

Default

Reset

Rsvd

31:7

R

00000000h

N/A (Hard-coded)

Reserved.

6

W6

W5

W4

W3

W2

W1

W0

RW

0h

POR - DAFG - ULR

Wake enable for GPIO6: 0 = wake-up event is disabled; 1 = When HD Audio

link is powered down (RST# is asserted), a wake-up event will trigger a Status

Change Request event on the link.

5

RW

0h

POR - DAFG - ULR

Wake enable for GPIO5: 0 = wake-up event is disabled; 1 = When HD Audio

link is powered down (RST# is asserted), a wake-up event will trigger a Status

Change Request event on the link.

4

RW

0h

POR - DAFG - ULR

Wake enable for GPIO4: 0 = wake-up event is disabled; 1 = When HD Audio

link is powered down (RST# is asserted), a wake-up event will trigger a Status

Change Request event on the link.

3

RW

0h

POR - DAFG - ULR

Wake enable for GPIO3: 0 = wake-up event is disabled; 1 = When HD Audio

link is powered down (RST# is asserted), a wake-up event will trigger a Status

Change Request event on the link.

2

RW

0h

POR - DAFG - ULR

Wake enable for GPIO2: 0 = wake-up event is disabled; 1 = When HD Audio

link is powered down (RST# is asserted), a wake-up event will trigger a Status

Change Request event on the link.

1

RW

0h

POR - DAFG - ULR

Wake enable for GPIO1: 0 = wake-up event is disabled; 1 = When HD Audio

link is powered down (RST# is asserted), a wake-up event will trigger a Status

Change Request event on the link.

0

RW

0h

POR - DAFG - ULR

Wake enable for GPIO0: 0 = wake-up event is disabled; 1 = When HD Audio

link is powered down (RST# is asserted), a wake-up event will trigger a Status

Change Request event on the link.

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7.4.15. AFG (NID = 01h): GPIOUnsol

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

719h

Get

F1900h

Please note that the 40QFN package version only supports GPIO0, GPIO1 and GPIO2.

Field Name

Bits

R/W

Default

Reset

Rsvd

31:7

R

00000000h

N/A (Hard-coded)

Reserved.

6

EnMask6

EnMask5

EnMask4

EnMask3

EnMask2

EnMask1

RW

0h

POR - DAFG - ULR

Unsolicited enable mask for GPIO6. If set, and the Unsolicited Response con-

trol for this widget has been enabled, an unsolicited response will be sent when

GPIO2 is configured as input and changes state.

5

RW

0h

POR - DAFG - ULR

Unsolicited enable mask for GPIO5. If set, and the Unsolicited Response con-

trol for this widget has been enabled, an unsolicited response will be sent when

GPIO2 is configured as input and changes state.

4

RW

0h

POR - DAFG - ULR

Unsolicited enable mask for GPIO4. If set, and the Unsolicited Response con-

trol for this widget has been enabled, an unsolicited response will be sent when

GPIO2 is configured as input and changes state.

3

RW

0h

POR - DAFG - ULR

Unsolicited enable mask for GPIO3. If set, and the Unsolicited Response con-

trol for this widget has been enabled, an unsolicited response will be sent when

GPIO2 is configured as input and changes state.

2

RW

0h

POR - DAFG - ULR

Unsolicited enable mask for GPIO2. If set, and the Unsolicited Response con-

trol for this widget has been enabled, an unsolicited response will be sent when

GPIO2 is configured as input and changes state.

1

RW

0h

POR - DAFG - ULR

Unsolicited enable mask for GPIO1. If set, and the Unsolicited Response con-

trol for this widget has been enabled, an unsolicited response will be sent when

GPIO1 is configured as input and changes state.

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Field Name

Bits

R/W

Default

Reset

EnMask0

0

RW

0h

POR - DAFG - ULR

Unsolicited enable mask for GPIO0. If set, and the Unsolicited Response con-

trol for this widget has been enabled, an unsolicited response will be sent when

GPIO0 is configured as input and changes state.

7.4.16. AFG (NID = 01h): GPIOSticky

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

71Ah

Get

F1A00h

Please note that the 40QFN package version only supports GPIO0, GPIO1 and GPIO2.

Field Name

Bits

R/W

Default

Reset

Rsvd

31:7

R

00000000h

N/A (Hard-coded)

Reserved.

6

Mask6

Mask5

Mask4

Mask3

Mask2

RW

0h

POR - DAFG - ULR

GPIO6 input type (when configured as input): 0 = Non-Sticky (level-sensitive);

1 = Sticky (edge-sensitive).

5

RW

0h

POR - DAFG - ULR

GPIO5input type (when configured as input): 0 = Non-Sticky (level-sensitive);

1 = Sticky (edge-sensitive).

4

RW

0h

POR - DAFG - ULR

GPIO4 input type (when configured as input): 0 = Non-Sticky (level-sensitive);

1 = Sticky (edge-sensitive).

3

RW

0h

POR - DAFG - ULR

GPIO3 input type (when configured as input): 0 = Non-Sticky (level-sensitive);

1 = Sticky (edge-sensitive).

2

RW

0h

POR - DAFG - ULR

GPIO2 input type (when configured as input): 0 = Non-Sticky (level-sensitive);

1 = Sticky (edge-sensitive).

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Field Name

Bits

R/W

Default

Reset

Mask1

1

RW

0h

POR - DAFG - ULR

GPIO1 input type (when configured as input): 0 = Non-Sticky (level-sensitive);

1 = Sticky (edge-sensitive).

Mask0

0

RW

0h

POR - DAFG - ULR

GPIO0 input type (when configured as input): 0 = Non-Sticky (level-sensitive);

1 = Sticky (edge-sensitive).

7.4.17. AFG (NID = 01h): SubID

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

723h

722h

721h

720h

Get

F2300h / F2200h / F2100h / F2000h

Field Name

Bits

R/W

Default

Reset

Subsys3

31:24

RW

00h

POR

Subsystem ID (byte 3)

23:16 RW

Subsystem ID (byte 2)

15:8 RW

Subsystem ID (byte 1)

7:0 RW

Subsys2

Subsys1

Assembly

00h

01h

00h

POR

Assembly ID (Not applicable to codec vendors).

7.4.18. AFG (NID = 01h): GPIOPlrty

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

770h

Get

F7000h

Please note that the 40QFN package version only supports GPIO0, GPIO1 and GPIO2

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Field Name

Bits

R/W

Default

Reset

Rsvd

31:7

R

00000000h

N/A (Hard-coded)

Reserved.

6

GP6

GP5

GP4

GP3

RW

1h

POR - DAFG - ULR

GPIO6 Polarity:

If configured as output or non-sticky input:

0 = inverting

1 = non-inverting

If configured as sticky input:

0 = falling edges will be detected

1 = rising edges will be detected

5

RW

1h

GPIO5 Polarity:

If configured as output or non-sticky input:

0 = inverting

1 = non-inverting

If configured as sticky input:

0 = falling edges will be detected

1 = rising edges will be detected

4

RW

1h

GPIO4 Polarity:

If configured as output or non-sticky input:

0 = inverting

1 = non-inverting

If configured as sticky input:

0 = falling edges will be detected

1 = rising edges will be detected

3

RW

1h

GPIO3 Polarity:

If configured as output or non-sticky input:

0 = inverting

1 = non-inverting

If configured as sticky input:

0 = falling edges will be detected

1 = rising edges will be detected

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

GP2

2

RW

1h

POR - DAFG - ULR

GPIO2 Polarity:

If configured as output or non-sticky input:

0 = inverting

1 = non-inverting

If configured as sticky input:

0 = falling edges will be detected

1 = rising edges will be detected

GP1

1

RW

1h

POR - DAFG - ULR

GPIO1 Polarity:

If configured as output or non-sticky input:

0 = inverting

1 = non-inverting

If configured as sticky input:

0 = falling edges will be detected

1 = rising edges will be detected

GP0

0

RW

1h

POR - DAFG - ULR

GPIO0 Polarity:

If configured as output or non-sticky input:

0 = inverting

1 = non-inverting

If configured as sticky input:

0 = falling edges will be detected

1 = rising edges will be detected

7.4.19. AFG (NID = 01h): GPIODrive

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

771h

Get

F7100h

Please note that the 40QFN package version only supports GPIO0, GPIO1 and GPIO2

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

Rsvd

31:7

R

00000000h

N/A (Hard-coded)

Reserved.

6

OD6

OD5

OD4

OD3

OD2

OD1

OD0

RW

0h

POR - DAFG - ULR

GPIO6 Drive Mode: 0 = push-pull (drive 0 and 1); 1 = open drain (drive 0, float

for 1).

5

RW

0h

POR - DAFG - ULR

GPIO5 Drive Mode: 0 = push-pull (drive 0 and 1); 1 = open drain (drive 0, float

for 1).

4

RW

0h

POR - DAFG - ULR

GPIO4 Drive Mode: 0 = push-pull (drive 0 and 1); 1 = open drain (drive 0, float

for 1).

3

RW

0h

POR - DAFG - ULR

GPIO3 Drive Mode: 0 = push-pull (drive 0 and 1); 1 = open drain (drive 0, float

for 1).

2

RW

0h

POR - DAFG - ULR

GPIO2 Drive Mode: 0 = push-pull (drive 0 and 1); 1 = open drain (drive 0, float

for 1).

1

RW

0h

POR - DAFG - ULR

GPIO1 Drive Mode: 0 = push-pull (drive 0 and 1); 1 = open drain (drive 0, float

for 1).

0

RW

0h

POR - DAFG - ULR

GPIO0 Drive Mode: 0 = push-pull (drive 0 and 1); 1 = open-drain (drive 0, float

for 1).

7.4.20. AFG (NID = 01h): DMic

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

778h

Get

F7800h

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

Rsvd

31:6

R

0000000h

N/A (Hard-coded)

Reserved.

5

Mono1

Mono0

PhAdj

RW

0h

POR

DMic1 mono select: 0 = stereo operation, 1 = mono operation (left channel du-

plicated to the right channel).

4

RW

0h

POR

DMic0 mono select: 0 = stereo operation, 1 = mono operation (left channel du-

plicated to the right channel).

3:2

RW

0h

POR

Selects what phase of the DMic clock the data should be latched:

0h = left data rising edge/right data falling edge

1h = left data center of high/right data center of low

2h = left data falling edge/right data rising edge

3h = left data center of low/right data center of high

Rate

1:0

RW

2h

POR

Selects the DMic clock rate:

0h = 4.704MHz

1h = 3.528MHz

2h = 2.352MHz

3h = 1.176MHz.

7.4.21. AFG (NID = 01h): DACMode

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

780h

Get

F8000h

Field Name

Bits

R/W

Default

Reset

N/A (Hard-coded)

Rsvd

31:9

R

000000h

Reserved.

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

Atten3dB

8

RW

1h

POR - S&DAFG - LR

Attenuate DAC path signal by 3dB

RW 0h

SDM wait-to-settle disable:

1 = at mute, the SDM switches to the mute pattern immediately

0 = at mute, the SDM switches to the mute pattern after settling (can take up to

~45ms)

SDMSettleDisable

SDMCoeffSel

7

POR - S&DAFG - LR

6

RW

0h

POR - S&DAFG - LR

DAC SDM coefficient select (stages 1, 2, 3):

1 = 1/16, 1/2, 1/4

0 = 1/16, 1/4, 1/2

SDMLFHalf

5

RW

0h

POR - S&DAFG - LR

DAC SDM local feedback coefficient select: 1 = 1/4096, 0 = 1/2048.

4 RW 0h POR - S&DAFG - LR

SDMLFDisable

DAC SDM local feedback disable: 1 = local feedback disabled, 0 = local feed-

back enabled.

InvertValid

InvertData

3

RW

0h

POR - S&DAFG - LR

DAC Valid Invert: 1 = 7.056MHz valid strobe is inverted, 0 = 7.056MHz valid

strobe is not inverted.

2

RW

0h

POR - S&DAFG - LR

DAC Data Invert: 1 = 1-bit outputs are inverted, 0 = 1-bit outputs are not invert-

ed.

Atten6dBDisable

Fade

1

RW

Disable built-in -6dB digital attenuation: 1 = -6dB disabled, 0 = -6dB enabled.

RW 1h POR - S&DAFG - LR

DAC Gain Fade Enable:

1h

POR - S&DAFG - LR

0

1 = gain will be slowly faded from old value to new value (~10ms)

0 = gain will jump immediately to new value.

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Eight channel HD Audio codec optimized for low power

7.4.22. AFG (NID = 01h): ADCMode

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

784h

Get

F8400h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:4

R

0000000h

N/A (Hard-coded)

Reserved.

3

InvertValid

RW

0h

POR - S&DAFG - LR

ADC Valid Invert: 1 = 14.112MHz valid strobe is inverted, 0 = 14.112MHz valid

strobe is not inverted.

InvertData

Rsvd1

2

RW

0h

POR - S&DAFG - LR

ADC Data Invert: 1 = 1-bit inputs are inverted, 0 = 1-bit inputs are not inverted.

1:0

R

0h

N/A (Hard-coded)

Reserved.

7.4.23. AFG (NID = 01h): EAPD

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

788h

Get

F8800h

Field Name

Bits

R/W

Default

Reset

Rsvd3

31:15

Reserved.

14

R

00000h

N/A (Hard-coded)

HPBSDInv

RW

0h

POR

HP Amp Shutdown Invert:

0 = Amp will power down (or mute) when EAPD pin is low

1 = Amp will power down (or mute) when EAPD pin is high

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

HPBSDMode

13

RW

0h

POR

HP Amp Shutdown Mode:

0 = Amp will mute when disabled

1 = Amp will enter a low power state when disabled

HPBSD

12

RW

0h

POR

HP Amp Shutdown Control Select:

0 = Amp controlled by EAPD pin only

1 = Amp controlled by power state only

Rsvd2

11

R

0h

N/A (Hard-coded)

POR

Reserved.

10

HPASDInv

RW

0h

HP Amp Shutdown Invert:

0 = Amp will power down (or mute) when EAPD pin is low

1 = Amp will power down (or mute) when EAPD pin is high

HPASDMode

HPASD

9

RW

0h

POR

HP Amp Shutdown Mode:

0 = Amp will mute when disabled

1 = Amp will enter a low power state when disabled

8

RW

0h

POR

HP Amp Shutdown Control Select:

0 = Amp controlled by EAPD pin only

1 = Amp controlled by power state only

Rsvd1

7:2

R

0h

N/A (Hard-coded)

POR

Reserved.

1:0

PinMode

RW

0h

EAPD Pin Mode:

00b = Open Drain I/O (Value at pin is wired-AND of EAPD bit and external sig-

nal)

01b = CMOS Output (Value of EAPD bit is forced at pin)

1xb = CMOS Input (External signal controls internal amps, EAPD bit ignored)

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Eight channel HD Audio codec optimized for low power

7.4.24. AFG (NID = 01h): PortUse

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

7C0h

Get

FC000h

Field Name

Bits

R/W

Default

Reset

Rsvd

31:8

R

0000000h

N/A (Hard-coded)

Reserved.

7

PortH

PortG

PortF

PortE

PortD

PortC

PortB

RW

0h

POR

Port H usage: 0 = connected as an output, 1 = either not connected or connect-

ed as an input.

6

RW

0h

POR

Port G usage: 0 = connected as an output, 1 = either not connected or connect-

ed as an input.

5

RW

0h

POR

Port F usage: 0 = connected as an output, 1 = either not connected or connect-

ed as an input.

4

RW

0h

POR

Port E usage: 0 = connected as an output, 1 = either not connected or connect-

ed as an input.

3

RW

0h

POR

Port D usage: 0 = connected as an output, 1 = either not connected or connect-

ed as an input.

2

RW

0h

POR

Port C usage: 0 = connected as an output, 1 = either not connected or connect-

ed as an input.

1

RW

0h

POR

Port B usage: 0 = connected as an output, 1 = either not connected or connect-

ed as an input.

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

PortA

0

RW

0h

POR

Port A usage: 0 = connected as an output, 1 = either not connected or connect-

ed as an input.

7.4.25. AFG (NID = 01h): VSPwrState

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

7D8h

Get

FD800h

Field Name

Bits

R/W

Default

Reset

Rsvd

31:2

R

00000000h

N/A (Hard-coded)

Reserved.

1

D5

D4

RW

0h

POR - ELR

Vendor specific D5 power state, only entered once the part is already in D3cold

(this bit must be set before the command to enter D3cold). If set, this bit over-

rides the D4 bit (bit 0). Includes the power savings of D4, but additionally pow-

ers down GPIO pins, the VAG amp, and the HP amps. Exits this power state

via POR or rising edge of Link Reset.

0

RW

0h

POR - ELR

Vendor specific D4 power state, only entered once the part is already in D3cold

(this bit must be set before the command to enter D3cold). If the D5 bit (bit 1)

is set, this bit is overridden. Includes the power savings of D3cold, but addi-

tionally powers down the HDA interface (no responses). Exit this power state

via POR or rising edge of Link Reset.

7.4.26. AFG (NID = 01h): AnaPort

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

7EDh

7ECh

Get

FEC00h

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

Rsvd

31:8

R

0000000h

N/A (Hard-coded)

Reserved.

7

HPwd

GPwd

FPwd

EPwd

DPwd

CPwd

BPwd

APwd

RW

0h

POR - S&DAFG - ULR

Power down Port H.

RW

Power down Port G.

RW

Power down Port F.

RW

Power down Port E.

RW

Power down Port D.

RW

Power down Port C.

RW

Power down Port B.

RW

Power down Port A.

6

5

4

3

2

1

0

7.4.27. AFG (NID = 01h): AnaBeep

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

7EEh

Get

FEE00h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:7

R

0000000h

N/A (Hard-coded)

Reserved.

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

BeepDetect

6

R

0h

POR - DAFG - ULR

0: no beep present; 1: beep present

5:4 RW 3h

Gain

POR

Analog PC Beep Gain: 0h = -24dB, 1h = -18dB, 2h = -12dB, 3h = -6dB.

3:2 RW 0h POR

Select counter delay.0h=64ms,1h = 128ms, 2h = 256ms, 3h = 512ms

1:0 RW 2h POR

CntSel

Mode

Analog PC Beep Mode:

00b = Always disabled

01b = Always enabled

1xb = Enabled during HDA Link Reset only

7.4.28. AFG (NID = 01h): Reset

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

7FFh

Get

FFF00h

Field Name

Bits

R/W

Default

Reset

Rsvd1

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7:0

Execute

W

00h

N/A (Hard-coded)

Function Reset. Function Group reset is executed when the Set verb 7FF is

written with 8-bit payload of 00h. The codec should issue a response to ac-

knowledge receipt of the verb, and then reset the affected Function Group and

all associated widgets to their power-on reset values. Some controls such as

Configuration Default controls should not be reset. Overlaps Response.

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Eight channel HD Audio codec optimized for low power

7.5. PortA (NID = 0Ah): WCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0009h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:24

R

00h

N/A (Hard-coded)

Reserved.

23:20

Type

R

4h

N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay

19:16

R

0h

N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1

SwapCap

PwrCntrl

Dig

15:12

Reserved.

11

R

0h

R

0h

Left/right swap support: 1 = yes, 0 = no.

10 1h

Power state support: 1 = yes, 0 = no.

0h

R

9

R

Digital stream support: 1 = yes (digital), 0 = no (analog).

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

ConnList

8

R

1h

N/A (Hard-coded)

Connection list present: 1 = yes, 0 = no.

1h

UnSolCap

ProcWidget

Stripe

7

R

N/A (Hard-coded)

Unsolicited response support: 1 = yes, 0 = no.

0h

Processing state support: 1 = yes, 0 = no.

0h

Striping support: 1 = yes, 0 = no.

0h

Stream format override: 1 = yes, 0 = no.

0h

Amplifier capabilities override: 1 = yes, no.

0h

Output amp present: 1 = yes, 0 = no.

1h

Input amp present: 1 = yes, 0 = no.

1h

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

6

R

N/A (Hard-coded)

5

R

FormatOvrd

AmpParOvrd

OutAmpPrsnt

InAmpPrsnt

Stereo

4

R

3

R

2

R

1

R

0

R

7.5.1.

PortA (NID = 0Ah): PinCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Ch

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:17

Reserved.

16

R

0000h

N/A (Hard-coded)

EapdCap

VrefCntrl

R

1h

N/A (Hard-coded)

EAPD support: 1 = yes, 0 = no.

15:8

R

17h

Vref support:

bit 7 = Reserved

bit 6 = Reserved

bit 5 = 100% support (1 = yes, 0 = no)

bit 4 = 80% support (1 = yes, 0 = no)

bit 3 = Reserved

bit 2 = GND support (1 = yes, 0 = no)

bit 1 = 50% support (1 = yes, 0 = no)

bit 0 = Hi-Z support (1 = yes, 0 = no)

Rsvd1

7

R

0h

N/A (Hard-coded)

Reserved.

6

BalancedIO

InCap

R

0h

Balanced I/O support: 1 = yes, 0 = no.

1h

Input support: 1 = yes, 0 = no.

1h

Output support: 1 = yes, 0 = no.

1h

Headphone amp present: 1 = yes, 0 = no.

1h

Presence detection support: 1 = yes, 0 = no.

0h

5

R

OutCap

4

R

HdphDrvCap

PresDtctCap

TrigRqd

3

R

2

R

1

R

Trigger required for impedance sense: 1 = yes, 0 = no.

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

ImpSenseCap

0

R

0h

N/A (Hard-coded)

Impedance sense support: 1 = yes, 0 = no.

7.5.2.

PortA (NID = 0Ah): ConLst

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Eh

Field Name

Bits

R/W

Default

Reset

Rsvd

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

LForm

ConL

R

0h

N/A (Hard-coded)

Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)

NID entries.

6:0

R

04h

N/A (Hard-coded)

Number of NID entries in connection list.

7.5.3.

PortA (NID = 0Ah): ConLstEntry0

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0200h

Field Name

Bits

R/W

Default

Reset

ConL3

31:24

R

19h

N/A (Hard-coded)

DAC4 Converter widget (0x19)

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

ConL2

23:16

R

1Eh

N/A (Hard-coded)

MixerOutVol Selector widget (0x1E)

15 1h

ConL1Range

ConL1

R

N/A (Hard-coded)

1 = ConL0..ConL1 defines a range of selectable inputs.

14:8

DAC3 Converter widget (0x18)

7:0 15h

R

18h

N/A (Hard-coded)

ConL0

R

N/A (Hard-coded)

DAC0 Converter widget (0x15)

7.5.4.

PortA (NID = 0Ah): InAmpLeft

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

360h

Get

B2000h

Field Name

Bits

R/W

Default

Reset

Rsvd1

31:2

R

00000000h

N/A (Hard-coded)

Reserved.

1:0

Gain

R

0h

POR - DAFG - ULR

Amp gain step number (see InAmpCap parameter pertaining to this widget).

7.5.5.

PortA (NID = 0Ah): InAmpRight

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

350h

Get

B0000h

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

Rsvd1

31:2

R

00000000h

N/A (Hard-coded)

Reserved.

1:0

Gain

R

0h

POR - DAFG - ULR

Amp gain step number (see InAmpCap parameter pertaining to this widget).

7.5.6.

PortA (NID = 0Ah): ConSelectCtrl

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

701h

Get

F0100h

Field Name

Bits

R/W

Default

Reset

Rsvd

31:3

R

00000000h

N/A (Hard-coded)

Reserved.

2:0

Index

RW

0h

POR - DAFG - ULR

Connection select control index.

7.5.7.

PortA (NID = 0Ah): PwrState

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

705h

Get

F0500h

Field Name

Bits

R/W

Default

Reset

Rsvd4

31:11

R

000000h

N/A (Hard-coded)

Reserved.

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

SettingsReset

10

R

1h

POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

Rsvd3

Error

9

R

0h

N/A (Hard-coded)

Reserved.

8

R

0h

POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

Rsvd2

Act

7:6

R

0h

N/A (Hard-coded)

POR - DAFG - LR

N/A (Hard-coded)

POR - DAFG - LR

Reserved.

5:4

R

3h

Actual power state of this widget.

Rsvd1

Set

3:2

R

0h

Reserved.

1:0

RW

0h

Current power state setting for this widget.

7.5.8.

PortA (NID = 0Ah): PinWCntrl

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

707h

Get

F0700h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

HPhnEn

RW

0h

POR - DAFG - ULR

Headphone amp enable: 1 = enabled, 0 = disabled.

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

OutEn

6

RW

0h

POR - DAFG - ULR

Output enable: 1 = enabled, 0 = disabled.

0h

Input enable: 1 = enabled, 0 = disabled.

InEn

5

R

POR - DAFG - ULR

N/A (Hard-coded)

POR - DAFG - ULR

Rsvd1

VRefEn

4:3

R

0h

Reserved.

2:0

R

0h

Vref selection (See VrefCntrl field of PinCap parameter for supported selec-

tions):

000b= HI-Z

001b= 50%

010b= GND

011b= Reserved

100b= 80%

101b= 100%

110b= Reserved

111b= Reserved

7.5.9.

PortA (NID = 0Ah): UnsolResp

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

708h

Get

F0800h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

En

RW

0h

POR - DAFG - ULR

Unsolicited response enable (also enables Wake events for this Widget): 1 =

enabled, 0 = disabled.

Rsvd1

6

R

0h

N/A (Hard-coded)

Reserved.

89

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

Tag

5:0

RW

00h

POR - DAFG - ULR

Software programmable field returned in top six bits (31:26) of every Unsolicit-

ed Response generated by this node.

7.5.10. PortA (NID = 0Ah): ChSense

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

709h

Get

F0900h

Field Name

Bits

R/W

Default

0h

Reset

PresDtct

31

R

POR

Presence detection indicator: 1 = presence detected; 0 = presence not detect-

ed.

Rsvd

30:0

R

00000000h

N/A (Hard-coded)

Reserved.

7.5.11. PortA (NID = 0Ah): EAPDBTLLR

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

70Ch

Get

F0C00h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:2

R

00000000h

N/A (Hard-coded)

Reserved.

1

EAPD

RW

1h

POR - DAFG - ULR

EAPD control: 1 = set EAPD pin to 1 (powered) up if this pin is powered up, 0

= set EAPD pin to 0.

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

Rsvd1

0

R

0h

N/A (Hard-coded)

Reserved.

7.5.12. PortA (NID = 0Ah): ConfigDefault

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

71Dh

Byte 1 (Bits 7:0)

71Fh

71Eh

71Ch

Get

F1F00h / F1E00h / F1D00h / F1C00h

Field Name

Bits

R/W

Default

Reset

PortConnectivity

31:30

RW

0h

POR

Port connectivity:

0h = Port complex is connected to a jack

1h = No physical connection for port

2h = Fixed function device is attached

3h = Both jack and internal device attached (info in all other fields refers to in-

tegrated device, any presence detection refers to jack)

Location

29:24

RW

02h

POR

Location

Bits [5..4]:

0h = External on primary chassis

1h = Internal

2h = Separate chassis

3h = Other

Bits [3..0]:

0h = N/A

1h = Rear

2h = Front

3h = Left

4h = Right

5h = Top

6h = Bottom

7h-9h = Special

Ah-Fh = Reserved

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Field Name

Bits

R/W

Default

Reset

Device

23:20

RW

2h

POR

Default device:

0h = Line out

1h = Speaker

2h = HP out

3h = CD

4h = SPDIF Out

5h = Digital other out

6h = Modem line side

7h = Modem handset side

8h = Line in

9h = Aux

Ah = Mic in

Bh = Telephony

Ch = SPDIF In

Dh = Digital other in

Eh = Reserved

Fh = Other

ConnectionType

19:16

RW

1h

POR

Connection type:

0h = Unknown

1h = 1/8" stereo/mono

2h = 1/4" stereo/mono

3h = ATAPI internal

4h = RCA

5h = Optical

6h = Other digital

7h = Other analog

8h = Multichannel analog (DIN)

9h = XLR/Professional

Ah = RJ-11 (modem)

Bh = Combination

Ch-Eh = Reserved

Fh = Other

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Field Name

Bits

R/W

Default

Reset

Color

15:12

RW

4h

POR

Color:

0h = Unknown

1h = Black

2h = Grey

3h = Blue

4h = Green

5h = Red

6h = Orange

7h = Yellow

8h = Purple

9h = Pink

Ah-Dh = Reserved

Eh = White

Fh = Other

Misc

11:8

RW

0h

POR

Miscellaneous:

Bits [3..1] = Reserved

Bit 0 = Jack detect override

Association

Sequence

7:4

RW

1h

0h

POR

Default assocation.

3:0

RW

Sequence.

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7.6. PortB (NID = 0Bh): WCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0009h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:24

R

00h

N/A (Hard-coded)

Reserved.

23:20

Type

R

4h

N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay

19:16

R

0h

N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1

15:12

Reserved.

11

R

0h

SwapCap

PwrCntrl

Dig

R

0h

Left/right swap support: 1 = yes, 0 = no.

10 1h

Power state support: 1 = yes, 0 = no.

0h

Digital stream support: 1 = yes (digital), 0 = no (analog).

1h N/A (Hard-coded)

R

9

R

ConnList

8

R

Connection list present: 1 = yes, 0 = no.

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Field Name

Bits

R/W

Default

Reset

UnSolCap

7

R

1h

N/A (Hard-coded)

Unsolicited response support: 1 = yes, 0 = no.

0h

Processing state support: 1 = yes, 0 = no.

0h

Striping support: 1 = yes, 0 = no.

0h

Stream format override: 1 = yes, 0 = no.

0h

Amplifier capabilities override: 1 = yes, no.

0h

Output amp present: 1 = yes, 0 = no.

1h

Input amp present: 1 = yes, 0 = no.

1h

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

ProcWidget

Stripe

6

R

N/A (Hard-coded)

5

R

FormatOvrd

AmpParOvrd

OutAmpPrsnt

InAmpPrsnt

Stereo

4

R

3

R

2

R

1

R

0

R

7.6.1.

PortB (NID = 0Bh): PinCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Ch

Field Name

Bits

R/W

Default

Reset

N/A (Hard-coded)

Rsvd2

31:17

R

0000h

Reserved.

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

EapdCap

16

R

1h

N/A (Hard-coded)

EAPD support: 1 = yes, 0 = no.

VrefCntrl

15:8

R

17h

N/A (Hard-coded)

Vref support:

bit 7 = Reserved

bit 6 = Reserved

bit 5 = 100% support (1 = yes, 0 = no)

bit 4 = 80% support (1 = yes, 0 = no)

bit 3 = Reserved

bit 2 = GND support (1 = yes, 0 = no)

bit 1 = 50% support (1 = yes, 0 = no)

bit 0 = Hi-Z support (1 = yes, 0 = no)

Rsvd1

7

R

0h

N/A (Hard-coded)

Reserved.

6

BalancedIO

InCap

R

0h

Balanced I/O support: 1 = yes, 0 = no.

1h

Input support: 1 = yes, 0 = no.

1h

Output support: 1 = yes, 0 = no.

1h

Headphone amp present: 1 = yes, 0 = no.

1h

Presence detection support: 1 = yes, 0 = no.

0h

Trigger required for impedance sense: 1 = yes, 0 = no.

0h N/A (Hard-coded)

5

R

OutCap

4

R

HdphDrvCap

PresDtctCap

TrigRqd

3

R

2

R

1

R

ImpSenseCap

0

R

Impedance sense support: 1 = yes, 0 = no.

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Eight channel HD Audio codec optimized for low power

7.6.2.

PortB (NID = 0Bh): ConLst

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Eh

Field Name

Bits

R/W

Default

Reset

Rsvd

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

LForm

ConL

R

0h

N/A (Hard-coded)

Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)

NID entries.

6:0

R

04h

N/A (Hard-coded)

Number of NID entries in connection list.

7.6.3.

PortB (NID = 0Bh): ConLstEntry0

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0200h

Field Name

Bits

R/W

Default

Reset

ConL3

31:24

R

19h

N/A (Hard-coded)

DAC4 Converter widget (0x19)

23:16 1Eh

MixerOutVol Selector widget (0x1E)

14:8 1h

ConL2

R

N/A (Hard-coded)

ConL1Range

R

1 = ConL0..ConL1 defines a range of selectable inputs.

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Field Name

Bits

R/W

Default

Reset

ConL1

15:8

R

18h

N/A (Hard-coded)

DAC3 Converter widget (0x18)

7:0 15h

ConL0

R

N/A (Hard-coded)

DAC0 Converter widget (0x15)

7.6.4.

PortB (NID = 0Bh): ConSelectCtrl

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

701h

Get

F0100h

Field Name

Bits

R/W

Default

Reset

Rsvd

31:2

R

00000000h

N/A (Hard-coded)

Reserved.

1:0

Index

RW

0h

POR - DAFG - ULR

Connection select control index.

7.6.5.

PortB (NID = 0Bh): InAmpLeft

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

360h

Get

B2000h

Field Name

Bits

R/W

Default

Reset

Rsvd1

31:2

R

00000000h

N/A (Hard-coded)

Reserved.

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Field Name

Bits

R/W

Default

Reset

Gain

1:0

RW

0h

POR - DAFG - ULR

Amp gain step number (see InAmpCap parameter pertaining to this widget).

7.6.6.

PortB (NID = 0Bh): InAmpRight

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

350h

Get

B0000h

Field Name

Bits

R/W

Default

Reset

Rsvd1

31:2

R

00000000h

N/A (Hard-coded)

Reserved.

1:0

Gain

RW

0h

POR - DAFG - ULR

Amp gain step number (see InAmpCap parameter pertaining to this widget).

7.6.7.

PortB (NID = 0Bh): PwrState

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

705h

Get

F0500h

Field Name

Bits

R/W

Default

Reset

Rsvd4

31:11

Reserved.

10

R

000000h

N/A (Hard-coded)

SettingsReset

R

1h

POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

Rsvd3

9

R

0h

N/A (Hard-coded)

Reserved.

8

Error

R

0h

POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

Rsvd2

Act

7:6

R

0h

N/A (Hard-coded)

POR - DAFG - LR

N/A (Hard-coded)

POR - DAFG - LR

Reserved.

5:4

R

3h

Actual power state of this widget.

Rsvd1

Set

3:2

R

0h

Reserved.

1:0

RW

0h

Current power state setting for this widget.

7.6.8.

PortB (NID = 0Bh): PinWCntrl

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

707h

Get

F0700h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

HPhnEn

OutEn

RW

0h

POR - DAFG - ULR

Headphone amp enable: 1 = enabled, 0 = disabled.

RW 0h POR - DAFG - ULR

6

Output enable: 1 = enabled, 0 = disabled.

100

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

InEn

5

RW

0h

POR - DAFG - ULR

Output enable: 1 = enabled, 0 = disabled.

Rsvd1

4:3

RW

00h

N/A (Hard-coded)

Reserved.

2:0

VRefEn

RW

0h

POR - DAFG - ULR

Vref selection (See VrefCntrl field of PinCap parameter for supported selec-

tions):

000b= HI-Z

001b= 50%

010b= GND

011b= Reserved

100b= 80%

101b= 100%

110b= Reserved

111b= Reserved

7.6.9.

PortB (NID = 0Bh): UnsolResp

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

708h

Get

F0800h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

En

RW

0h

POR - DAFG - ULR

Unsolicited response enable (also enables Wake events for this Widget): 1 =

enabled, 0 = disabled.

Rsvd1

6

R

0h

N/A (Hard-coded)

Reserved.

101

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

Tag

5:0

RW

00h

POR - DAFG - ULR

Software programmable field returned in top six bits (31:26) of every Unsolicit-

ed Response generated by this node.

7.6.10. PortB (NID = 0Bh): ChSense

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

709h

Get

F0900h

Field Name

Bits

R/W

Default

0h

Reset

PresDtct

31

R

POR

Presence detection indicator: 1 = presence detected; 0 = presence not detect-

ed.

Rsvd

30:0

R

00000000h

N/A (Hard-coded)

Reserved.

7.6.11. PortB (NID = 0Bh): EAPDBTLLR

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

70Ch

Get

F0C00h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:2

R

00000000h

N/A (Hard-coded)

Reserved.

1

EAPD

RW

1h

POR - DAFG - ULR

EAPD control: 1 = set EAPD pin to 1 (powered) up if this pin is powered up, 0

= set EAPD pin to 0.

102

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Field Name

Bits

R/W

Default

Reset

Rsvd1

0

R

0h

N/A (Hard-coded)

Reserved.

7.6.12. PortB (NID = 0Bh): ConfigDefault

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

71Dh

Byte 1 (Bits 7:0)

71Fh

71Eh

71Ch

Get

F1F00h / F1E00h / F1D00h / F1C00h

Field Name

Bits

R/W

Default

Reset

PortConnectivity

31:30

RW

0h

POR

Port connectivity:

0h = Port complex is connected to a jack

1h = No physical connection for port

2h = Fixed function device is attached

3h = Both jack and internal device attached (info in all other fields refers to in-

tegrated device, any presence detection refers to jack)

Location

29:24

RW

02h

POR

Location

Bits [5..4]:

0h = External on primary chassis

1h = Internal

2h = Separate chassis

3h = Other

Bits [3..0]:

0h = N/A

1h = Rear

2h = Front

3h = Left

4h = Right

5h = Top

6h = Bottom

7h-9h = Special

Ah-Fh = Reserved

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Field Name

Bits

R/W

Default

Reset

Device

23:20

RW

Ah

POR

Default device:

0h = Line out

1h = Speaker

2h = HP out

3h = CD

4h = SPDIF Out

5h = Digital other out

6h = Modem line side

7h = Modem handset side

8h = Line in

9h = Aux

Ah = Mic in

Bh = Telephony

Ch = SPDIF In

Dh = Digital other in

Eh = Reserved

Fh = Other

ConnectionType

19:16

RW

1h

POR

Connection type:

0h = Unknown

1h = 1/8" stereo/mono

2h = 1/4" stereo/mono

3h = ATAPI internal

4h = RCA

5h = Optical

6h = Other digital

7h = Other analog

8h = Multichannel analog (DIN)

9h = XLR/Professional

Ah = RJ-11 (modem)

Bh = Combination

Ch-Eh = Reserved

Fh = Other

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Field Name

Bits

R/W

Default

Reset

Color

15:12

RW

9h

POR

Color:

0h = Unknown

1h = Black

2h = Grey

3h = Blue

4h = Green

5h = Red

6h = Orange

7h = Yellow

8h = Purple

9h = Pink

Ah-Dh = Reserved

Eh = White

Fh = Other

Misc

11:8

RW

0h

POR

Miscellaneous:

Bits [3..1] = Reserved

Bit 0 = Jack detect override

Association

Sequence

7:4

RW

2h

0h

POR

Default assocation.

3:0

RW

Sequence.

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7.7. PortC (NID = 0Ch): WCap

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:24

R

00h

N/A (Hard-coded)

Reserved.

23:20

Type

R

4h

N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay

19:16

R

0h

N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1

15:12

Reserved.

11

R

0h

SwapCap

PwrCntrl

Dig

Left/right swap support: 1 = yes, 0 = no.

10 1h

Power state support: 1 = yes, 0 = no.

0h

Digital stream support: 1 = yes (digital), 0 = no (analog).

R

9

R

ConnList

UnSolCap

ProcWidget

8

R

1h

Connection list present: 1 = yes, 0 = no.

1h

Unsolicited response support: 1 = yes, 0 = no.

0h N/A (Hard-coded)

N/A (Hard-coded)

7

R

N/A (Hard-coded)

6

R

Processing state support: 1 = yes, 0 = no.

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7.7. PortC (NID = 0Ch): WCap

Field Name

Bits

R/W

Default

Reset

Stripe

5

R

0h

N/A (Hard-coded)

Striping support: 1 = yes, 0 = no.

0h

Stream format override: 1 = yes, 0 = no.

0h

Amplifier capabilities override: 1 = yes, no.

0h

Output amp present: 1 = yes, 0 = no.

1h

Input amp present: 1 = yes, 0 = no.

1h

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

FormatOvrd

AmpParOvrd

OutAmpPrsnt

InAmpPrsnt

Stereo

4

R

N/A (Hard-coded)

3

R

2

R

1

R

0

R

7.7.1.

PortC (NID = 0Ch): PinCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Ch

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:17

Reserved.

16

R

0000h

N/A (Hard-coded)

EapdCap

R

1h

N/A (Hard-coded)

EAPD support: 1 = yes, 0 = no.

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Field Name

Bits

R/W

Default

Reset

VrefCntrl

15:8

R

00h

N/A (Hard-coded)

Vref support:

bit 7 = Reserved

bit 6 = Reserved

bit 5 = 100% support (1 = yes, 0 = no)

bit 4 = 80% support (1 = yes, 0 = no)

bit 3 = Reserved

bit 2 = GND support (1 = yes, 0 = no)

bit 1 = 50% support (1 = yes, 0 = no)

bit 0 = Hi-Z support (1 = yes, 0 = no)

Rsvd1

7

R

0h

N/A (Hard-coded)

Reserved.

6

BalancedIO

InCap

R

0h

Balanced I/O support: 1 = yes, 0 = no.

1h

Input support: 1 = yes, 0 = no.

1h

Output support: 1 = yes, 0 = no.

0h

Headphone amp present: 1 = yes, 0 = no.

1h

Presence detection support: 1 = yes, 0 = no.

0h

Trigger required for impedance sense: 1 = yes, 0 = no.

0h N/A (Hard-coded)

Impedance sense support: 1 = yes, 0 = no.

5

R

OutCap

4

R

HdphDrvCap

PresDtctCap

TrigRqd

3

R

2

R

1

R

ImpSenseCap

0

R

7.7.2.

PortC (NID = 0Ch): ConLst

Reg

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Set

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7.7.2.

PortC (NID = 0Ch): ConLst

Reg

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Eh

Field Name

Bits

R/W

Default

Reset

Rsvd

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

LForm

ConL

R

0h

N/A (Hard-coded)

Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)

NID entries.

6:0

R

04h

N/A (Hard-coded)

Number of NID entries in connection list.

7.7.3.

PortC (NID = 0Ch): ConLstEntry0

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0200h

Field Name

Bits

R/W

Default

Reset

ConL3

31:24

R

19h

N/A (Hard-coded)

DAC4 Converter widget (0x19)

23:16 1Eh

MixerOutVol Selector widget (0x1E)

15 1h

ConL2

R

N/A (Hard-coded)

ConL1Range

ConL1

R

N/A (Hard-coded)

= ConL0..ConL1 defines a range of selectable inputs.

14:8 16h N/A (Hard-coded)

DAC3 Converter widget (0x16)

R

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Field Name

Bits

R/W

Default

Reset

ConL0

7:0

R

15h

N/A (Hard-coded)

DAC0 Converter widget (0x15)

7.7.4.

PortC (NID = 0Ch): InAmpLeft

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

360h

Get

B2000h

Field Name

Bits

R/W

Default

Reset

Rsvd1

31:2

R

00000000h

N/A (Hard-coded)

Reserved.

1:0

Gain

RW

0h

POR - DAFG - ULR

Amp gain step number (see InAmpCap parameter pertaining to this widget).

7.7.5.

PortC (NID = 0Ch): InAmpRight

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

350h

Get

B0000h

Field Name

Bits

R/W

Default

Reset

Rsvd1

31:2

R

00000000h

N/A (Hard-coded)

Reserved.

1:0

Gain

RW

0h

POR - DAFG - ULR

Amp gain step number (see InAmpCap parameter pertaining to this widget).

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7.7.6.

PortC (NID = 0Ch): ConSelectCtrl

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

701h

Get

F0100h

Field Name

Bits

R/W

Default

Reset

Rsvd

31:2

R

00000000h

N/A (Hard-coded)

Reserved.

1:0

Index

RW

0h

POR - DAFG - ULR

Connection select control index.

7.7.7.

PortC (NID = 0Ch): PwrState

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

705h

Get

F0500h

Field Name

Bits

R/W

Default

Reset

Rsvd4

31:11

Reserved.

10

R

000000h

N/A (Hard-coded)

SettingsReset

R

1h

POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

Rsvd3

Error

9

R

0h

N/A (Hard-coded)

Reserved.

8

R

0h

POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

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Field Name

Bits

R/W

Default

Reset

Rsvd2

7:6

R

0h

N/A (Hard-coded)

Reserved.

5:4

Act

R

3h

POR - DAFG - LR

N/A (Hard-coded)

POR - DAFG - LR

Actual power state of this widget.

Rsvd1

Set

3:2

R

0h

Reserved.

1:0

RW

0h

Current power state setting for this widget.

7.7.8.

PortC (NID = 0Ch): PinWCntrl

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

707h

Get

F0700h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:7

R

000000h

N/A (Hard-coded)

Reserved.

6

OutEn

InEn

RW

0h

POR - DAFG - ULR

N/A (Hard-coded)

POR - DAFG - ULR

Output enable: 1 = enabled, 0 = disabled.

RW 0h

Input enable: 1 = enabled, 0 = disabled.

5

Rsvd1

VRefEn

4:3

RW

00h

Reserved.

2:0

RW

0h

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Field Name

Bits

R/W

Default

Reset

Vref selection (See VrefCntrl field of PinCap parameter for supported selec-

tions):

000b= HI-Z

001b= 50%

010b= GND

011b= Reserved

100b= 80%

101b= 100%

110b= Reserved

111b= Reserved

7.7.9.

PortC (NID = 0Ch): UnsolResp

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

708h

Get

F0800h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

En

RW

0h

POR - DAFG - ULR

Unsolicited response enable (also enables Wake events for this Widget): 1 =

enabled, 0 = disabled.

Rsvd1

Tag

6

R

0h

N/A (Hard-coded)

Reserved.

5:0

RW

00h

POR - DAFG - ULR

Software programmable field returned in top six bits (31:26) of every Unsolicit-

ed Response generated by this node.

7.7.10. PortC (NID = 0Ch): ChSense

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

709h

Get

F0900h

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Field Name

Bits

R/W

Default

Reset

PresDtct

31

R

0h

POR

Presence detection indicator: 1 = presence detected; 0 = presence not detect-

ed.

Rsvd

30:0

R

00000000h

N/A (Hard-coded)

Reserved.

7.7.11. PortC (NID = 0Ch): EAPDBTLLR

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

70Ch

Get

F0C00h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:2

R

00000000h

N/A (Hard-coded)

Reserved.

1

EAPD

Rsvd1

RW

1h

POR - DAFG - ULR

EAPD control: 1 = set EAPD pin to 1 (powered) up if this pin is powered up, 0

= set EAPD pin to 0.

0

R

0h

N/A (Hard-coded)

Reserved.

7.7.12. PortC (NID = 0Ch): ConfigDefault

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

71Dh

Byte 1 (Bits 7:0)

71Fh

71Eh

71Ch

Get

F1F00h / F1E00h / F1D00h / F1C00h

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Field Name

Bits

R/W

Default

Reset

PortConnectivity

31:30

RW

0h

POR

Port connectivity:

0h = Port complex is connected to a jack

1h = No physical connection for port

2h = Fixed function device is attached

3h = Both jack and internal device attached (info in all other fields refers to in-

tegrated device, any presence detection refers to jack)

Location

29:24

RW

01h

POR

Location

Bits [5..4]:

0h = External on primary chassis

1h = Internal

2h = Separate chassis

3h = Other

Bits [3..0]:

0h = N/A

1h = Rear

2h = Front

3h = Left

4h = Right

5h = Top

6h = Bottom

7h-9h = Special

Ah-Fh = Reserved

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Field Name

Bits

R/W

Default

Reset

Device

23:20

RW

8h

POR

Default device:

0h = Line out

1h = Speaker

2h = HP out

3h = CD

4h = SPDIF Out

5h = Digital other out

6h = Modem line side

7h = Modem handset side

8h = Line in

9h = Aux

Ah = Mic in

Bh = Telephony

Ch = SPDIF In

Dh = Digital other in

Eh = Reserved

Fh = Other

ConnectionType

19:16

RW

1h

POR

Connection type:

0h = Unknown

1h = 1/8" stereo/mono

2h = 1/4" stereo/mono

3h = ATAPI internal

4h = RCA

5h = Optical

6h = Other digital

7h = Other analog

8h = Multichannel analog (DIN)

9h = XLR/Professional

Ah = RJ-11 (modem)

Bh = Combination

Ch-Eh = Reserved

Fh = Other

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Field Name

Bits

R/W

Default

Reset

Color

15:12

RW

3h

POR

Color:

0h = Unknown

1h = Black

2h = Grey

3h = Blue

4h = Green

5h = Red

6h = Orange

7h = Yellow

8h = Purple

9h = Pink

Ah-Dh = Reserved

Eh = White

Fh = Other

Misc

11:8

RW

0h

POR

Miscellaneous:

Bits [3..1] = Reserved

Bit 0 = Jack detect override

Association

Sequence

7:4

RW

4h

0h

POR

Default assocation.

3:0

RW

Sequence.

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7.8. PortD (NID = 0Dh): WCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0009h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:24

R

00h

N/A (Hard-coded)

Reserved.

23:20

Type

R

4h

N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay

19:16

R

0h

N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1

15:12

Reserved.

11

R

0h

SwapCap

PwrCntrl

Dig

R

0h

Left/right swap support: 1 = yes, 0 = no.

10 1h

Power state support: 1 = yes, 0 = no.

0h

Digital stream support: 1 = yes (digital), 0 = no (analog).

1h N/A (Hard-coded)

R

9

R

ConnList

8

R

Connection list present: 1 = yes, 0 = no.

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Field Name

Bits

R/W

Default

Reset

UnSolCap

7

R

1h

N/A (Hard-coded)

Unsolicited response support: 1 = yes, 0 = no.

0h

Processing state support: 1 = yes, 0 = no.

0h

Striping support: 1 = yes, 0 = no.

0h

Stream format override: 1 = yes, 0 = no.

0h

Amplifier capabilities override: 1 = yes, no.

0h

Output amp present: 1 = yes, 0 = no.

1h

Input amp present: 1 = yes, 0 = no.

1h

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

ProcWidget

Stripe

6

R

N/A (Hard-coded)

5

R

FormatOvrd

AmpParOvrd

OutAmpPrsnt

InAmpPrsnt

Stereo

4

R

3

R

2

R

1

R

0

R

7.8.1.

PortD (NID = 0Dh): PinCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Ch

Field Name

Bits

R/W

Default

Reset

N/A (Hard-coded)

Rsvd2

31:17

R

0000h

Reserved.

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Field Name

Bits

R/W

Default

Reset

EapdCap

16

R

1h

N/A (Hard-coded)

EAPD support: 1 = yes, 0 = no.

VrefCntrl

15:8

R

00h

N/A (Hard-coded)

Vref support:

bit 7 = Reserved

bit 6 = Reserved

bit 5 = 100% support (1 = yes, 0 = no)

bit 4 = 80% support (1 = yes, 0 = no)

bit 3 = Reserved

bit 2 = GND support (1 = yes, 0 = no)

bit 1 = 50% support (1 = yes, 0 = no)

bit 0 = Hi-Z support (1 = yes, 0 = no)

Rsvd1

7

R

0h

N/A (Hard-coded)

Reserved.

6

BalancedIO

InCap

R

0h

Balanced I/O support: 1 = yes, 0 = no.

1h

Input support: 1 = yes, 0 = no.

1h

Output support: 1 = yes, 0 = no.

1h

Headphone amp present: 1 = yes, 0 = no.

1h

Presence detection support: 1 = yes, 0 = no.

0h

Trigger required for impedance sense: 1 = yes, 0 = no.

0h N/A (Hard-coded)

5

R

OutCap

4

R

HdphDrvCap

PresDtctCap

TrigRqd

3

R

2

R

1

R

ImpSenseCap

0

R

Impedance sense support: 1 = yes, 0 = no.

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7.8.2.

PortD (NID = 0Dh): ConLst

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Eh

Field Name

Bits

R/W

Default

Reset

Rsvd

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

LForm

ConL

R

0h

N/A (Hard-coded)

Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)

NID entries.

6:0

R

04h

N/A (Hard-coded)

Number of NID entries in connection list.

7.8.3.

PortD (NID = 0Dh): ConLstEntry0

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0200h

Field Name

Bits

R/W

Default

Reset

ConL3

31:24

R

19h

N/A (Hard-coded)

DAC4 Converter widget (0x19)

23:16 1Eh

MixerOutVol Selector widget (0x1E)

14:8 1h

ConL2

R

N/A (Hard-coded)

ConL1Range

R

1 = ConL0..ConL1 defines a range of selectable inputs.

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Field Name

Bits

R/W

Default

Reset

ConL1

15:8

R

18h

N/A (Hard-coded)

DAC3 Converter widget (0x18)

7:0 15h

ConL0

R

N/A (Hard-coded)

DAC0 Converter widget (0x15)

7.8.4.

PortD (NID = 0Dh): InAmpLeft

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

360h

Get

B2000h

Field Name

Bits

R/W

Default

Reset

Rsvd1

31:2

R

00000000h

N/A (Hard-coded)

Reserved.

1:0

Gain

RW

0h

POR - DAFG - ULR

Amp gain step number (see InAmpCap parameter pertaining to this widget).

7.8.5.

PortD (NID = 0Dh): InAmpRight

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

350h

Get

B0000h

Field Name

Bits

R/W

Default

Reset

N/A (Hard-coded)

Rsvd1

31:2

R

00000000h

Reserved.

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Field Name

Bits

R/W

Default

Reset

Gain

1:0

RW

0h

POR - DAFG - ULR

Amp gain step number (see InAmpCap parameter pertaining to this widget).

7.8.6.

PortD (NID = 0Dh): ConSelectCtrl

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

701h

Get

F0100h

Field Name

Bits

R/W

Default

Reset

Rsvd

31:2

R

00000000h

N/A (Hard-coded)

Reserved.

1:0

Index

RW

0h

POR - DAFG - ULR

Connection select control index.

7.8.7.

PortD (NID = 0Dh): PwrState

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

705h

Get

F0500h

Field Name

Bits

R/W

Default

Reset

Rsvd4

31:11

Reserved.

10

R

000000h

N/A (Hard-coded)

SettingsReset

R

1h

POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

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Field Name

Bits

R/W

Default

Reset

Rsvd3

9

R

0h

N/A (Hard-coded)

Reserved.

8

Error

R

0h

POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

Rsvd2

Act

7:6

R

0h

N/A (Hard-coded)

POR - DAFG - LR

N/A (Hard-coded)

POR - DAFG - LR

Reserved.

5:4

R

3h

Actual power state of this widget.

Rsvd1

Set

3:2

R

0h

Reserved.

1:0

RW

0h

Current power state setting for this widget.

7.8.8.

PortD (NID = 0Dh): PinWCntrl

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

707h

Get

F0700h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

HPhnEn

OutEn

RW

0h

POR - DAFG - ULR

Headphone amp enable: 1 = enabled, 0 = disabled

RW 0h POR - DAFG - ULR

6

Output enable: 1 = enabled, 0 = disabled.

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Field Name

Bits

R/W

Default

Reset

InEn

5

RW‘

0h

POR - DAFG - ULR

Input enable: 1 = enabled, 0 = disabled

Rsvd1

4:0

R

0h

N/A (Hard-coded)

Reserved.

7.8.9.

PortD (NID = 0Dh): UnsolResp

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

708h

Get

F0800h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

En

RW

0h

POR - DAFG - ULR

Unsolicited response enable (also enables Wake events for this Widget): 1 =

enabled, 0 = disabled.

Rsvd1

Tag

6

R

0h

N/A (Hard-coded)

Reserved.

5:0

RW

00h

POR - DAFG - ULR

Software programmable field returned in top six bits (31:26) of every Unsolicit-

ed Response generated by this node.

7.8.10. PortD (NID = 0Dh): ChSense

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

709h

Get

F0900h

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Field Name

Bits

R/W

Default

Reset

PresDtct

31

R

0h

POR

Presence detection indicator: 1 = presence detected; 0 = presence not detect-

ed.

Rsvd

30:0

R

00000000h

N/A (Hard-coded)

Reserved.

7.8.11. PortD (NID = 0Dh): EAPDBTLLR

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

70Ch

Get

F0C00h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:2

R

00000000h

N/A (Hard-coded)

Reserved.

1

EAPD

Rsvd1

RW

1h

POR - DAFG - ULR

EAPD control: 1 = set EAPD pin to 1 (powered) up if this pin is powered up, 0

= set EAPD pin to 0.

0

R

0h

N/A (Hard-coded)

Reserved.

7.8.12. PortD (NID = 0Dh): ConfigDefault

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

71Dh

Byte 1 (Bits 7:0)

71Fh

71Eh

71Ch

Get

F1F00h / F1E00h / F1D00h / F1C00h

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Field Name

Bits

R/W

Default

Reset

PortConnectivity

31:30

RW

0h

POR

Port connectivity:

0h = Port complex is connected to a jack

1h = No physical connection for port

2h = Fixed function device is attached

3h = Both jack and internal device attached (info in all other fields refers to in-

tegrated device, any presence detection refers to jack)

Location

29:24

RW

01h

POR

Location

Bits [5..4]:

0h = External on primary chassis

1h = Internal

2h = Separate chassis

3h = Other

Bits [3..0]:

0h = N/A

1h = Rear

2h = Front

3h = Left

4h = Right

5h = Top

6h = Bottom

7h-9h = Special

Ah-Fh = Reserved

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Field Name

Bits

R/W

Default

Reset

Device

23:20

RW

0h

POR

Default device:

0h = Line out

1h = Speaker

2h = HP out

3h = CD

4h = SPDIF Out

5h = Digital other out

6h = Modem line side

7h = Modem handset side

8h = Line in

9h = Aux

Ah = Mic in

Bh = Telephony

Ch = SPDIF In

Dh = Digital other in

Eh = Reserved

Fh = Other

ConnectionType

19:16

RW

1h

POR

Connection type:

0h = Unknown

1h = 1/8" stereo/mono

2h = 1/4" stereo/mono

3h = ATAPI internal

4h = RCA

5h = Optical

6h = Other digital

7h = Other analog

8h = Multichannel analog (DIN)

9h = XLR/Professional

Ah = RJ-11 (modem)

Bh = Combination

Ch-Eh = Reserved

Fh = Other

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Field Name

Bits

R/W

Default

Reset

Color

15:12

RW

4h

POR

Color:

0h = Unknown

1h = Black

2h = Grey

3h = Blue

4h = Green

5h = Red

6h = Orange

7h = Yellow

8h = Purple

9h = Pink

Ah-Dh = Reserved

Eh = White

Fh = Other

Misc

11:8

RW

0h

POR

Miscellaneous:

Bits [3..1] = Reserved

Bit 0 = Jack detect override

Association

Sequence

7:4

RW

3h

0h

POR

Default assocation.

3:0

RW

Sequence.

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7.9. PortE (NID = 0Eh): WCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0009h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:24

R

00h

N/A (Hard-coded)

Reserved.

23:20

Type

R

4h

N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay

19:16

R

0h

N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1

15:12

Reserved.

11

R

0h

SwapCap

PwrCntrl

Dig

R

0h

Left/right swap support: 1 = yes, 0 = no.

10 1h

Power state support: 1 = yes, 0 = no.

0h

Digital stream support: 1 = yes (digital), 0 = no (analog).

1h N/A (Hard-coded)

R

9

R

ConnList

8

R

Connection list present: 1 = yes, 0 = no.

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Field Name

Bits

R/W

Default

Reset

UnSolCap

7

R

1h

N/A (Hard-coded)

Unsolicited response support: 1 = yes, 0 = no.

0h

Processing state support: 1 = yes, 0 = no.

0h

Striping support: 1 = yes, 0 = no.

0h

Stream format override: 1 = yes, 0 = no.

0h

Amplifier capabilities override: 1 = yes, no.

0h

Output amp present: 1 = yes, 0 = no.

1h

Input amp present: 1 = yes, 0 = no.

1h

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

ProcWidget

Stripe

6

R

N/A (Hard-coded)

5

R

FormatOvrd

AmpParOvrd

OutAmpPrsnt

InAmpPrsnt

Stereo

4

R

3

R

2

R

1

R

0

R

7.9.1.

PortE (NID = 0Eh): PinCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Ch

Field Name

Bits

R/W

Default

Reset

N/A (Hard-coded)

Rsvd2

31:17

R

0000h

Reserved.

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Field Name

Bits

R/W

Default

Reset

EapdCap

16

R

1h

N/A (Hard-coded)

EAPD support: 1 = yes, 0 = no.

VrefCntrl

15:8

R

17h

N/A (Hard-coded)

Vref support:

bit 7 = Reserved

bit 6 = Reserved

bit 5 = 100% support (1 = yes, 0 = no)

bit 4 = 80% support (1 = yes, 0 = no)

bit 3 = Reserved

bit 2 = GND support (1 = yes, 0 = no)

bit 1 = 50% support (1 = yes, 0 = no)

bit 0 = Hi-Z support (1 = yes, 0 = no)

Rsvd1

7

R

0h

N/A (Hard-coded)

Reserved.

6

BalancedIO

InCap

R

0h

Balanced I/O support: 1 = yes, 0 = no.

1h

Input support: 1 = yes, 0 = no.

1h

Output support: 1 = yes, 0 = no.

0h

Headphone amp present: 1 = yes, 0 = no.

1h

Presence detection support: 1 = yes, 0 = no.

0h

Trigger required for impedance sense: 1 = yes, 0 = no.

0h N/A (Hard-coded)

5

R

OutCap

4

R

HdphDrvCap

PresDtctCap

TrigRqd

3

R

2

R

1

R

ImpSenseCap

0

R

Impedance sense support: 1 = yes, 0 = no.

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7.9.2.

PortE (NID = 0Eh): ConLst

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Eh

Field Name

Bits

R/W

Default

Reset

Rsvd

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

LForm

ConL

R

0h

N/A (Hard-coded)

Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)

NID entries.

6:0

R

04h

N/A (Hard-coded)

Number of NID entries in connection list.

7.9.3.

PortE (NID = 0Eh): ConLstEntry0

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0200h

Field Name

Bits

R/W

Default

Reset

ConL3

31:24

R

19h

N/A (Hard-coded)

DAC4 Converter widget (0x19)

23:16 1Eh

MixerOutVol Selector widget (0x1E)

14:8 1h

ConL2

R

N/A (Hard-coded)

ConL1Range

R

1 = ConL0..ConL1 defines a range of selectable inputs.

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Field Name

Bits

R/W

Default

Reset

ConL1

15:8

R

18h

N/A (Hard-coded)

DAC3 Converter widget (0x18)

7:0 15h

ConL0

R

N/A (Hard-coded)

DAC0 Converter widget (0x15)

7.9.4.

PortE (NID = 0Eh): InAmpLeft

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

360h

Get

B2000h

Field Name

Bits

R/W

Default

Reset

Rsvd1

31:2

R

00000000h

N/A (Hard-coded)

Reserved.

1:0

Gain

RW

0h

POR - DAFG - ULR

Amp gain step number (see InAmpCap parameter pertaining to this widget).

7.9.5.

PortE (NID = 0Eh): InAmpRight

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

350h

Get

B0000h

Field Name

Bits

R/W

Default

Reset

Rsvd1

31:2

R

00000000h

N/A (Hard-coded)

Reserved.

1:0

Gain

RW

0h

POR - DAFG - ULR

Amp gain step number (see InAmpCap parameter pertaining to this widget).

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7.9.6.

PortE (NID = 0Eh): ConSelectCtrl

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

701h

Get

F0100h

Field Name

Bits

R/W

Default

Reset

Rsvd

31:2

R

00000000h

N/A (Hard-coded)

Reserved.

1:0

Index

RW

0h

POR - DAFG - ULR

Connection select control index.

7.9.7.

PortE (NID = 0Eh): PwrState

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

705h

Get

F0500h

Field Name

Bits

R/W

Default

Reset

Rsvd4

31:11

Reserved.

10

R

000000h

N/A (Hard-coded)

SettingsReset

R

1h

POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

Rsvd3

Error

9

R

0h

N/A (Hard-coded)

Reserved.

8

R

0h

POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

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Field Name

Bits

R/W

Default

Reset

Rsvd2

7:6

R

0h

N/A (Hard-coded)

Reserved.

5:4

Act

R

3h

POR - DAFG - LR

N/A (Hard-coded)

POR - DAFG - LR

Actual power state of this widget.

Rsvd1

Set

3:2

R

0h

Reserved.

1:0

RW

0h

Current power state setting for this widget.

7.9.8.

PortE (NID = 0Eh): PinWCntrl

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

707h

Get

F0700h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:7

R

000000h

N/A (Hard-coded)

Reserved.

6

OutEn

InEn

RW

0h

POR - DAFG - ULR

N/A (Hard-coded)

POR - DAFG - ULR

Output enable: 1 = enabled, 0 = disabled.

RW 1h

Input enable: 1 = enabled, 0 = disabled.

5

Rsvd1

VRefEn

4:3

R

0h

Reserved.

2.0

RW

0h

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Field Name

Bits

R/W

Default

Reset

Vref selection (See VrefCntrl field of PinCap parameter for supported selec-

tions):

000b= HI-Z

001b= 50%

010b= GND

011b= Reserved

100b= 80%

101b= 100%

110b= Reserved

111b= Reserved

7.9.9.

PortE (NID = 0Eh): UnsolResp

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

708h

Get

F0800h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

En

RW

0h

POR - DAFG - ULR

Unsolicited response enable (also enables Wake events for this Widget): 1 =

enabled, 0 = disabled.

Rsvd1

Tag

6

R

0h

N/A (Hard-coded)

Reserved.

5:0

RW

00h

POR - DAFG - ULR

Software programmable field returned in top six bits (31:26) of every Unsolicit-

ed Response generated by this node.

7.9.10. PortE (NID = 0Eh): ChSense

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

709h

Get

F0900h

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Field Name

Bits

R/W

Default

Reset

PresDtct

31

R

0h

POR

Presence detection indicator: 1 = presence detected; 0 = presence not detect-

ed.

Rsvd

30:0

R

00000000h

N/A (Hard-coded)

Reserved.

7.9.11. PortE (NID = 0Eh): EAPDBTLLR

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

70Ch

Get

F0C00h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:2

R

00000000h

N/A (Hard-coded)

Reserved.

1

EAPD

Rsvd1

RW

1h

POR - DAFG - ULR

EAPD control: 1 = set EAPD pin to 1 (powered) up if this pin is powered up, 0

= set EAPD pin to 0.

0

R

0h

N/A (Hard-coded)

Reserved.

7.9.12. PortE (NID = 0Eh): ConfigDefault

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

71Dh

Byte 1 (Bits 7:0)

71Fh

71Eh

71Ch

Get

F1F00h / F1E00h / F1D00h / F1C00h

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Field Name

Bits

R/W

Default

Reset

PortConnectivity

31:30

RW

0h

POR

Port connectivity:

0h = Port complex is connected to a jack

1h = No physical connection for port

2h = Fixed function device is attached

3h = Both jack and internal device attached (info in all other fields refers to in-

tegrated device, any presence detection refers to jack)

Location

29:24

RW

01h

POR

Location

Bits [5..4]:

0h = External on primary chassis

1h = Internal

2h = Separate chassis

3h = Other

Bits [3..0]:

0h = N/A

1h = Rear

2h = Front

3h = Left

4h = Right

5h = Top

6h = Bottom

7h-9h = Special

Ah-Fh = Reserved

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Field Name

Bits

R/W

Default

Reset

Device

23:20

RW

Ah

POR

Default device:

0h = Line out

1h = Speaker

2h = HP out

3h = CD

4h = SPDIF Out

5h = Digital other out

6h = Modem line side

7h = Modem handset side

8h = Line in

9h = Aux

Ah = Mic in

Bh = Telephony

Ch = SPDIF In

Dh = Digital other in

Eh = Reserved

Fh = Other

ConnectionType

19:16

RW

1h

POR

Connection type:

0h = Unknown

1h = 1/8" stereo/mono

2h = 1/4" stereo/mono

3h = ATAPI internal

4h = RCA

5h = Optical

6h = Other digital

7h = Other analog

8h = Multichannel analog (DIN)

9h = XLR/Professional

Ah = RJ-11 (modem)

Bh = Combination

Ch-Eh = Reserved

Fh = Other

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Field Name

Bits

R/W

Default

Reset

Color

15:12

RW

9h

POR

Color:

0h = Unknown

1h = Black

2h = Grey

3h = Blue

4h = Green

5h = Red

6h = Orange

7h = Yellow

8h = Purple

9h = Pink

Ah-Dh = Reserved

Eh = White

Fh = Other

Misc

11:8

RW

0h

POR

Miscellaneous:

Bits [3..1] = Reserved

Bit 0 = Jack detect override

Association

Sequence

7:4

RW

4h

Eh

POR

Default assocation.

3:0

RW

Sequence.

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7.10. PortF (NID = 0Fh): WCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0009h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:24

R

00h

N/A (Hard-coded)

Reserved.

23:20

Type

R

4h

N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay

19:16

R

0h

N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1

15:12

Reserved.

11

R

0h

SwapCap

PwrCntrl

Dig

R

0h

Left/right swap support: 1 = yes, 0 = no.

10 1h

Power state support: 1 = yes, 0 = no.

0h

Digital stream support: 1 = yes (digital), 0 = no (analog).

1h N/A (Hard-coded)

R

9

R

ConnList

8

R

Connection list present: 1 = yes, 0 = no.

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Field Name

Bits

R/W

Default

Reset

UnSolCap

7

R

1h

N/A (Hard-coded)

Unsolicited response support: 1 = yes, 0 = no.

0h

Processing state support: 1 = yes, 0 = no.

0h

Striping support: 1 = yes, 0 = no.

0h

Stream format override: 1 = yes, 0 = no.

0h

Amplifier capabilities override: 1 = yes, no.

0h

Output amp present: 1 = yes, 0 = no.

1h

Input amp present: 1 = yes, 0 = no.

1h

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

ProcWidget

Stripe

6

R

N/A (Hard-coded)

5

R

FormatOvrd

AmpParOvrd

OutAmpPrsnt

InAmpPrsnt

Stereo

4

R

3

R

2

R

1

R

0

R

7.10.1. PortF (NID = 0Fh): PinCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Ch

Field Name

Bits

R/W

Default

Reset

N/A (Hard-coded)

Rsvd2

31:17

R

0000h

Reserved.

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Field Name

Bits

R/W

Default

Reset

EapdCap

16

R

1h

N/A (Hard-coded)

EAPD support: 1 = yes, 0 = no.

VrefCntrl

15:8

R

00h

N/A (Hard-coded)

Vref support:

bit 7 = Reserved

bit 6 = Reserved

bit 5 = 100% support (1 = yes, 0 = no)

bit 4 = 80% support (1 = yes, 0 = no)

bit 3 = Reserved

bit 2 = GND support (1 = yes, 0 = no)

bit 1 = 50% support (1 = yes, 0 = no)

bit 0 = Hi-Z support (1 = yes, 0 = no)

Rsvd1

7

R

0h

N/A (Hard-coded)

Reserved.

6

BalancedIO

InCap

R

0h

Balanced I/O support: 1 = yes, 0 = no.

1h

Input support: 1 = yes, 0 = no.

1h

Output support: 1 = yes, 0 = no.

0h

Headphone amp present: 1 = yes, 0 = no.

1h

Presence detection support: 1 = yes, 0 = no.

0h

Trigger required for impedance sense: 1 = yes, 0 = no.

0h N/A (Hard-coded)

5

R

OutCap

4

R

HdphDrvCap

PresDtctCap

TrigRqd

3

R

2

R

1

R

ImpSenseCap

0

R

Impedance sense support: 1 = yes, 0 = no.

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7.10.2. PortF (NID = 0Fh): ConLst

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Eh

Field Name

Bits

R/W

Default

Reset

Rsvd

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

LForm

ConL

R

0h

N/A (Hard-coded)

Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)

NID entries.

6:0

R

04h

N/A (Hard-coded)

Number of NID entries in connection list.

7.10.3. PortF (NID = 0Fh): ConLstEntry0

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0200h

Field Name

Bits

R/W

Default

Reset

ConL3

31:24

R

19h

N/A (Hard-coded)

DAC4 Converter widget (0x19)

23:16 1Eh

MixerOutVol Selector widget (0x1E)

14:8 1h

ConL2

R

N/A (Hard-coded)

ConL1Range

R

1 = ConL0..ConL1 defines a range of selectable inputs.

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Field Name

Bits

R/W

Default

Reset

ConL1

15:8

R

18h

N/A (Hard-coded)

DAC3 Converter widget (0x18)

7:0 15h

DAC0 Converter widget (0x15)

ConL0

R

N/A (Hard-coded)

7.10.4. PortF (NID = 0Fh): InAmpLeft

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

360h

Get

B2000h

Field Name

Bits

R/W

Default

Reset

Rsvd1

31:2

R

00000000h

N/A (Hard-coded)

Reserved.

1:0

Gain

RW

0h

POR - DAFG - ULR

Amp gain step number (see InAmpCap parameter pertaining to this widget).

7.10.5. PortF (NID = 0Fh): InAmpRight

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

350h

Get

B0000h

Field Name

Bits

R/W

Default

Reset

Rsvd1

31:2

R

00000000h

N/A (Hard-coded)

Reserved.

1:0

Gain

RW

0h

POR - DAFG - ULR

Amp gain step number (see InAmpCap parameter pertaining to this widget).

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7.10.6. PortF (NID = 0Fh): ConSelectCtrl

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

701h

Get

F0100h

Field Name

Bits

R/W

Default

Reset

Rsvd

31:2

R

00000000h

N/A (Hard-coded)

Reserved.

1:0

Index

RW

0h

POR - DAFG - ULR

Connection select control index.

7.10.7. PortF (NID = 0Fh): PwrState

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

705h

Get

F0500h

Field Name

Bits

R/W

Default

Reset

Rsvd4

31:11

Reserved.

10

R

000000h

N/A (Hard-coded)

SettingsReset

R

1h

POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

Rsvd3

Error

9

R

0h

N/A (Hard-coded)

Reserved.

8

R

0h

POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

147

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

Rsvd2

7:6

R

0h

N/A (Hard-coded)

Reserved.

5:4

Act

R

3h

POR - DAFG - LR

N/A (Hard-coded)

POR - DAFG - LR

Actual power state of this widget.

Rsvd1

Set

3:2

R

0h

Reserved.

1:0

RW

0h

Current power state setting for this widget.

7.10.8. PortF (NID = 0Fh): PinWCntrl

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

707h

Get

F0700h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:7

R

000000h

N/A (Hard-coded)

Reserved.

6

OutEn

InEn

RW

0h

POR - DAFG - ULR

N/A (Hard-coded)

Output enable: 1 = enabled, 0 = disabled.

RW 0h

Input enable: 1 = enabled, 0 = disabled.

5

Rsvd1

4:0

R

0h

Reserved.

148

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Eight channel HD Audio codec optimized for low power

7.10.9. PortF (NID = 0Fh): UnsolResp

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

708h

Get

F0800h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

En

RW

0h

POR - DAFG - ULR

Unsolicited response enable (also enables Wake events for this Widget): 1 =

enabled, 0 = disabled.

Rsvd1

Tag

6

R

0h

N/A (Hard-coded)

Reserved.

5:0

RW

00h

POR - DAFG - ULR

Software programmable field returned in top six bits (31:26) of every Unsolicit-

ed Response generated by this node.

7.10.10. PortF (NID = 0Fh): ChSense

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

709h

Get

F0900h

Field Name

Bits

R/W

Default

0h

Reset

PresDtct

31

R

POR

Presence detection indicator: 1 = presence detected; 0 = presence not detect-

ed.

Rsvd

30:0

R

00000000h

N/A (Hard-coded)

Reserved.

149

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Eight channel HD Audio codec optimized for low power

7.10.11. PortF (NID = 0Fh): EAPDBTLLR

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

70Ch

Get

F0C00h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:2

R

00000000h

N/A (Hard-coded)

Reserved.

1

EAPD

Rsvd1

RW

1h

POR - DAFG - ULR

EAPD control: 1 = set EAPD pin to 1 (powered) up if this pin is powered up, 0

= set EAPD pin to 0.

0

R

0h

N/A (Hard-coded)

Reserved.

7.10.12. PortF (NID = 0Fh): ConfigDefault

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

71Dh

Byte 1 (Bits 7:0)

71Fh

71Eh

71Ch

Get

F1F00h / F1E00h / F1D00h / F1C00h

Field Name

Bits

R/W

Default

Reset

PortConnectivity

31:30

RW

0h

POR

Port connectivity:

0h = Port complex is connected to a jack

1h = No physical connection for port

2h = Fixed function device is attached

3h = Both jack and internal device attached (info in all other fields refers to in-

tegrated device, any presence detection refers to jack)

150

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

Location

29:24

RW

01h

POR

Location

Bits [5..4]:

0h = External on primary chassis

1h = Internal

2h = Separate chassis

3h = Other

Bits [3..0]:

0h = N/A

1h = Rear

2h = Front

3h = Left

4h = Right

5h = Top

6h = Bottom

7h-9h = Special

Ah-Fh = Reserved

Device

23:20

RW

0h

POR

Default device:

0h = Line out

1h = Speaker

2h = HP out

3h = CD

4h = SPDIF Out

5h = Digital other out

6h = Modem line side

7h = Modem handset side

8h = Line in

9h = Aux

Ah = Mic in

Bh = Telephony

Ch = SPDIF In

Dh = Digital other in

Eh = Reserved

Fh = Other

151

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

ConnectionType

19:16

RW

1h

POR

Connection type:

0h = Unknown

1h = 1/8" stereo/mono

2h = 1/4" stereo/mono

3h = ATAPI internal

4h = RCA

5h = Optical

6h = Other digital

7h = Other analog

8h = Multichannel analog (DIN)

9h = XLR/Professional

Ah = RJ-11 (modem)

Bh = Combination

Ch-Eh = Reserved

Fh = Other

Color

15:12

RW

1h

POR

Color:

0h = Unknown

1h = Black

2h = Grey

3h = Blue

4h = Green

5h = Red

6h = Orange

7h = Yellow

8h = Purple

9h = Pink

Ah-Dh = Reserved

Eh = White

Fh = Other

Misc

11:8

RW

0h

POR

Miscellaneous:

Bits [3..1] = Reserved

Bit 0 = Jack detect override

Association

Sequence

7:4

RW

3h

2h

POR

Default assocation.

3:0

RW

Sequence.

152

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Eight channel HD Audio codec optimized for low power

7.11. PortG (NID = 0Gh): WCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0009h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:24

R

00h

N/A (Hard-coded)

Reserved.

23:20

Type

R

4h

N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay

19:16

R

0h

N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1

15:12

Reserved.

11

R

0h

SwapCap

PwrCntrl

Dig

R

0h

Left/right swap support: 1 = yes, 0 = no.

10 1h

Power state support: 1 = yes, 0 = no.

0h

Digital stream support: 1 = yes (digital), 0 = no (analog).

1h N/A (Hard-coded)

R

9

R

ConnList

8

R

Connection list present: 1 = yes, 0 = no.

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

UnSolCap

7

R

1h

N/A (Hard-coded)

Unsolicited response support: 1 = yes, 0 = no.

0h

Processing state support: 1 = yes, 0 = no.

0h

Striping support: 1 = yes, 0 = no.

0h

Stream format override: 1 = yes, 0 = no.

0h

Amplifier capabilities override: 1 = yes, no.

0h

Output amp present: 1 = yes, 0 = no.

1h

Input amp present: 1 = yes, 0 = no.

1h

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

ProcWidget

Stripe

6

R

N/A (Hard-coded)

5

R

FormatOvrd

AmpParOvrd

OutAmpPrsnt

InAmpPrsnt

Stereo

4

R

3

R

2

R

1

R

0

R

7.11.1. PortG (NID = 0Gh): PinCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Ch

Field Name

Bits

R/W

Default

Reset

N/A (Hard-coded)

Rsvd2

31:17

R

0000h

Reserved.

154

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Field Name

Bits

R/W

Default

Reset

EapdCap

16

R

1h

N/A (Hard-coded)

EAPD support: 1 = yes, 0 = no.

VrefCntrl

15:8

R

00h

N/A (Hard-coded)

Vref support:

bit 7 = Reserved

bit 6 = Reserved

bit 5 = 100% support (1 = yes, 0 = no)

bit 4 = 80% support (1 = yes, 0 = no)

bit 3 = Reserved

bit 2 = GND support (1 = yes, 0 = no)

bit 1 = 50% support (1 = yes, 0 = no)

bit 0 = Hi-Z support (1 = yes, 0 = no)

Rsvd1

7

R

0h

N/A (Hard-coded)

Reserved.

6

BalancedIO

InCap

R

0h

Balanced I/O support: 1 = yes, 0 = no.

1h

Input support: 1 = yes, 0 = no.

1h

Output support: 1 = yes, 0 = no.

0h

Headphone amp present: 1 = yes, 0 = no.

1h

Presence detection support: 1 = yes, 0 = no.

0h

Trigger required for impedance sense: 1 = yes, 0 = no.

0h N/A (Hard-coded)

5

R

OutCap

4

R

HdphDrvCap

PresDtctCap

TrigRqd

3

R

2

R

1

R

ImpSenseCap

0

R

Impedance sense support: 1 = yes, 0 = no.

155

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Eight channel HD Audio codec optimized for low power

7.11.2. PortG (NID = 0Gh): ConLst

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Eh

Field Name

Bits

R/W

Default

Reset

Rsvd

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

LForm

ConL

R

0h

N/A (Hard-coded)

Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)

NID entries.

6:0

R

04h

N/A (Hard-coded)

Number of NID entries in connection list.

7.11.3. PortG (NID = 0Gh): ConLstEntry0

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0200h

Field Name

Bits

R/W

Default

Reset

ConL3

31:24

R

19h

N/A (Hard-coded)

DAC4 Converter widget (0x19)

23:16 1Eh

MixerOutVol Selector widget (0x1E)

14:8 1h

ConL2

R

N/A (Hard-coded)

ConL1Range

R

1 = ConL0..ConL1 defines a range of selectable inputs.

156

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

ConL1

15:8

R

18h

N/A (Hard-coded)

DAC3 Converter widget (0x18)

7:0 15h

DAC0 Converter widget (0x15)

ConL0

R

N/A (Hard-coded)

7.11.4. PortG (NID = 0Gh): InAmpLeft

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

360h

Get

B2000h

Field Name

Bits

R/W

Default

Reset

Rsvd1

31:2

R

00000000h

N/A (Hard-coded)

Reserved.

1:0

Gain

RW

0h

POR - DAFG - ULR

Amp gain step number (see InAmpCap parameter pertaining to this widget).

7.11.5. PortG (NID = 0Gh): InAmpRight

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

350h

Get

B0000h

Field Name

Bits

R/W

Default

Reset

Rsvd1

31:2

R

00000000h

N/A (Hard-coded)

Reserved.

1:0

Gain

RW

0h

POR - DAFG - ULR

Amp gain step number (see InAmpCap parameter pertaining to this widget).

157

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Eight channel HD Audio codec optimized for low power

7.11.6. PortG (NID = 0Gh): ConSelectCtrl

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

701h

Get

F0100h

Field Name

Bits

R/W

Default

Reset

Rsvd

31:2

R

00000000h

N/A (Hard-coded)

Reserved.

1:0

Index

RW

0h

POR - DAFG - ULR

Connection select control index.

7.11.7. PortG (NID = 0Gh): PwrState

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

705h

Get

F0500h

Field Name

Bits

R/W

Default

Reset

Rsvd4

31:11

Reserved.

10

R

000000h

N/A (Hard-coded)

SettingsReset

R

1h

POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

Rsvd3

Error

9

R

0h

N/A (Hard-coded)

Reserved.

8

R

0h

POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

158

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

Rsvd2

7:6

R

0h

N/A (Hard-coded)

Reserved.

5:4

Act

R

3h

POR - DAFG - LR

N/A (Hard-coded)

POR - DAFG - LR

Actual power state of this widget.

Rsvd1

Set

3:2

R

0h

Reserved.

1:0

RW

0h

Current power state setting for this widget.

7.11.8. PortG (NID = 0Gh): PinWCntrl

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

707h

Get

F0700h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:7

R

000000h

N/A (Hard-coded)

Reserved.

6

OutEn

InEn

RW

0h

POR - DAFG - ULR

N/A (Hard-coded)

Output enable: 1 = enabled, 0 = disabled.

RW 1h

Input enable: 1 = enabled, 0 = disabled.

5

Rsvd1

4:0

R

00h

Reserved.

159

V1.1 06/11

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Eight channel HD Audio codec optimized for low power

7.11.9. PortG (NID = 0Gh): UnsolResp

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

708h

Get

F0800h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

En

RW

0h

POR - DAFG - ULR

Unsolicited response enable (also enables Wake events for this Widget): 1 =

enabled, 0 = disabled.

Rsvd1

Tag

6

R

0h

N/A (Hard-coded)

Reserved.

5:0

RW

00h

POR - DAFG - ULR

Software programmable field returned in top six bits (31:26) of every Unsolicit-

ed Response generated by this node.

7.11.10. PortG (NID = 0Gh): ChSense

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

709h

Get

F0900h

Field Name

Bits

R/W

Default

0h

Reset

PresDtct

31

R

POR

Presence detection indicator: 1 = presence detected; 0 = presence not detect-

ed.

Rsvd

30:0

R

00000000h

N/A (Hard-coded)

Reserved.

160

V1.1 06/11

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Eight channel HD Audio codec optimized for low power

7.11.11. PortG (NID = 0Gh): EAPDBTLLR

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

70Ch

Get

F0C00h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:2

R

00000000h

N/A (Hard-coded)

Reserved.

1

EAPD

Rsvd1

RW

1h

POR - DAFG - ULR

EAPD control: 1 = set EAPD pin to 1 (powered) up if this pin is powered up, 0

= set EAPD pin to 0.

0

R

0h

N/A (Hard-coded)

Reserved.

7.11.12. PortG (NID = 0Gh): ConfigDefault

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

71Dh

Byte 1 (Bits 7:0)

71Fh

71Eh

71Ch

Get

F1F00h / F1E00h / F1D00h / F1C00h

Field Name

Bits

R/W

Default

Reset

PortConnectivity

31:30

RW

0h

POR

Port connectivity:

0h = Port complex is connected to a jack

1h = No physical connection for port

2h = Fixed function device is attached

3h = Both jack and internal device attached (info in all other fields refers to in-

tegrated device, any presence detection refers to jack)

161

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

Location

29:24

RW

01h

POR

Location

Bits [5..4]:

0h = External on primary chassis

1h = Internal

2h = Separate chassis

3h = Other

Bits [3..0]:

0h = N/A

1h = Rear

2h = Front

3h = Left

4h = Right

5h = Top

6h = Bottom

7h-9h = Special

Ah-Fh = Reserved

Device

23:20

RW

0h

POR

Default device:

0h = Line out

1h = Speaker

2h = HP out

3h = CD

4h = SPDIF Out

5h = Digital other out

6h = Modem line side

7h = Modem handset side

8h = Line in

9h = Aux

Ah = Mic in

Bh = Telephony

Ch = SPDIF In

Dh = Digital other in

Eh = Reserved

Fh = Other

162

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

ConnectionType

19:16

RW

1h

POR

Connection type:

0h = Unknown

1h = 1/8" stereo/mono

2h = 1/4" stereo/mono

3h = ATAPI internal

4h = RCA

5h = Optical

6h = Other digital

7h = Other analog

8h = Multichannel analog (DIN)

9h = XLR/Professional

Ah = RJ-11 (modem)

Bh = Combination

Ch-Eh = Reserved

Fh = Other

Color

15:12

RW

6h

POR

Color:

0h = Unknown

1h = Black

2h = Grey

3h = Blue

4h = Green

5h = Red

6h = Orange

7h = Yellow

8h = Purple

9h = Pink

Ah-Dh = Reserved

Eh = White

Fh = Other

Misc

11:8

RW

0h

POR

Miscellaneous:

Bits [3..1] = Reserved

Bit 0 = Jack detect override

Association

Sequence

7:4

RW

3h

1h

POR

Default assocation.

3:0

RW

Sequence.

163

V1.1 06/11

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Eight channel HD Audio codec optimized for low power

7.12. ADC0 (NID = 1Ah): WCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0009h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:24

R

00h

N/A (Hard-coded)

Reserved.

23:20

Type

R

1h

N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay

19:16

R

Dh

N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1

SwapCap

PwrCntrl

Dig

15:12

Reserved.

11

R

0h

R

0h

Left/right swap support: 1 = yes, 0 = no.

10 1h

Power state support: 1 = yes, 0 = no.

0h

R

9

R

Digital stream support: 1 = yes (digital), 0 = no (analog).

164

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92HD89D

Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

ConnList

8

R

1h

N/A (Hard-coded)

Connection list present: 1 = yes, 0 = no.

0h

UnSolCap

ProcWidget

Stripe

7

R

N/A (Hard-coded)

Unsolicited response support: 1 = yes, 0 = no.

1h

Processing state support: 1 = yes, 0 = no.

0h

Striping support: 1 = yes, 0 = no.

0h

Stream format override: 1 = yes, 0 = no.

0h

Amplifier capabilities override: 1 = yes, no.

0h

Output amp present: 1 = yes, 0 = no.

0h

Input amp present: 1 = yes, 0 = no.

1h

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

6

R

N/A (Hard-coded)

5

R

FormatOvrd

AmpParOvrd

OutAmpPrsnt

InAmpPrsnt

Stereo

4

R

3

R

2

R

1

R

0

R

7.12.1. ADC0 (NID = 1Ah): ConLst

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Eh

165

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

Rsvd

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

LForm

ConL

R

0h

N/A (Hard-coded)

Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)

NID entries.

6:0

R

01h

N/A (Hard-coded)

Number of NID entries in connection list.

7.12.2. ADC0 (NID = 1Ah): ConLstEntry0

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0200h

Field Name

Bits

R/W

Default

Reset

ConL3

31:24

R

00h

N/A (Hard-coded)

Unused list entry.

23:16

Unused list entry.

15:8

Unused list entry.

7:0

ConL2

ConL1

ConL0

R

00h

20h

N/A (Hard-coded)

R

ADC0Mux Selector widget (0x20)

7.12.3. ADC0 (NID = 1Ah): Cnvtr

Reg

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Set

2h

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Eight channel HD Audio codec optimized for low power

7.12.3. ADC0 (NID = 1Ah): Cnvtr

Reg

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

A0000h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:16

Reserved.

15

R

0000h

N/A (Hard-coded)

POR - DAFG - ULR

StrmType

R

0h

Stream type: 1 = Non-PCM, 0 = PCM.

14 RW 0h

Sample base rate: 1 = 44.1kHz, 0 = 48kHz.

13:11 RW 0h

Sample base rate multiple:

FrmtSmplRate

SmplRateMultp

000b= x1 (48kHz/44.1kHz or less)

001b= x2 (96kHz/88.2kHz/32kHz)

010b= x3 (144kHz)

011b= x4 (192kHz/176.4kHz)

100b-111b Reserved

SmplRateDiv

10:8

RW

0h

POR - DAFG - ULR

Sample base rate divider:

000b= Divide by 1 (48kHz/44.1kHz)

001b= Divide by 2 (24kHz/20.05kHz)

010b= Divide by 3 (16kHz/32kHz)

011b= Divide by 4 (11.025kHz)

100b= Divide by 5 (9.6kHz)

101b= Divide by 6 (8kHz)

110b= Divide by 7

111b= Divide by 8 (6kHz)

Rsvd1

7

R

0h

N/A (Hard-coded)

Reserved.

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Field Name

Bits

R/W

Default

Reset

BitsPerSmpl

6:4

RW

3h

POR - DAFG - ULR

Bits per sample:

000b= 8 bits

001b= 16 bits

010b= 20 bits

011b= 24 bits

100b= 32 bits

101b-111b= Reserved

NmbrChan

3:0

RW

1h

POR - DAFG - ULR

Total number of channels in the stream assigned to this converter:

0000b-1111b= 1-16 channels.

7.12.4. ADC0 (NID = 1Ah): ProcState

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

703h

Get

F0300h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

HPFOCDIS

RW

0h

POR - DAFG - ULR

HPF offset calculation disable. 1 = calculation disabled; 0 = calculation en-

abled.

Rsvd1

6:2

R

00h

N/A (Hard-coded)

Reserved.

1:0

ADCHPFByp

RW

1h

POR - DAFG - ULR

Processing State: 00b= bypass the ADC HPF ("off"), 01b-11b= ADC HPF is en-

abled ("on" or "benign").

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7.12.5. ADC0 (NID = 1Ah): PwrState

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

705h

Get

F0500h

Field Name

Bits

R/W

Default

Reset

Rsvd4

31:11

Reserved.

10

R

000000h

N/A (Hard-coded)

SettingsReset

R

1h

POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

Rsvd3

Error

9

R

0h

N/A (Hard-coded)

Reserved.

8

R

0h

POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

Rsvd2

Act

7:6

R

0h

N/A (Hard-coded)

POR - DAFG - LR

N/A (Hard-coded)

POR - DAFG - LR

Reserved.

5:4

R

3h

Actual power state of this widget.

Rsvd1

Set

3:2

R

0h

Reserved.

1:0

RW

3h

Current power state setting for this widget.

7.12.6. ADC0 (NID = 1Ah): CnvtrID

Reg

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

706h

Set

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7.12.6. ADC0 (NID = 1Ah): CnvtrID

Reg

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0600h

Field Name

Bits

R/W

Default

Reset

Rsvd

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7:4

Strm

Ch

RW

0h

POR - S&DAFG - LR - PS

Stream ID: 0h = Converter "off", 1h-Fh = valid ID's.

3:0 RW 0h POR - S&DAFG - LR - PS

Channel assignment ("Ch" and "Ch+1" assigned as a pair, for a stereo convert-

er).

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7.13. ADC1 (NID = 1Bh): WCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0009h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:24

R

00h

N/A (Hard-coded)

Reserved.

23:20

Type

R

1h

N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay

19:16

R

Dh

N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1

15:12

Reserved.

11

R

0h

SwapCap

PwrCntrl

Dig

R

0h

Left/right swap support: 1 = yes, 0 = no.

10 1h

Power state support: 1 = yes, 0 = no.

0h

Digital stream support: 1 = yes (digital), 0 = no (analog).

1h N/A (Hard-coded)

R

9

R

ConnList

8

R

Connection list present: 1 = yes, 0 = no.

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Field Name

Bits

R/W

Default

Reset

UnSolCap

7

R

0h

N/A (Hard-coded)

Unsolicited response support: 1 = yes, 0 = no.

1h

Processing state support: 1 = yes, 0 = no.

0h

Striping support: 1 = yes, 0 = no.

0h

Stream format override: 1 = yes, 0 = no.

0h

Amplifier capabilities override: 1 = yes, no.

0h

Output amp present: 1 = yes, 0 = no.

0h

Input amp present: 1 = yes, 0 = no.

1h

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

ProcWidget

Stripe

6

R

N/A (Hard-coded)

5

R

FormatOvrd

AmpParOvrd

OutAmpPrsnt

InAmpPrsnt

Stereo

4

R

3

R

2

R

1

R

0

R

7.13.1. ADC1 (NID = 1Bh): ConLst

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Eh

Field Name

Bits

R/W

Default

Reset

N/A (Hard-coded)

Rsvd

31:8

R

000000h

Reserved.

172

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

LForm

7

R

0h

N/A (Hard-coded)

Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)

NID entries.

ConL

6:0

R

01h

N/A (Hard-coded)

Number of NID entries in connection list.

7.13.2. ADC1 (NID = 1Bh): ConLstEntry0

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0200h

Field Name

Bits

R/W

Default

Reset

ConL3

31:24

R

00h

N/A (Hard-coded)

Unused list entry.

23:16

Unused list entry.

15:8

Unused list entry.

7:0

ADC1Mux widget (0x21)

ConL2

ConL1

ConL0

R

00h

21h

N/A (Hard-coded)

R

7.13.3. ADC1 (NID = 1Bh): Cnvtr

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

2h

Get

A0000h

173

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Field Name

Bits

R/W

Default

Reset

Rsvd2

31:16

Reserved.

15

R

0000h

N/A (Hard-coded)

StrmType

R

0h

N/A (Hard-coded)

POR - DAFG - ULR

Stream type: 1 = Non-PCM, 0 = PCM.

14 RW 0h

Sample base rate: 1 = 44.1kHz, 0 = 48kHz.

13:11 RW 0h

Sample base rate multiple:

FrmtSmplRate

SmplRateMultp

000b= x1 (48kHz/44.1kHz or less)

001b= x2 (96kHz/88.2kHz/32kHz)

010b= x3 (144kHz)

011b= x4 (192kHz/176.4kHz)

100b-111b Reserved

SmplRateDiv

10:8

RW

0h

POR - DAFG - ULR

Sample base rate divider:

000b= Divide by 1 (48kHz/44.1kHz)

001b= Divide by 2 (24kHz/20.05kHz)

010b= Divide by 3 (16kHz/32kHz)

011b= Divide by 4 (11.025kHz)

100b= Divide by 5 (9.6kHz)

101b= Divide by 6 (8kHz)

110b= Divide by 7

111b= Divide by 8 (6kHz)

Rsvd1

7

R

0h

3h

N/A (Hard-coded)

Reserved.

6:4

BitsPerSmpl

RW

POR - DAFG - ULR

Bits per sample:

000b= 8 bits

001b= 16 bits

010b= 20 bits

011b= 24 bits

100b= 32 bits

101b-111b= Reserved

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Field Name

Bits

R/W

Default

Reset

NmbrChan

3:0

RW

1h

POR - DAFG - ULR

Total number of channels in the stream assigned to this converter:

0000b-1111b= 1-16 channels.

7.13.4. ADC1 (NID = 1Bh): ProcState

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

703h

Get

F0300h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

HPFOCDIS

RW

0h

POR - DAFG - ULR

HPF offset calculation disable. 1 = calculation disabled; 0 = calculation en-

abled.

Rsvd1

6:2

R

00h

N/A (Hard-coded)

Reserved.

1:0

ADCHPFByp

RW

1h

POR - DAFG - ULR

Processing State: 00b= bypass the ADC HPF ("off"), 01b-11b= ADC HPF is en-

abled ("on" or "benign").

7.13.5. ADC1 (NID = 1Bh): PwrState

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

705h

Get

F0500h

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

Rsvd4

31:11

Reserved.

10

R

000000h

N/A (Hard-coded)

SettingsReset

R

1h

POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

Rsvd3

Error

9

R

0h

N/A (Hard-coded)

Reserved.

8

R

0h

POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

Rsvd2

Act

7:6

R

0h

N/A (Hard-coded)

POR - DAFG - LR

N/A (Hard-coded)

POR - DAFG - LR

Reserved.

5:4

R

3h

Actual power state of this widget.

Rsvd1

Set

3:2

R

0h

Reserved.

1:0

RW

3h

Current power state setting for this widget.

7.13.6. ADC1 (NID = 1Bh): CnvtrID

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

706h

Get

F0600h

176

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Field Name

Bits

R/W

Default

Reset

Rsvd

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7:4

Strm

Ch

RW

0h

POR - S&DAFG - LR - PS

Stream ID: 0h = Converter "off", 1h-Fh = valid ID's.

3:0 RW 0h POR - S&DAFG - LR - PS

Channel assignment ("Ch" and "Ch+1" assigned as a pair, for a stereo convert-

er).

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7.14. DigBeep (NID = 1Ch): WCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0009h

Field Name

Bits

R/W

Default

Reset

Rsvd4

31:24

R

00h

N/A (Hard-coded)

Reserved.

23:20

Type

R

7h

N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Rsvd3

19:11

Reserved.

10

R

0h

1h

N/A (Hard-coded)

PwrCntrl

R

Power state support: 1 = yes, 0 = no."

Rsvd2

9:4

R

0h

N/A (Hard-coded)

Reserved

3

AmpParOvrd

OutAmpPrsnt

Rsvd1

R

1h

Amplifier capabilities override: 1 = yes, no.

1h

Output amp present: 1 = yes, 0 = no.

2

R

1:0

R

0h

Reserved.

178

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Eight channel HD Audio codec optimized for low power

7.14.1. DigBeep (NID = 1Ch): OutAmpCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0012h

Field Name

Bits

R/W

Default

1h

Reset

Mute

31

R

N/A (Hard-coded)

Mute support: 1 = yes, 0 = no.

Rsvd3

30:23

R

00h

17h

Reserved.

22:16

StepSize

Rsvd2

R

Size of each step in the gain range: 0 to 127 = .25dB to 32dB, in .25dB steps.

15

R

0h

N/A (Hard-coded)

Reserved.

14:8

NumSteps

Rsvd1

R

03h

N/A (Hard-coded)

Number of gains steps (number of possible settings - 1).

7

R

0h

N/A (Hard-coded)

Reserved.

6:0

Offset

R

03h

N/A (Hard-coded)

Indicates which step is 0dB

7.14.2. DigBeep (NID = 1Ch): OutAmpLeft

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

3A0h

Get

BA000h

179

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Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

Mute

Rsvd1

Gain

RW

0h

POR - DAFG - ULR

N/A (Hard-coded)

POR - DAFG - ULR

Amp mute: 1 = muted, 0 = not muted.

6:2

R

00h

Reserved.

1:0

RW

1h

Amp gain step number (see OutAmpCap parameter pertaining to this widget).

7.14.3. DigBeep (NID = 1Ch): PwrState

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

705h

Get

F0500h

Field Name

Bits

R/W

Default

Reset

Rsvd4

31:11

Reserved.

10

R

000000h

N/A (Hard-coded)

SettingsReset

R

1h

POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

Rsvd3

Error

9

R

0h

N/A (Hard-coded)

Reserved.

8

R

0h

POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

180

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

Rsvd2

7:6

R

0h

N/A (Hard-coded)

Reserved.

5:4

Act

R

3h

POR - DAFG - LR

N/A (Hard-coded)

POR - DAFG - LR

Actual power state of this widget.

Rsvd1

Set

3:2

R

0h

Reserved.

1:0

RW

0h

Current power state setting for this widget.

7.14.4. DigBeep (NID = 1Ch): Gen

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

70Ah

Get

F0A00h

Field Name

Bits

R/W

Default

Reset

Rsvd

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7:0

Divider

RW

00h

POR - DAFG - LR

Enable internal PC-Beep generation. Divider == 00h disables internal PC Beep

generation and enables normal operation of the codec. Divider != 00h gener-

ates the beep tone on all Pin Complexes that are currently configured as out-

puts. The HD Audio spec states that the beep tone frequency = (48kHz HD

Audio SYNC rate) / (4*Divider), producing tones from 47 Hz to 12 kHz (logarith-

mic scale).

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7.15. Mixer (NID = 1Dh): WCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0009h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:24

R

00h

N/A (Hard-coded)

Reserved.

23:20

Type

R

2h

N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay

19:16

R

0h

N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1

15:12

Reserved.

11

R

0h

SwapCap

PwrCntrl

Dig

R

0h

Left/right swap support: 1 = yes, 0 = no.

10 1h

Power state support: 1 = yes, 0 = no.

0h

Digital stream support: 1 = yes (digital), 0 = no (analog).

1h N/A (Hard-coded)

R

9

R

ConnList

8

R

Connection list present: 1 = yes, 0 = no.

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Field Name

Bits

R/W

Default

Reset

UnSolCap

7

R

0h

N/A (Hard-coded)

Unsolicited response support: 1 = yes, 0 = no.

0h

Processing state support: 1 = yes, 0 = no.

0h

Striping support: 1 = yes, 0 = no.

0h

Stream format override: 1 = yes, 0 = no.

1h

Amplifier capabilities override: 1 = yes, no.

0h

Output amp present: 1 = yes, 0 = no.

1h

Input amp present: 1 = yes, 0 = no.

1h

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

ProcWidget

Stripe

6

R

N/A (Hard-coded)

5

R

FormatOvrd

AmpParOvrd

OutAmpPrsnt

InAmpPrsnt

Stereo

4

R

3

R

2

R

1

R

0

R

7.15.1. Mixer (NID = 1Dh): InAmpCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Dh

Field Name

Bits

R/W

Default

1h

Reset

N/A (Hard-coded)

Mute

31

R

Mute support: 1 = yes, 0 = no.

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

Rsvd3

30:23

R

00h

N/A (Hard-coded)

Reserved.

22:16

StepSize

Rsvd2

R

05h

N/A (Hard-coded)

Size of each step in the gain range: 0 to 127 = .25dB to 32dB, in .25dB steps.

15

R

0h

N/A (Hard-coded)

Reserved.

14:8

NumSteps

Rsvd1

R

1Fh

N/A (Hard-coded)

Number of gains steps (number of possible settings - 1).

7

R

0h

N/A (Hard-coded)

Reserved.

6:0

Offset

R

17h

N/A (Hard-coded)

Indicates which step is 0dB

7.15.2. Mixer (NID = 1Dh): ConLst

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Eh

Field Name

Bits

R/W

Default

Reset

Rsvd

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

LForm

ConL

R

0h

N/A (Hard-coded)

Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)

NID entries.

6:0

R

03h

N/A (Hard-coded)

Number of NID entries in connection list.

184

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7.15.3. Mixer (NID = 1Dh): ConLstEntry0

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0200h

Field Name

Bits

R/W

Default

Reset

ConL3

31:24

Unused

23:16

R

00h

N/A (Hard-coded)

ConL2

R

12h

N/A (Hard-coded)

CD widget (0x12). Uses InAmpLeft4/InAmpRight4 controls.

15 1h N/A (Hard-coded)

ConL0..ConL1 define a range of selectable input

14:8 2Bh N/A (Hard-coded)

Inport3 Mux widget (0x2B). Uses InAmpLeft3/InAmpRight3 controls

7:0 28h N/A (Hard-coded)

Port C Pin widget (0x0C). Uses InAmpLeft0/InAmpRight0 controls.

ConL1Range

ConL1

R

ConL0

R

7.15.4. Mixer (NID = 1Dh): InAmpLeft0

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

360h

Get

B2000h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

Mute

RW

1h

POR - DAFG - ULR

Amp mute: 1 = muted, 0 = not muted.

185

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Field Name

Bits

R/W

Default

Reset

Rsvd1

6:5

R

0h

N/A (Hard-coded)

Reserved.

4:0

Gain

RW

17h

POR - DAFG - ULR

Amp gain step number (see InAmpCap parameter pertaining to this widget).

7.15.5. Mixer (NID = 1Dh): InAmpRight0

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

350h

Get

B0000h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

POR - DAFG - ULR

N/A (Hard-coded)

POR - DAFG - ULR

Reserved.

7

Mute

Rsvd1

Gain

RW

1h

Amp mute: 1 = muted, 0 = not muted.

6:5

R

0h

Reserved.

4:0

RW

17h

Amp gain step number (see InAmpCap parameter pertaining to this widget).

7.15.6. Mixer (NID = 1Dh): InAmpLeft1

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

361h

Get

B2001h

186

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Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

Mute

Rsvd1

Gain

RW

1h

POR - DAFG - ULR

N/A (Hard-coded)

POR - DAFG - ULR

Amp mute: 1 = muted, 0 = not muted.

6:5

R

0h

Reserved.

4:0

RW

17h

Amp gain step number (see InAmpCap parameter pertaining to this widget).

7.15.7. Mixer (NID = 1Dh): InAmpRight1

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

351h

Get

B0001h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

POR - DAFG - ULR

N/A (Hard-coded)

POR - DAFG - ULR

Reserved.

7

Mute

Rsvd1

Gain

RW

1h

Amp mute: 1 = muted, 0 = not muted.

6:5

R

0h

Reserved.

4:0

RW

17h

Amp gain step number (see InAmpCap parameter pertaining to this widget).

187

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7.15.8. Mixer (NID = 1Dh): InAmpLeft2

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

362h

Get

B2002h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

POR - DAFG - ULR

N/A (Hard-coded)

POR - DAFG - ULR

Reserved.

7

Mute

Rsvd1

Gain

RW

1h

Amp mute: 1 = muted, 0 = not muted.

6:5

R

0h

Reserved.

4:0

RW

17h

Amp gain step number (see InAmpCap parameter pertaining to this widget).

7.15.9. Mixer (NID = 1Dh): InAmpRight2

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

352h

Get

B0002h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

POR - DAFG - ULR

N/A (Hard-coded)

Reserved.

7

Mute

RW

1h

Amp mute: 1 = muted, 0 = not muted.

Rsvd1

6:5

R

0h

Reserved.

188

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

Gain

4:0

RW

17h

POR - DAFG - ULR

Amp gain step number (see InAmpCap parameter pertaining to this widget).

7.15.10. Mixer (NID = 1Dh): InAmpLeft3

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

363h

Get

B2003h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

POR - DAFG - ULR

N/A (Hard-coded)

POR - DAFG - ULR

Reserved.

7

Mute

Rsvd1

Gain

RW

1h

Amp mute: 1 = muted, 0 = not muted.

6:5

R

0h

Reserved.

4:0

RW

17h

Amp gain step number (see InAmpCap parameter pertaining to this widget).

7.15.11. Mixer (NID = 1Dh): InAmpRight3

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

353h

Get

B0003h

Field Name

Bits

R/W

Default

Reset

N/A (Hard-coded)

Rsvd2

31:8

R

000000h

Reserved.

189

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Field Name

Bits

R/W

Default

Reset

Mute

7

RW

1h

POR - DAFG - ULR

Amp mute: 1 = muted, 0 = not muted.

Rsvd1

Gain

6:5

R

0h

N/A (Hard-coded)

Reserved.

4:0

RW

17h

POR - DAFG - ULR

Amp gain step number (see InAmpCap parameter pertaining to this widget).

7.15.12. Mixer (NID = 1Dh): InAmpLeft4

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

364h

Get

B2004h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

POR - DAFG - ULR

N/A (Hard-coded)

POR - DAFG - ULR

Reserved.

7

Mute

Rsvd1

Gain

RW

1h

Amp mute: 1 = muted, 0 = not muted.

6:5

R

0h

Reserved.

4:0

RW

17h

Amp gain step number (see InAmpCap parameter pertaining to this widget).

7.15.13. Mixer (NID = 1Dh): InAmpRight4

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

354h

Get

B0004h

190

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

Mute

Rsvd1

Gain

RW

1h

POR - DAFG - ULR

N/A (Hard-coded)

POR - DAFG - ULR

Amp mute: 1 = muted, 0 = not muted.

6:5

R

0h

Reserved.

4:0

RW

17h

Amp gain step number (see InAmpCap parameter pertaining to this widget).

7.15.14. Mixer (NID = 1Dh): PwrState

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

705h

Get

F0500h

Field Name

Bits

R/W

Default

Reset

Rsvd4

31:11

Reserved.

10

R

000000h

N/A (Hard-coded)

SettingsReset

R

1h

POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

Rsvd3

Error

9

R

0h

N/A (Hard-coded)

Reserved.

8

R

0h

POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

191

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Field Name

Bits

R/W

Default

Reset

Rsvd2

7:6

R

0h

N/A (Hard-coded)

Reserved.

5:4

Act

R

3h

POR - DAFG - LR

N/A (Hard-coded)

POR - DAFG - LR

Actual power state of this widget.

Rsvd1

Set

3:2

R

0h

Reserved.

1:0

RW

0h

Current power state setting for this widget.

192

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Eight channel HD Audio codec optimized for low power

7.16. MixerOutVol (NID = 1Eh): WCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0009h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:24

R

00h

N/A (Hard-coded)

Reserved.

23:20

Type

R

3h

N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay

19:16

R

0h

N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1

15:12

Reserved.

11

R

0h

SwapCap

PwrCntrl

Dig

R

0h

Left/right swap support: 1 = yes, 0 = no.

10 1h

Power state support: 1 = yes, 0 = no.

0h

Digital stream support: 1 = yes (digital), 0 = no (analog).

1h N/A (Hard-coded)

R

9

R

ConnList

8

R

Connection list present: 1 = yes, 0 = no.

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Field Name

Bits

R/W

Default

Reset

UnSolCap

7

R

0h

N/A (Hard-coded)

Unsolicited response support: 1 = yes, 0 = no.

0h

Processing state support: 1 = yes, 0 = no.

0h

Striping support: 1 = yes, 0 = no.

0h

Stream format override: 1 = yes, 0 = no.

1h

Amplifier capabilities override: 1 = yes, no.

1h

Output amp present: 1 = yes, 0 = no.

0h

Input amp present: 1 = yes, 0 = no.

1h

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

ProcWidget

Stripe

6

R

N/A (Hard-coded)

5

R

FormatOvrd

AmpParOvrd

OutAmpPrsnt

InAmpPrsnt

Stereo

4

R

3

R

2

R

1

R

0

R

7.16.1. MixerOutVol (NID = 1Eh): ConLst

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Eh

Field Name

Bits

R/W

Default

Reset

N/A (Hard-coded)

Rsvd

31:8

R

000000h

Reserved.

194

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Field Name

Bits

R/W

Default

Reset

LForm

7

R

0h

N/A (Hard-coded)

Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)

NID entries.

ConL

6:0

R

01h

N/A (Hard-coded)

Number of NID entries in connection list.

7.16.2. MixerOutVol (NID = 1Eh): ConLstEntry0

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0200h

Field Name

Bits

R/W

Default

Reset

ConL3

31:24

R

00h

N/A (Hard-coded)

Unused list entry.

23:16

Unused list entry.

15:8

Unused list entry.

7:0

ConL2

ConL1

ConL0

R

00h

1Dh

N/A (Hard-coded)

R

Mixer Summing widget (0x1D)

7.16.3. MixerOutVol (NID = 1Dh): OutAmpCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0012h

195

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

Mute

31

R

1h

N/A (Hard-coded)

Mute support: 1 = yes, 0 = no.

Rsvd3

30:23

R

00h

N/A (Hard-coded)

Reserved.

22:16

StepSize

Rsvd2

R

05h

Size of each step in the gain range: 0 to 127 = .25dB to 32dB, in .25dB steps.

15

R

0h

N/A (Hard-coded)

Reserved.

14:8

NumSteps

Rsvd1

R

1Fh

N/A (Hard-coded)

Number of gains steps (number of possible settings - 1).

7

R

0h

N/A (Hard-coded)

Reserved.

6:0

Offset

R

1Fh

N/A (Hard-coded)

Indicates which step is 0dB

7.16.4. MixerOutVol (NID = 1Dh): OutAmpLeft

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

3A0h

Get

BA000h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

Mute

RW

1h

POR - DAFG - ULR

Amp mute: 1 = muted, 0 = not muted.

196

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

Rsvd1

6:5

R

0h

N/A (Hard-coded)

Reserved.

4:0

Gain

RW

1Fh

POR - DAFG - ULR

Amp gain step number (see OutAmpCap parameter pertaining to this widget).

7.16.5. MixerOutVol (NID = 1Dh): OutAmpRight

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

390h

Get

B8000h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

POR - DAFG - ULR

N/A (Hard-coded)

POR - DAFG - ULR

Reserved.

7

Mute

Rsvd1

Gain

RW

1h

Amp mute: 1 = muted, 0 = not muted.

6:5

R

0h

Reserved.

4:0

RW

1Fh

Amp gain step number (see OutAmpCap parameter pertaining to this widget).

7.16.6. MixerOutVol (NID = 1Dh): PwrState

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

705h

Get

F0500h

197

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

Rsvd4

31:11

Reserved.

10

R

000000h

N/A (Hard-coded)

SettingsReset

R

1h

POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

Rsvd3

Error

9

R

0h

N/A (Hard-coded)

Reserved.

8

R

0h

POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

Rsvd2

Act

7:6

R

0h

N/A (Hard-coded)

POR - DAFG - LR

N/A (Hard-coded)

POR - DAFG - LR

Reserved.

5:4

R

3h

Actual power state of this widget.

Rsvd1

Set

3:2

R

0h

Reserved.

1:0

RW

0h

Current power state setting for this widget.

198

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7.17. Vendor Reserved (NID = 1Fh)

199

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7.18. PortH (NID = 11h): WCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0009h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:24

R

00h

N/A (Hard-coded)

Reserved.

23:20

Type

R

4h

N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay

19:16

R

0h

N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1

15:12

Reserved.

11

R

0h

SwapCap

PwrCntrl

Dig

R

0h

Left/right swap support: 1 = yes, 0 = no.

10 1h

Power state support: 1 = yes, 0 = no.

0h

Digital stream support: 1 = yes (digital), 0 = no (analog).

1h N/A (Hard-coded)

R

9

R

ConnList

8

R

Connection list present: 1 = yes, 0 = no.

200

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

UnSolCap

7

R

1h

N/A (Hard-coded)

Unsolicited response support: 1 = yes, 0 = no.

0h

Processing state support: 1 = yes, 0 = no.

0h

Striping support: 1 = yes, 0 = no.

0h

Stream format override: 1 = yes, 0 = no.

0h

Amplifier capabilities override: 1 = yes, no.

0h

Output amp present: 1 = yes, 0 = no.

1h

Input amp present: 1 = yes, 0 = no.

1h

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

ProcWidget

Stripe

6

R

N/A (Hard-coded)

5

R

FormatOvrd

AmpParOvrd

OutAmpPrsnt

InAmpPrsnt

Stereo

4

R

3

R

2

R

1

R

0

R

7.18.1. PortH (NID = 11h): PinCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Ch

Field Name

Bits

R/W

Default

Reset

N/A (Hard-coded)

Rsvd2

31:17

R

0000h

Reserved.

201

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Field Name

Bits

R/W

Default

Reset

EapdCap

16

R

1h

N/A (Hard-coded)

EAPD support: 1 = yes, 0 = no.

VrefCntrl

15:8

R

00h

N/A (Hard-coded)

Vref support:

bit 7 = Reserved

bit 6 = Reserved

bit 5 = 100% support (1 = yes, 0 = no)

bit 4 = 80% support (1 = yes, 0 = no)

bit 3 = Reserved

bit 2 = GND support (1 = yes, 0 = no)

bit 1 = 50% support (1 = yes, 0 = no)

bit 0 = Hi-Z support (1 = yes, 0 = no)

Rsvd1

7

R

0h

N/A (Hard-coded)

Reserved.

6

BalancedIO

InCap

R

0h

Balanced I/O support: 1 = yes, 0 = no.

1h

Input support: 1 = yes, 0 = no.

1h

Output support: 1 = yes, 0 = no.

0h

Headphone amp present: 1 = yes, 0 = no.

1h

Presence detection support: 1 = yes, 0 = no.

0h

Trigger required for impedance sense: 1 = yes, 0 = no.

0h N/A (Hard-coded)

5

R

OutCap

4

R

HdphDrvCap

PresDtctCap

TrigRqd

3

R

2

R

1

R

ImpSenseCap

0

R

Impedance sense support: 1 = yes, 0 = no.

202

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Eight channel HD Audio codec optimized for low power

7.18.2. PortH (NID = 11h): ConLst

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Eh

Field Name

Bits

R/W

Default

Reset

Rsvd

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

LForm

ConL

R

0h

N/A (Hard-coded)

Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)

NID entries.

6:0

R

04h

N/A (Hard-coded)

Number of NID entries in connection list.

7.18.3. PortH (NID = 11h): ConLstEntry0

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0200h

Field Name

Bits

R/W

Default

Reset

ConL3

31:24

R

19h

N/A (Hard-coded)

DAC4 Converter widget (0x19)

23:16 1Eh

MixerOutVol Selector widget (0x1E)

14:8 1h

ConL2

R

N/A (Hard-coded)

ConL1Range

R

1 = ConL0..ConL1 defines a range of selectable inputs.

203

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Field Name

Bits

R/W

Default

Reset

ConL1

15:8

R

18h

N/A (Hard-coded)

DAC3 Converter widget (0x18)

7:0 15h

DAC0 Converter widget (0x15)

ConL0

R

N/A (Hard-coded)

7.18.4. PortH (NID = 11h): InAmpLeft

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

360h

Get

B2000h

Field Name

Bits

R/W

Default

Reset

Rsvd1

31:2

R

00000000h

N/A (Hard-coded)

Reserved.

1:0

Gain

RW

0h

POR - DAFG - ULR

Amp gain step number (see InAmpCap parameter pertaining to this widget).

7.18.5. PortH (NID = 11h): InAmpRight

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

350h

Get

B0000h

Field Name

Bits

R/W

Default

Reset

Rsvd1

31:2

R

00000000h

N/A (Hard-coded)

Reserved.

1:0

Gain

RW

0h

POR - DAFG - ULR

Amp gain step number (see InAmpCap parameter pertaining to this widget).

204

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7.18.6. PortH (NID = 11h): ConSelectCtrl

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

701h

Get

F0100h

Field Name

Bits

R/W

Default

Reset

Rsvd

31:2

R

00000000h

N/A (Hard-coded)

Reserved.

1:0

Index

RW

0h

POR - DAFG - ULR

Connection select control index.

7.18.7. PortH (NID = 11h): PwrState

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

705h

Get

F0500h

Field Name

Bits

R/W

Default

Reset

Rsvd4

31:11

Reserved.

10

R

000000h

N/A (Hard-coded)

SettingsReset

R

1h

POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

Rsvd3

Error

9

R

0h

N/A (Hard-coded)

Reserved.

8

R

0h

POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

205

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Field Name

Bits

R/W

Default

Reset

Rsvd2

7:6

R

0h

N/A (Hard-coded)

Reserved.

5:4

Act

R

3h

POR - DAFG - LR

N/A (Hard-coded)

POR - DAFG - LR

Actual power state of this widget.

Rsvd1

Set

3:2

R

0h

Reserved.

1:0

RW

0h

Current power state setting for this widget.

7.18.8. PortH (NID = 11h): PinWCntrl

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

707h

Get

F0700h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:7

R

000000h

N/A (Hard-coded)

Reserved.

6

OutEn

InEn

RW

0h

POR - DAFG - ULR

N/A (Hard-coded)

Output enable: 1 = enabled, 0 = disabled.

RW 1h

Input enable: 1 = enabled, 0 = disabled.

5

Rsvd1

4:0

R

00h

Reserved.

206

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7.18.9. PortH (NID = 11h): UnsolResp

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

708h

Get

F0800h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

En

RW

0h

POR - DAFG - ULR

Unsolicited response enable (also enables Wake events for this Widget): 1 =

enabled, 0 = disabled.

Rsvd1

Tag

6

R

0h

N/A (Hard-coded)

Reserved.

5:0

RW

00h

POR - DAFG - ULR

Software programmable field returned in top six bits (31:26) of every Unsolicit-

ed Response generated by this node.

7.18.10. PortH (NID = 11h): ChSense

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

709h

Get

F0900h

Field Name

Bits

R/W

Default

0h

Reset

PresDtct

31

R

POR

Presence detection indicator: 1 = presence detected; 0 = presence not detect-

ed.

Rsvd

30:0

R

00000000h

N/A (Hard-coded)

Reserved.

207

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Eight channel HD Audio codec optimized for low power

7.18.11. PortH (NID = 11h): EAPDBTLLR

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

70Ch

Get

F0C00h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:2

R

00000000h

N/A (Hard-coded)

Reserved.

1

EAPD

Rsvd1

RW

1h

POR - DAFG - ULR

EAPD control: 1 = set EAPD pin to 1 (powered) up if this pin is powered up, 0

= set EAPD pin to 0.

0

R

0h

N/A (Hard-coded)

Reserved.

7.18.12. PortH (NID = 11h): ConfigDefault

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

71Dh

Byte 1 (Bits 7:0)

71Fh

71Eh

71Ch

Get

F1F00h / F1E00h / F1D00h / F1C00h

Field Name

Bits

R/W

Default

Reset

PortConnectivity

31:30

RW

0h

POR

Port connectivity:

0h = Port complex is connected to a jack

1h = No physical connection for port

2h = Fixed function device is attached

3h = Both jack and internal device attached (info in all other fields refers to in-

tegrated device, any presence detection refers to jack)

208

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Field Name

Bits

R/W

Default

Reset

Location

29:24

RW

01h

POR

Location

Bits [5..4]:

0h = External on primary chassis

1h = Internal

2h = Separate chassis

3h = Other

Bits [3..0]:

0h = N/A

1h = Rear

2h = Front

3h = Left

4h = Right

5h = Top

6h = Bottom

7h-9h = Special

Ah-Fh = Reserved

Device

23:20

RW

0h

POR

Default device:

0h = Line out

1h = Speaker

2h = HP out

3h = CD

4h = SPDIF Out

5h = Digital other out

6h = Modem line side

7h = Modem handset side

8h = Line in

9h = Aux

Ah = Mic in

Bh = Telephony

Ch = SPDIF In

Dh = Digital other in

Eh = Reserved

Fh = Other

209

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

ConnectionType

19:16

RW

1h

POR

Connection type:

0h = Unknown

1h = 1/8" stereo/mono

2h = 1/4" stereo/mono

3h = ATAPI internal

4h = RCA

5h = Optical

6h = Other digital

7h = Other analog

8h = Multichannel analog (DIN)

9h = XLR/Professional

Ah = RJ-11 (modem)

Bh = Combination

Ch-Eh = Reserved

Fh = Other

Color

15:12

RW

2h

POR

Color:

0h = Unknown

1h = Black

2h = Grey

3h = Blue

4h = Green

5h = Red

6h = Orange

7h = Yellow

8h = Purple

9h = Pink

Ah-Dh = Reserved

Eh = White

Fh = Other

Misc

11:8

RW

0h

POR

Miscellaneous:

Bits [3..1] = Reserved

Bit 0 = Jack detect override

Association

Sequence

7:4

RW

3h

4h

POR

Default assocation.

3:0

RW

Sequence.

210

V1.1 06/11

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Eight channel HD Audio codec optimized for low power

7.19. CD (NID = 12h): WCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0009h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:24

R

00h

N/A (Hard-coded)

Reserved.

23:20

Type

R

4h

N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay

19:16

R

0h

N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1

15:12

Reserved.

11

R

0h

SwapCap

PwrCntrl

DigitalStrm

ConnList

R

0h

Left/right swap support: 1 = yes, 0 = no.

10 1h

Power state support: 1 = yes, 0 = no.

0h

Digital stream support: 1 = yes (digital), 0 = no (analog).

0h N/A (Hard-coded)

R

9

R

8

R

Connection list present: 1 = yes, 0 = no.

211

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Field Name

Bits

R/W

Default

Reset

UnsolCap

7

R

1h

N/A (Hard-coded)

Unsolicited response support: 1 = yes, 0 = no.

0h

Processing state support: 1 = yes, 0 = no.

0h

Striping support: 1 = yes, 0 = no.

0h

Stream format override: 1 = yes, 0 = no.

0h

Amplifier capabilities override: 1 = yes, no.

0h

Output amp present: 1 = yes, 0 = no.

0h

Input amp present: 1 = yes, 0 = no.

1h

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

ProcWidget

Stripe

6

R

N/A (Hard-coded)

5

R

FormatOvrd

AmpParOvrd

OutAmpPrsnt

InAmpPrsnt

Stereo

4

R

3

R

2

R

1

R

0

R

7.19.1. CD (NID = 12h): PinCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Ch

Field Name

Bits

R/W

Default

Reset

N/A (Hard-coded)

Rsvd2

31:17

R

0000h

Reserved.

212

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

EapdCap

16

R

0h

N/A (Hard-coded)

EAPD support: 1 = yes, 0 = no.

VRefCntrl

15:8

R

00h

N/A (Hard-coded)

Vref support:

bit 7 = Reserved

bit 6 = Reserved

bit 5 = 100% support (1 = yes, 0 = no)

bit 4 = 80% support (1 = yes, 0 = no)

bit 3 = Reserved

bit 2 = GND support (1 = yes, 0 = no)

bit 1 = 50% support (1 = yes, 0 = no)

bit 0 = Hi-Z support (1 = yes, 0 = no)

Rsvd1

7

R

0h

N/A (Hard-coded)

Reserved.

6

BalancedIO

InCap

R

0h

Balanced I/O support: 1 = yes, 0 = no.

1h

Input support: 1 = yes, 0 = no.

0h

Output support: 1 = yes, 0 = no.

0h

Headphone amp present: 1 = yes, 0 = no.

0h

Presence detection support: 1 = yes, 0 = no.

0h

Trigger required for impedance sense: 1 = yes, 0 = no.

0h N/A (Hard-coded)

5

R

OutCap

4

R

HPhnDrvCap

PresDtctCap

TrigRqd

3

R

2

R

1

R

ImpSenseCap

0

R

Impedance sense support: 1 = yes, 0 = no.

213

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7.19.2. CD (NID = 12h): PwrState

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

705h

Get

F0500h

Field Name

Bits

R/W

Default

Reset

Rsvd4

31:11

Reserved.

10

R

000000h

N/A (Hard-coded)

SettingsReset

R

1h

POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

Rsvd3

Error

9

R

0h

N/A (Hard-coded)

Reserved.

8

R

0h

POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

Rsvd2

Act

7:6

R

0h

N/A (Hard-coded)

POR - DAFG - LR

N/A (Hard-coded)

POR - DAFG - LR

Reserved.

5:4

R

3h

Actual power state of this widget.

Rsvd1

Set

3:2

R

0h

Reserved.

1:0

RW

0h

Current power state setting for this widget.

7.19.3. CD (NID = 12h): PinWCntrl

Reg

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

707h

Set

214

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Eight channel HD Audio codec optimized for low power

7.19.3. CD (NID = 12h): PinWCntrl

Reg

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0700h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:6

R

0000000h

N/A (Hard-coded)

POR - DAFG - ULR

N/A (Hard-coded)

Reserved.

5

InEn

RW

0h

Input enable: 1 = enabled, 0 = disabled.

Rsvd1

4:0

R

00h

Reserved.

7.19.4. CD (NID = 12h): ConfigDefault

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

71Dh

Byte 1 (Bits 7:0)

71Fh

71Eh

71Ch

Get

F1F00h / F1E00h / F1D00h / F1C00h

Field Name

Bits

R/W

Default

Reset

PortConnectivity

31:30

RW

2h

POR

Port connectivity:

0h = Port complex is connected to a jack

1h = No physical connection for port

2h = Fixed function device is attached

3h = Both jack and internal device attached (info in all other fields refers to in-

tegrated device, any presence detection refers to jack)

215

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

Location

29:24

RW

19h

POR

Location

Bits [5..4]:

0h = External on primary chassis

1h = Internal

2h = Separate chassis

3h = Other

Bits [3..0]:

0h = N/A

1h = Rear

2h = Front

3h = Left

4h = Right

5h = Top

6h = Bottom

7h-9h = Special

Ah-Fh = Reserved

Device

23:20

RW

3h

POR

Default device:

0h = Line out

1h = Speaker

2h = HP out

3h = CD

4h = SPDIF Out

5h = Digital other out

6h = Modem line side

7h = Modem handset side

8h = Line in

9h = Aux

Ah = Mic in

Bh = Telephony

Ch = SPDIF In

Dh = Digital other in

Eh = Reserved

Fh = Other

216

V1.1 06/11

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

ConnectionType

19:16

RW

3h

POR

Connection type:

0h = Unknown

1h = 1/8" stereo/mono

2h = 1/4" stereo/mono

3h = ATAPI internal

4h = RCA

5h = Optical

6h = Other digital

7h = Other analog

8h = Multichannel analog (DIN)

9h = XLR/Professional

Ah = RJ-11 (modem)

Bh = Combination

Ch-Eh = Reserved

Fh = Other

Color

15:12

RW

0h

POR

Color:

0h = Unknown

1h = Black

2h = Grey

3h = Blue

4h = Green

5h = Red

6h = Orange

7h = Yellow

8h = Purple

9h = Pink

Ah-Dh = Reserved

Eh = White

Fh = Other

Misc

11:8

RW

1h

POR

Miscellaneous:

Bits [3..1] = Reserved

Bit 0 = Jack detect override

Association

Sequence

7:4

RW

4h

1h

POR

Default assocation.

3:0

RW

Sequence.

217

V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

7.20. DMic0 (NID = 13h): WCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0009h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:24

R

00h

N/A (Hard-coded)

Reserved.

23:20

Type

R

Fh

N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay

19:16

R

0h

N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1

15:12

Reserved.

11

R

0h

SwapCap

PwrCntrl

DigitalStrm

ConnList

R

0h

Left/right swap support: 1 = yes, 0 = no.

10 0h

Power state support: 1 = yes, 0 = no.

0h

Digital stream support: 1 = yes (digital), 0 = no (analog).

0h N/A (Hard-coded)

R

9

R

8

R

Connection list present: 1 = yes, 0 = no.

218

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

UnsolCap

7

R

0h

N/A (Hard-coded)

Unsolicited response support: 1 = yes, 0 = no.

0h

Processing state support: 1 = yes, 0 = no.

0h

Striping support: 1 = yes, 0 = no.

0h

Stream format override: 1 = yes, 0 = no.

0h

Amplifier capabilities override: 1 = yes, no.

0h

Output amp present: 1 = yes, 0 = no.

0h

Input amp present: 1 = yes, 0 = no.

0h

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

ProcWidget

Stripe

6

R

N/A (Hard-coded)

5

R

FormatOvrd

AmpParOvrd

OutAmpPrsnt

InAmpPrsnt

Stereo

4

R

3

R

2

R

1

R

0

R

7.20.1. DMic0 (NID = 13h): PinCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Ch

Field Name

Bits

R/W

Default

Reset

N/A (Hard-coded)

Rsvd2

31:17

R

0000h

Reserved.

219

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

EapdCap

16

R

0h

N/A (Hard-coded)

EAPD support: 1 = yes, 0 = no.

VRefCntrl

15:8

R

00h

N/A (Hard-coded)

Vref support:

bit 7 = Reserved

bit 6 = Reserved

bit 5 = 100% support (1 = yes, 0 = no)

bit 4 = 80% support (1 = yes, 0 = no)

bit 3 = Reserved

bit 2 = GND support (1 = yes, 0 = no)

bit 1 = 50% support (1 = yes, 0 = no)

bit 0 = Hi-Z support (1 = yes, 0 = no)

Rsvd1

7

R

0h

N/A (Hard-coded)

Reserved.

6

BalancedIO

InCap

R

0h

Balanced I/O support: 1 = yes, 0 = no.

1h

Input support: 1 = yes, 0 = no.

0h

Output support: 1 = yes, 0 = no.

0h

Headphone amp present: 1 = yes, 0 = no.

0h

Presence detection support: 1 = yes, 0 = no.

0h

Trigger required for impedance sense: 1 = yes, 0 = no.

0h N/A (Hard-coded)

5

R

OutCap

4

R

HPhnDrvCap

PresDtctCap

TrigRqd

3

R

2

R

1

R

ImpSenseCap

0

R

Impedance sense support: 1 = yes, 0 = no.

220

V1.1 06/11

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Eight channel HD Audio codec optimized for low power

7.20.2. DMic0 (NID = 13h): InAmpLeft

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

360h

Get

B2000h

Field Name

Bits

R/W

Default

Reset

Rsvd1

31:2

R

00000000h

N/A (Hard-coded)

Reserved.

1:0

Gain

RW

0h

POR - DAFG - ULR

Amp gain step number (see InAmpCap parameter pertaining to this widget).

7.20.3. DMic0 (NID = 13h): InAmpRight

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

350h

Get

B0000h

Field Name

Bits

R/W

Default

Reset

Rsvd1

31:2

R

00000000h

N/A (Hard-coded)

Reserved.

1:0

Gain

RW

0h

POR - DAFG - ULR

Amp gain step number (see InAmpCap parameter pertaining to this widget).

7.20.4. DMic0 (NID = 13h): PwrState

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

705h

Get

F0500h

221

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

Rsvd4

31:11

Reserved.

10

R

000000h

N/A (Hard-coded)

SettingsReset

R

1h

POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

Rsvd3

Error

9

R

0h

N/A (Hard-coded)

Reserved.

8

R

0h

POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

Rsvd2

Act

7:6

R

0h

N/A (Hard-coded)

POR - DAFG - LR

N/A (Hard-coded)

POR - DAFG - LR

Reserved.

5:4

R

3h

Actual power state of this widget.

Rsvd1

Set

3:2

R

0h

Reserved.

1:0

RW

0h

Current power state setting for this widget.

7.20.5. DMic0 (NID = 13h): PinWCntrl

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

707h

Get

F0700h

222

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:6

R

0000000h

N/A (Hard-coded)

Reserved.

5

InEn

RW

0h

POR - DAFG - ULR

N/A (Hard-coded)

Input enable: 1 = enabled, 0 = disabled.

Rsvd1

4:0

R

00h

Reserved.

7.20.6. DMic0 (NID = 13h): UnsolResp

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

708h

Get

F0800h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

En

RW

0h

POR - DAFG - ULR

Unsolicited response enable (also enables Wake events for this Widget): 1 =

enabled, 0 = disabled.

Rsvd1

Tag

6

R

0h

N/A (Hard-coded)

Reserved.

5:0

RW

00h

POR - DAFG - ULR

Software programmable field returned in top six bits (31:26) of every Unsolicit-

ed Response generated by this node.

7.20.7. DMic0 (NID = 13h): ConfigDefault

Reg

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Set

71Fh

71Eh

71Dh

71Ch

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7.20.7. DMic0 (NID = 13h): ConfigDefault

Reg

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F1F00h / F1E00h / F1D00h / F1C00h

Field Name

Bits

R/W

Default

Reset

PortConnectivity

31:30

RW

2h

POR

Port connectivity:

0h = Port complex is connected to a jack

1h = No physical connection for port

2h = Fixed function device is attached

3h = Both jack and internal device attached (info in all other fields refers to in-

tegrated device, any presence detection refers to jack)

Location

29:24

RW

10h

POR

Location

Bits [5..4]:

0h = External on primary chassis

1h = Internal

2h = Separate chassis

3h = Other

Bits [3..0]:

0h = N/A

1h = Rear

2h = Front

3h = Left

4h = Right

5h = Top

6h = Bottom

7h-9h = Special

Ah-Fh = Reserved

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Field Name

Bits

R/W

Default

Reset

Device

23:20

RW

Ah

POR

Default device:

0h = Line out

1h = Speaker

2h = HP out

3h = CD

4h = SPDIF Out

5h = Digital other out

6h = Modem line side

7h = Modem handset side

8h = Line in

9h = Aux

Ah = Mic in

Bh = Telephony

Ch = SPDIF In

Dh = Digital other in

Eh = Reserved

Fh = Other

ConnectionType

19:16

RW

3h

POR

Connection type:

0h = Unknown

1h = 1/8" stereo/mono

2h = 1/4" stereo/mono

3h = ATAPI internal

4h = RCA

5h = Optical

6h = Other digital

7h = Other analog

8h = Multichannel analog (DIN)

9h = XLR/Professional

Ah = RJ-11 (modem)

Bh = Combination

Ch-Eh = Reserved

Fh = Other

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Field Name

Bits

R/W

Default

Reset

Color

15:12

RW

0h

POR

Color:

0h = Unknown

1h = Black

2h = Grey

3h = Blue

4h = Green

5h = Red

6h = Orange

7h = Yellow

8h = Purple

9h = Pink

Ah-Dh = Reserved

Eh = White

Fh = Other

Misc

11:8

RW

1h

POR

Miscellaneous:

Bits [3..1] = Reserved

Bit 0 = Jack detect override

Association

Sequence

7:4

RW

4h

2h

POR

Default assocation.

3:0

RW

Sequence.

226

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7.21. DMic1 (NID = 14h): WCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0009h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:24

R

00h

N/A (Hard-coded)

Reserved.

23:20

Type

R

Fh

N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay

19:16

R

0h

N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1

15:12

Reserved.

11

R

0h

SwapCap

PwrCntrl

DigitalStrm

ConnList

R

0h

Left/right swap support: 1 = yes, 0 = no.

10 0h

Power state support: 1 = yes, 0 = no.

0h

Digital stream support: 1 = yes (digital), 0 = no (analog).

0h N/A (Hard-coded)

R

9

R

8

R

Connection list present: 1 = yes, 0 = no.

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Field Name

Bits

R/W

Default

Reset

UnsolCap

7

R

0h

N/A (Hard-coded)

Unsolicited response support: 1 = yes, 0 = no.

0h

Processing state support: 1 = yes, 0 = no.

0h

Striping support: 1 = yes, 0 = no.

0h

Stream format override: 1 = yes, 0 = no.

0h

Amplifier capabilities override: 1 = yes, no.

0h

Output amp present: 1 = yes, 0 = no.

0h

Input amp present: 1 = yes, 0 = no.

0h

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

ProcWidget

Stripe

6

R

N/A (Hard-coded)

5

R

FormatOvrd

AmpParOvrd

OutAmpPrsnt

InAmpPrsnt

Stereo

4

R

3

R

2

R

1

R

0

R

7.21.1. DMic1 (NID = 14h): PinCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Ch

Field Name

Bits

R/W

Default

Reset

N/A (Hard-coded)

Rsvd2

31:17

R

0000h

Reserved.

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Field Name

Bits

R/W

Default

Reset

EapdCap

16

R

0h

N/A (Hard-coded)

EAPD support: 1 = yes, 0 = no.

VRefCntrl

15:8

R

00h

N/A (Hard-coded)

Vref support:

bit 7 = Reserved

bit 6 = Reserved

bit 5 = 100% support (1 = yes, 0 = no)

bit 4 = 80% support (1 = yes, 0 = no)

bit 3 = Reserved

bit 2 = GND support (1 = yes, 0 = no)

bit 1 = 50% support (1 = yes, 0 = no)

bit 0 = Hi-Z support (1 = yes, 0 = no)

Rsvd1

7

R

0h

N/A (Hard-coded)

Reserved.

6

BalancedIO

InCap

R

0h

Balanced I/O support: 1 = yes, 0 = no.

1h

Input support: 1 = yes, 0 = no.

0h

Output support: 1 = yes, 0 = no.

0h

Headphone amp present: 1 = yes, 0 = no.

0h

Presence detection support: 1 = yes, 0 = no.

0h

Trigger required for impedance sense: 1 = yes, 0 = no.

0h N/A (Hard-coded)

5

R

OutCap

4

R

HPhnDrvCap

PresDtctCap

TrigRqd

3

R

2

R

1

R

ImpSenseCap

0

R

Impedance sense support: 1 = yes, 0 = no.

229

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7.21.2. DMic1 (NID = 14h): InAmpLeft

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

360h

Get

B2000h

Field Name

Bits

R/W

Default

Reset

Rsvd1

31:2

R

00000000h

N/A (Hard-coded)

Reserved.

1:0

Gain

RW

0h

POR - DAFG - ULR

Amp gain step number (see InAmpCap parameter pertaining to this widget).

7.21.3. DMic1 (NID = 14h): InAmpRight

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

350h

Get

B0000h

Field Name

Bits

R/W

Default

Reset

Rsvd1

31:2

R

00000000h

N/A (Hard-coded)

Reserved.

1:0

Gain

RW

0h

POR - DAFG - ULR

Amp gain step number (see InAmpCap parameter pertaining to this widget).

7.21.4. DMic1 (NID = 14h): PwrState

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

705h

Get

F0500h

230

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Field Name

Bits

R/W

Default

Reset

Rsvd4

31:11

Reserved.

10

R

000000h

N/A (Hard-coded)

SettingsReset

R

1h

POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

Rsvd3

Error

9

R

0h

N/A (Hard-coded)

Reserved.

8

R

0h

POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

Rsvd2

Act

7:6

R

0h

N/A (Hard-coded)

POR - DAFG - LR

N/A (Hard-coded)

POR - DAFG - LR

Reserved.

5:4

R

3h

Actual power state of this widget.

Rsvd1

Set

3:2

R

0h

Reserved.

1:0

RW

0h

Current power state setting for this widget.

7.21.5. DMic1 (NID = 14h): PinWCntrl

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

707h

Get

F0700h

231

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Field Name

Bits

R/W

Default

Reset

Rsvd2

31:6

R

0000000h

N/A (Hard-coded)

Reserved.

5

InEn

RW

0h

POR - DAFG - ULR

N/A (Hard-coded)

Input enable: 1 = enabled, 0 = disabled.

Rsvd1

4:0

R

00h

Reserved.

7.21.6. DMic1 (NID = 14h): UnsolResp

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

708h

Get

F0800h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

En

RW

0h

POR - DAFG - ULR

Unsolicited response enable (also enables Wake events for this Widget): 1 =

enabled, 0 = disabled.

Rsvd1

Tag

6

R

0h

N/A (Hard-coded)

Reserved.

5:0

RW

00h

POR - DAFG - ULR

Software programmable field returned in top six bits (31:26) of every Unsolicit-

ed Response generated by this node.

7.21.7. DMic1 (NID = 14h): ConfigDefault

Reg

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Set

71Fh

71Eh

71Dh

71Ch

232

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7.21.7. DMic1 (NID = 14h): ConfigDefault

Reg

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F1F00h / F1E00h / F1D00h / F1C00h

Field Name

Bits

R/W

Default

Reset

PortConnectivity

31:30

RW

2h

POR

Port connectivity:

0h = Port complex is connected to a jack

1h = No physical connection for port

2h = Fixed function device is attached

3h = Both jack and internal device attached (info in all other fields refers to in-

tegrated device, any presence detection refers to jack)

Location

29:24

RW

10h

POR

Location

Bits [5..4]:

0h = External on primary chassis

1h = Internal

2h = Separate chassis

3h = Other

Bits [3..0]:

0h = N/A

1h = Rear

2h = Front

3h = Left

4h = Right

5h = Top

6h = Bottom

7h-9h = Special

Ah-Fh = Reserved

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Field Name

Bits

R/W

Default

Reset

Device

23:20

RW

Ah

POR

Default device:

0h = Line out

1h = Speaker

2h = HP out

3h = CD

4h = SPDIF Out

5h = Digital other out

6h = Modem line side

7h = Modem handset side

8h = Line in

9h = Aux

Ah = Mic in

Bh = Telephony

Ch = SPDIF In

Dh = Digital other in

Eh = Reserved

Fh = Other

ConnectionType

19:16

RW

3h

POR

Connection type:

0h = Unknown

1h = 1/8" stereo/mono

2h = 1/4" stereo/mono

3h = ATAPI internal

4h = RCA

5h = Optical

6h = Other digital

7h = Other analog

8h = Multichannel analog (DIN)

9h = XLR/Professional

Ah = RJ-11 (modem)

Bh = Combination

Ch-Eh = Reserved

Fh = Other

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Field Name

Bits

R/W

Default

Reset

Color

15:12

RW

0h

POR

Color:

0h = Unknown

1h = Black

2h = Grey

3h = Blue

4h = Green

5h = Red

6h = Orange

7h = Yellow

8h = Purple

9h = Pink

Ah-Dh = Reserved

Eh = White

Fh = Other

Misc

11:8

RW

1h

POR

Miscellaneous:

Bits [3..1] = Reserved

Bit 0 = Jack detect override

Association

Sequence

7:4

RW

4h

3h

POR

Default assocation.

3:0

RW

Sequence.

235

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7.22. DAC0 (NID = 15h): WCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0009h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:24

R

00h

N/A (Hard-coded)

Reserved.

23:20

Type

R

0h

N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay

19:16

R

Dh

N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1

15:12

Reserved.

11

R

0h

SwapCap

PwrCntrl

Dig

R

1h

Left/right swap support: 1 = yes, 0 = no.

10 1h

Power state support: 1 = yes, 0 = no.

0h

Digital stream support: 1 = yes (digital), 0 = no (analog).

0h N/A (Hard-coded)

R

9

R

ConnList

8

R

Connection list present: 1 = yes, 0 = no.

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Field Name

Bits

R/W

Default

Reset

UnSolCap

7

R

0h

N/A (Hard-coded)

Unsolicited response support: 1 = yes, 0 = no.

0h

Processing state support: 1 = yes, 0 = no.

0h

Striping support: 1 = yes, 0 = no.

0h

Stream format override: 1 = yes, 0 = no.

0h

Amplifier capabilities override: 1 = yes, no.

1h

Output amp present: 1 = yes, 0 = no.

0h

Input amp present: 1 = yes, 0 = no.

1h

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

ProcWidget

Stripe

6

R

N/A (Hard-coded)

5

R

FormatOvrd

AmpParOvrd

OutAmpPrsnt

InAmpPrsnt

Stereo

4

R

3

R

2

R

1

R

0

R

7.22.1. DAC0 (NID = 15h): Cnvtr

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

2h

Get

A0000h

Field Name

Bits

R/W

Default

Reset

N/A (Hard-coded)

Rsvd2

31:16

R

0000h

Reserved.

237

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Field Name

Bits

R/W

Default

Reset

StrmType

15

R

0h

N/A (Hard-coded)

Stream type: 1 = Non-PCM, 0 = PCM.

14 RW 0h

Sample base rate: 1 = 44.1kHz, 0 = 48kHz.

13:11 RW 0h

Sample base rate multiple:

FrmtSmplRate

SmplRateMultp

POR - DAFG - ULR

000b= x1 (48kHz/44.1kHz or less)

001b= x2 (96kHz/88.2kHz/32kHz)

010b= x3 (144kHz)

011b= x4 (192kHz/176.4kHz)

100b-111b Reserved

SmplRateDiv

10:8

RW

0h

POR - DAFG - ULR

Sample base rate divider:

000b= Divide by 1 (48kHz/44.1kHz)

001b= Divide by 2 (24kHz/20.05kHz)

010b= Divide by 3 (16kHz/32kHz)

011b= Divide by 4 (11.025kHz)

100b= Divide by 5 (9.6kHz)

101b= Divide by 6 (8kHz)

110b= Divide by 7

111b= Divide by 8 (6kHz)

Rsvd1

7

R

0h

3h

N/A (Hard-coded)

Reserved.

6:4

BitsPerSmpl

RW

POR - DAFG - ULR

Bits per sample:

000b= 8 bits

001b= 16 bits

010b= 20 bits

011b= 24 bits

100b= 32 bits

101b-111b= Reserved

NmbrChan

3:0

RW

1h

POR - DAFG - ULR

Total number of channels in the stream assigned to this converter:

0000b-1111b= 1-16 channels.

238

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7.22.2. DAC0 (NID = 15h): OutAmpLeft

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

3A0h

Get

BA000h

Field Name

Bits

R/W

Default

Reset

Rsvd

31:8

R

000000h

N/A (Hard-coded)

POR - DAFG - ULR

Reserved.

7

Mute

Gain

RW

1h

Amp mute: 1 = muted, 0 = not muted.

6:0 RW 7Fh

Amp gain step number (see OutAmpCap parameter pertaining to this widget).

7.22.3. DAC0 (NID = 15h): OutAmpRight

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

390h

Get

B8000h

Field Name

Bits

R/W

Default

Reset

Rsvd

31:8

R

000000h

N/A (Hard-coded)

POR - DAFG - ULR

Reserved.

7

Mute

Gain

RW

1h

Amp mute: 1 = muted, 0 = not muted.

6:0 RW 7Fh

Amp gain step number (see OutAmpCap parameter pertaining to this widget).

239

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7.22.4. DAC0 (NID = 15h): PwrState

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

705h

Get

F0500h

Field Name

Bits

R/W

Default

Reset

Rsvd4

31:11

Reserved.

10

R

000000h

N/A (Hard-coded)

SettingsReset

R

1h

POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

Rsvd3

Error

9

R

0h

N/A (Hard-coded)

Reserved.

8

R

0h

POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

Rsvd2

Act

7:6

R

0h

N/A (Hard-coded)

POR - DAFG - LR

N/A (Hard-coded)

POR - DAFG - LR

Reserved.

5:4

R

3h

Actual power state of this widget.

Rsvd1

Set

3:2

R

0h

Reserved.

1:0

RW

3h

Current power state setting for this widget.

7.22.5. DAC0 (NID = 15h): CnvtrID

Reg

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

706h

Set

240

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Eight channel HD Audio codec optimized for low power

7.22.5. DAC0 (NID = 15h): CnvtrID

Reg

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0600h

Field Name

Bits

R/W

Default

Reset

Rsvd

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7:4

Strm

Ch

RW

0h

POR - S&DAFG - LR - PS

Stream ID: 0h = Converter "off", 1h-Fh = valid ID's.

3:0 RW 0h POR - S&DAFG - LR - PS

Channel assignment ("Ch" and "Ch+1" assigned as a pair, for a stereo convert-

er).

7.22.6. DAC0 (NID = 15h): EAPDBTLLR

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

70Ch

Get

F0C00h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:3

R

00000000h

N/A (Hard-coded)

Reserved.

2

SwapEn

Rsvd1

RW

0h

POR - DAFG - ULR

Swap enable: 1 = L/R swap enabled, 0 = L/R swap disabled.

1:0

R

0h

N/A (Hard-coded)

Reserved.

241

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Eight channel HD Audio codec optimized for low power

7.23. DAC1 (NID = 16h): WCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0009h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:24

R

00h

N/A (Hard-coded)

Reserved.

23:20

Type

R

0h

N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay

19:16

R

Dh

N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1

15:12

Reserved.

11

R

0h

SwapCap

PwrCntrl

Dig

R

1h

Left/right swap support: 1 = yes, 0 = no.

10 1h

Power state support: 1 = yes, 0 = no.

0h

Digital stream support: 1 = yes (digital), 0 = no (analog).

0h N/A (Hard-coded)

R

9

R

ConnList

8

R

Connection list present: 1 = yes, 0 = no.

242

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

UnSolCap

7

R

0h

N/A (Hard-coded)

Unsolicited response support: 1 = yes, 0 = no.

0h

Processing state support: 1 = yes, 0 = no.

0h

Striping support: 1 = yes, 0 = no.

0h

Stream format override: 1 = yes, 0 = no.

0h

Amplifier capabilities override: 1 = yes, no.

1h

Output amp present: 1 = yes, 0 = no.

0h

Input amp present: 1 = yes, 0 = no.

1h

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

ProcWidget

Stripe

6

R

N/A (Hard-coded)

5

R

FormatOvrd

AmpParOvrd

OutAmpPrsnt

InAmpPrsnt

Stereo

4

R

3

R

2

R

1

R

0

R

7.23.1. DAC1 (NID = 16h): Cnvtr

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

2h

Get

A0000h

Field Name

Bits

R/W

Default

Reset

N/A (Hard-coded)

Rsvd2

31:16

R

0000h

Reserved.

243

V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

StrmType

15

R

0h

N/A (Hard-coded)

Stream type: 1 = Non-PCM, 0 = PCM.

14 RW 0h

Sample base rate: 1 = 44.1kHz, 0 = 48kHz.

13:11 RW 0h

Sample base rate multiple:

FrmtSmplRate

SmplRateMultp

POR - DAFG - ULR

000b= x1 (48kHz/44.1kHz or less)

001b= x2 (96kHz/88.2kHz/32kHz)

010b= x3 (144kHz)

011b= x4 (192kHz/176.4kHz)

100b-111b Reserved

SmplRateDiv

10:8

RW

0h

POR - DAFG - ULR

Sample base rate divider:

000b= Divide by 1 (48kHz/44.1kHz)

001b= Divide by 2 (24kHz/20.05kHz)

010b= Divide by 3 (16kHz/32kHz)

011b= Divide by 4 (11.025kHz)

100b= Divide by 5 (9.6kHz)

101b= Divide by 6 (8kHz)

110b= Divide by 7

111b= Divide by 8 (6kHz)

Rsvd1

7

R

0h

3h

N/A (Hard-coded)

Reserved.

6:4

BitsPerSmpl

RW

POR - DAFG - ULR

Bits per sample:

000b= 8 bits

001b= 16 bits

010b= 20 bits

011b= 24 bits

100b= 32 bits

101b-111b= Reserved

NmbrChan

3:0

RW

1h

POR - DAFG - ULR

Total number of channels in the stream assigned to this converter:

0000b-1111b= 1-16 channels.

244

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Eight channel HD Audio codec optimized for low power

7.23.2. DAC1 (NID = 16h): OutAmpLeft

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

3A0h

Get

BA000h

Field Name

Bits

R/W

Default

Reset

Rsvd

31:8

R

000000h

N/A (Hard-coded)

POR - DAFG - ULR

Reserved.

7

Mute

Gain

RW

1h

Amp mute: 1 = muted, 0 = not muted.

6:0 RW 7Fh

Amp gain step number (see OutAmpCap parameter pertaining to this widget).

7.23.3. DAC1 (NID = 16h): OutAmpRight

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

390h

Get

B8000h

Field Name

Bits

R/W

Default

Reset

Rsvd

31:8

R

000000h

N/A (Hard-coded)

POR - DAFG - ULR

Reserved.

7

Mute

Gain

RW

1h

Amp mute: 1 = muted, 0 = not muted.

6:0 RW 7Fh

Amp gain step number (see OutAmpCap parameter pertaining to this widget).

245

V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

7.23.4. DAC1 (NID = 16h): PwrState

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

705h

Get

F0500h

Field Name

Bits

R/W

Default

Reset

Rsvd4

31:11

Reserved.

10

R

000000h

N/A (Hard-coded)

SettingsReset

R

1h

POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

Rsvd3

Error

9

R

0h

N/A (Hard-coded)

Reserved.

8

R

0h

POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

Rsvd2

Act

7:6

R

0h

N/A (Hard-coded)

POR - DAFG - LR

N/A (Hard-coded)

POR - DAFG - LR

Reserved.

5:4

R

3h

Actual power state of this widget.

Rsvd1

Set

3:2

R

0h

Reserved.

1:0

RW

3h

Current power state setting for this widget.

7.23.5. DAC1 (NID = 16h): CnvtrID

Reg

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

706h

Set

246

V1.1 06/11

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Eight channel HD Audio codec optimized for low power

7.23.5. DAC1 (NID = 16h): CnvtrID

Reg

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0600h

Field Name

Bits

R/W

Default

Reset

Rsvd

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7:4

Strm

Ch

RW

0h

POR - S&DAFG - LR - PS

Stream ID: 0h = Converter "off", 1h-Fh = valid ID's.

3:0 RW 0h POR - S&DAFG - LR - PS

Channel assignment ("Ch" and "Ch+1" assigned as a pair, for a stereo convert-

er).

7.23.6. DAC1 (NID = 16h): EAPDBTLLR

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

70Ch

Get

F0C00h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:3

R

00000000h

N/A (Hard-coded)

Reserved.

2

SwapEn

Rsvd1

RW

0h

POR - DAFG - ULR

Swap enable: 1 = L/R swap enabled, 0 = L/R swap disabled.

1:0

R

0h

N/A (Hard-coded)

Reserved.

247

V1.1 06/11

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Eight channel HD Audio codec optimized for low power

7.24. DAC2 (NID = 17h): WCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0009h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:24

R

00h

N/A (Hard-coded)

Reserved.

23:20

Type

R

0h

N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay

19:16

R

Dh

N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1

15:12

Reserved.

11

R

0h

SwapCap

PwrCntrl

Dig

R

1h

Left/right swap support: 1 = yes, 0 = no.

10 1h

Power state support: 1 = yes, 0 = no.

0h

Digital stream support: 1 = yes (digital), 0 = no (analog).

0h N/A (Hard-coded)

R

9

R

ConnList

8

R

Connection list present: 1 = yes, 0 = no.

248

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

UnSolCap

7

R

0h

N/A (Hard-coded)

Unsolicited response support: 1 = yes, 0 = no.

0h

Processing state support: 1 = yes, 0 = no.

0h

Striping support: 1 = yes, 0 = no.

0h

Stream format override: 1 = yes, 0 = no.

0h

Amplifier capabilities override: 1 = yes, no.

1h

Output amp present: 1 = yes, 0 = no.

0h

Input amp present: 1 = yes, 0 = no.

1h

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

ProcWidget

Stripe

6

R

N/A (Hard-coded)

5

R

FormatOvrd

AmpParOvrd

OutAmpPrsnt

InAmpPrsnt

Stereo

4

R

3

R

2

R

1

R

0

R

7.24.1. DAC2 (NID = 17h): Cnvtr

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

2h

Get

A0000h

Field Name

Bits

R/W

Default

Reset

N/A (Hard-coded)

Rsvd2

31:16

R

0000h

Reserved.

249

V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

StrmType

15

R

0h

N/A (Hard-coded)

Stream type: 1 = Non-PCM, 0 = PCM.

14 RW 0h

Sample base rate: 1 = 44.1kHz, 0 = 48kHz.

13:11 RW 0h

Sample base rate multiple:

FrmtSmplRate

SmplRateMultp

POR - DAFG - ULR

000b= x1 (48kHz/44.1kHz or less)

001b= x2 (96kHz/88.2kHz/32kHz)

010b= x3 (144kHz)

011b= x4 (192kHz/176.4kHz)

100b-111b Reserved

SmplRateDiv

10:8

RW

0h

POR - DAFG - ULR

Sample base rate divider:

000b= Divide by 1 (48kHz/44.1kHz)

001b= Divide by 2 (24kHz/20.05kHz)

010b= Divide by 3 (16kHz/32kHz)

011b= Divide by 4 (11.025kHz)

100b= Divide by 5 (9.6kHz)

101b= Divide by 6 (8kHz)

110b= Divide by 7

111b= Divide by 8 (6kHz)

Rsvd1

7

R

0h

3h

N/A (Hard-coded)

Reserved.

6:4

BitsPerSmpl

RW

POR - DAFG - ULR

Bits per sample:

000b= 8 bits

001b= 16 bits

010b= 20 bits

011b= 24 bits

100b= 32 bits

101b-111b= Reserved

NmbrChan

3:0

RW

1h

POR - DAFG - ULR

Total number of channels in the stream assigned to this converter:

0000b-1111b= 1-16 channels.

250

V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

7.24.2. DAC2 (NID = 17h): OutAmpLeft

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

3A0h

Get

BA000h

Field Name

Bits

R/W

Default

Reset

Rsvd

31:8

R

000000h

N/A (Hard-coded)

POR - DAFG - ULR

Reserved.

7

Mute

Gain

RW

1h

Amp mute: 1 = muted, 0 = not muted.

6:0 RW 7Fh

Amp gain step number (see OutAmpCap parameter pertaining to this widget).

7.24.3. DAC2 (NID = 17h): OutAmpRight

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

390h

Get

B8000h

Field Name

Bits

R/W

Default

Reset

Rsvd

31:8

R

000000h

N/A (Hard-coded)

POR - DAFG - ULR

Reserved.

7

Mute

Gain

RW

1h

Amp mute: 1 = muted, 0 = not muted.

6:0 RW 7Fh

Amp gain step number (see OutAmpCap parameter pertaining to this widget).

251

V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

7.24.4. DAC2 (NID = 17h): PwrState

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

705h

Get

F0500h

Field Name

Bits

R/W

Default

Reset

Rsvd4

31:11

Reserved.

10

R

000000h

N/A (Hard-coded)

SettingsReset

R

1h

POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

Rsvd3

Error

9

R

0h

N/A (Hard-coded)

Reserved.

8

R

0h

POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

Rsvd2

Act

7:6

R

0h

N/A (Hard-coded)

POR - DAFG - LR

N/A (Hard-coded)

POR - DAFG - LR

Reserved.

5:4

R

3h

Actual power state of this widget.

Rsvd1

Set

3:2

R

0h

Reserved.

1:0

RW

3h

Current power state setting for this widget.

7.24.5. DAC2 (NID = 17h): CnvtrID

Reg

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

706h

Set

252

V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

7.24.5. DAC2 (NID = 17h): CnvtrID

Reg

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0600h

Field Name

Bits

R/W

Default

Reset

Rsvd

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7:4

Strm

Ch

RW

0h

POR - S&DAFG - LR - PS

Stream ID: 0h = Converter "off", 1h-Fh = valid ID's.

3:0 RW 0h POR - S&DAFG - LR - PS

Channel assignment ("Ch" and "Ch+1" assigned as a pair, for a stereo convert-

er).

7.24.6. DAC2 (NID = 17h): EAPDBTLLR

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

70Ch

Get

F0C00h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:3

R

00000000h

N/A (Hard-coded)

Reserved.

2

SwapEn

Rsvd1

RW

0h

POR - DAFG - ULR

Swap enable: 1 = L/R swap enabled, 0 = L/R swap disabled.

1:0

R

0h

N/A (Hard-coded)

Reserved.

253

V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

7.25. DAC3 (NID = 18h): WCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0009h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:24

R

00h

N/A (Hard-coded)

Reserved.

23:20

Type

R

0h

N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay

19:16

R

Dh

N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1

15:12

Reserved.

11

R

0h

SwapCap

PwrCntrl

Dig

R

1h

Left/right swap support: 1 = yes, 0 = no.

10 1h

Power state support: 1 = yes, 0 = no.

0h

Digital stream support: 1 = yes (digital), 0 = no (analog).

0h N/A (Hard-coded)

R

9

R

ConnList

8

R

Connection list present: 1 = yes, 0 = no.

254

V1.1 06/11

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

UnSolCap

7

R

0h

N/A (Hard-coded)

Unsolicited response support: 1 = yes, 0 = no.

0h

Processing state support: 1 = yes, 0 = no.

0h

Striping support: 1 = yes, 0 = no.

0h

Stream format override: 1 = yes, 0 = no.

0h

Amplifier capabilities override: 1 = yes, no.

1h

Output amp present: 1 = yes, 0 = no.

0h

Input amp present: 1 = yes, 0 = no.

1h

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

ProcWidget

Stripe

6

R

N/A (Hard-coded)

5

R

FormatOvrd

AmpParOvrd

OutAmpPrsnt

InAmpPrsnt

Stereo

4

R

3

R

2

R

1

R

0

R

7.25.1. DAC3 (NID = 18h): Cnvtr

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

2h

Get

A0000h

Field Name

Bits

R/W

Default

Reset

N/A (Hard-coded)

Rsvd2

31:16

R

0000h

Reserved.

255

V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

StrmType

15

R

0h

N/A (Hard-coded)

Stream type: 1 = Non-PCM, 0 = PCM.

14 RW 0h

Sample base rate: 1 = 44.1kHz, 0 = 48kHz.

13:11 RW 0h

Sample base rate multiple:

FrmtSmplRate

SmplRateMultp

POR - DAFG - ULR

000b= x1 (48kHz/44.1kHz or less)

001b= x2 (96kHz/88.2kHz/32kHz)

010b= x3 (144kHz)

011b= x4 (192kHz/176.4kHz)

100b-111b Reserved

SmplRateDiv

10:8

RW

0h

POR - DAFG - ULR

Sample base rate divider:

000b= Divide by 1 (48kHz/44.1kHz)

001b= Divide by 2 (24kHz/20.05kHz)

010b= Divide by 3 (16kHz/32kHz)

011b= Divide by 4 (11.025kHz)

100b= Divide by 5 (9.6kHz)

101b= Divide by 6 (8kHz)

110b= Divide by 7

111b= Divide by 8 (6kHz)

Rsvd1

7

R

0h

3h

N/A (Hard-coded)

Reserved.

6:4

BitsPerSmpl

RW

POR - DAFG - ULR

Bits per sample:

000b= 8 bits

001b= 16 bits

010b= 20 bits

011b= 24 bits

100b= 32 bits

101b-111b= Reserved

NmbrChan

3:0

RW

1h

POR - DAFG - ULR

Total number of channels in the stream assigned to this converter:

0000b-1111b= 1-16 channels.

256

V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

7.25.2. DAC3 (NID = 18h): OutAmpLeft

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

3A0h

Get

BA000h

Field Name

Bits

R/W

Default

Reset

Rsvd

31:8

R

000000h

N/A (Hard-coded)

POR - DAFG - ULR

Reserved.

7

Mute

Gain

RW

1h

Amp mute: 1 = muted, 0 = not muted.

6:0 RW 7Fh

Amp gain step number (see OutAmpCap parameter pertaining to this widget).

7.25.3. DAC3 (NID = 18h): OutAmpRight

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

390h

Get

B8000h

Field Name

Bits

R/W

Default

Reset

Rsvd

31:8

R

000000h

N/A (Hard-coded)

POR - DAFG - ULR

Reserved.

7

Mute

Gain

RW

1h

Amp mute: 1 = muted, 0 = not muted.

6:0 RW 7Fh

Amp gain step number (see OutAmpCap parameter pertaining to this widget).

257

V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

7.25.4. DAC3 (NID = 18h): PwrState

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

705h

Get

F0500h

Field Name

Bits

R/W

Default

Reset

Rsvd4

31:11

Reserved.

10

R

000000h

N/A (Hard-coded)

SettingsReset

R

1h

POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

Rsvd3

Error

9

R

0h

N/A (Hard-coded)

Reserved.

8

R

0h

POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

Rsvd2

Act

7:6

R

0h

N/A (Hard-coded)

POR - DAFG - LR

N/A (Hard-coded)

POR - DAFG - LR

Reserved.

5:4

R

3h

Actual power state of this widget.

Rsvd1

Set

3:2

R

0h

Reserved.

1:0

RW

3h

Current power state setting for this widget.

7.25.5. DAC3 (NID = 18h): CnvtrID

Reg

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

706h

Set

258

V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

7.25.5. DAC3 (NID = 18h): CnvtrID

Reg

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0600h

Field Name

Bits

R/W

Default

Reset

Rsvd

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7:4

Strm

Ch

RW

0h

POR - S&DAFG - LR - PS

Stream ID: 0h = Converter "off", 1h-Fh = valid ID's.

3:0 RW 0h POR - S&DAFG - LR - PS

Channel assignment ("Ch" and "Ch+1" assigned as a pair, for a stereo convert-

er).

7.25.6. DAC3 (NID = 18h): EAPDBTLLR

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

70Ch

Get

F0C00h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:3

R

00000000h

N/A (Hard-coded)

Reserved.

2

SwapEn

Rsvd1

RW

0h

POR - DAFG - ULR

Swap enable: 1 = L/R swap enabled, 0 = L/R swap disabled.

1:0

R

0h

N/A (Hard-coded)

Reserved.

259

V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

7.26. Vendor Reserved (NID = 19h)

260

V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

7.27. ADC0Mux (NID = 20h): WCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0009h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:24

R

00h

N/A (Hard-coded)

Reserved.

23:20

Type

R

3h

N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay

19:16

R

0h

N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1

15:12

Reserved.

11

R

0h

SwapCap

PwrCntrl

DigitalStrm

ConnList

R

1h

Left/right swap support: 1 = yes, 0 = no.

10 1h

Power state support: 1 = yes, 0 = no.

0h

Digital stream support: 1 = yes (digital), 0 = no (analog).

1h N/A (Hard-coded)

R

9

R

8

R

Connection list present: 1 = yes, 0 = no.

261

V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

UnsolCap

7

R

0h

N/A (Hard-coded)

Unsolicited response support: 1 = yes, 0 = no.

0h

Processing state support: 1 = yes, 0 = no.

0h

Striping support: 1 = yes, 0 = no.

0h

Stream format override: 1 = yes, 0 = no.

1h

Amplifier capabilities override: 1 = yes, no.

1h

Output amp present: 1 = yes, 0 = no.

0h

Input amp present: 1 = yes, 0 = no.

1h

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

ProcWidget

Stripe

6

R

N/A (Hard-coded)

5

R

FormatOvrd

AmpParamOvrd

OutAmpPrsnt

InAmpPrsnt

Stereo

4

R

3

R

2

R

1

R

0

R

7.27.1. ADC0Mux (NID = 20h): ConLst

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Eh

Field Name

Bits

R/W

Default

Reset

N/A (Hard-coded)

Rsvd

31:8

R

000000h

Reserved.

262

V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

LForm

7

R

0h

N/A (Hard-coded)

Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)

NID entries.

ConL

6:0

R

04h in 40QFN N/A (Hard-coded)

06h in 48QFN

Number of NID entries in connection list.

7.27.2. ADC0Mux (NID = 17h): ConLstEntry4

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0204h

Field Name

Bits

R/W

Default

Reset

ConL7

31:24

R

00h

N/A (Hard-coded)

Unused list entry.

23:16

Unused list entry.

15:8

ConL6

ConL5

R

00h

N/A (Hard-coded)

R

00h in 40QFN N/A (Hard-coded)

14h in 48QFN

DMic1 Pin widget (0x14) for QFN48, reserved for QFN40.

ConL4

7:0

R

00h in 40QFN N/A (Hard-coded)

13h in 48QFN

DMic0 Pin widget (0x13) for QFN48, reserved for QFN40.

7.27.3. ADC0Mux (NID = 20h): ConLstEntry0

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0200h

263

V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

ConL3

31:24

R

12h

N/A (Hard-coded)

CD Pin widget (0x12)

23

ConL2Range

R

1h

N/A (Hard-coded)

ConL1 .. ConL2 define a selectalbe range input

ConL2

ConL1

ConL0

22:16

Port H Pin widget (0x10)

15:8

Port A Pin widget (0x0A)

7:0

R

11h

0Ah

1Dh

N/A (Hard-coded)

R

Mixer Summing widget (0x1D

7.27.4. ADC0Mux (NID = 20h): OutAmpCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0012h

Field Name

Bits

R/W

Default

Reset

Mute

31

R

1h

N/A (Hard-coded)

Mute support: 1 = yes, 0 = no.

Rsvd3

30:23

R

00h

05h

N/A (Hard-coded)

Reserved.

22:16

StepSize

Rsvd2

Size of each step in the gain range: 0 to 127 = .25dB to 32dB, in .25dB steps.

15

R

0h

N/A (Hard-coded)

Reserved.

264

V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

NumSteps

14:8

R

0Fh

N/A (Hard-coded)

Number of gains steps (number of possible settings - 1).

Rsvd1

Offset

7

R

0h

N/A (Hard-coded)

Reserved.

6:0

R

00h

N/A (Hard-coded)

Indicates which step is 0dB

7.27.5. ADC0Mux (NID = 20h): OutAmpLeft

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

3A0h

Get

BA000h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

Mute

Rsvd1

Gain

RW

1h

POR - DAFG - ULR

N/A (Hard-coded)

POR - DAFG - ULR

Amp mute: 1 = muted, 0 = not muted.

6:4

R

0h

Reserved.

3:0

RW

0h

Amp gain step number (see OutAmpCap parameter pertaining to this widget).

7.27.6. ADC0Mux (NID = 20h): OutAmpRight

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

390h

Get

B8000h

265

V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

Mute

Rsvd1

Gain

RW

1h

POR - DAFG - ULR

N/A (Hard-coded)

POR - DAFG - ULR

Amp mute: 1 = muted, 0 = not muted.

6:4

R

0h

Reserved.

3:0

RW

0h

Amp gain step number (see OutAmpCap parameter pertaining to this widget).

7.27.7. ADC0Mux (NID = 20h): ConSelectCtrl

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

701h

Get

F0100h

Field Name

Bits

R/W

Default

Reset

Rsvd

31:3

R

00000000h

N/A (Hard-coded)

Reserved.

2:0

Index

RW

0h

POR - DAFG - ULR

Connection select control index.

7.27.8. ADC0Mux (NID = 20h): PwrState

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

705h

Get

F0500h

266

V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

Rsvd4

31:11

Reserved.

10

R

000000h

N/A (Hard-coded)

SettingsReset

R

1h

POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

Rsvd3

Error

9

R

0h

N/A (Hard-coded)

Reserved.

8

R

0h

POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

Rsvd2

Act

7:6

R

0h

N/A (Hard-coded)

POR - DAFG - LR

N/A (Hard-coded)

POR - DAFG - LR

Reserved.

5:4

R

3h

Actual power state of this widget.

Rsvd1

Set

3:2

R

0h

Reserved.

1:0

RW

0h

Current power state setting for this widget.

7.27.9. ADC0Mux (NID = 20h): EAPDBTLLR

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

70Ch

Get

F0C00h

267

V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:3

R

00000000h

N/A (Hard-coded)

Reserved.

2

SwapEn

Rsvd1

RW

0h

POR - DAFG - ULR

Swap enable: 1 = L/R swap enabled, 0 = L/R swap disabled.

1:0

R

0h

N/A (Hard-coded)

Reserved.

268

V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

7.28. ADC1Mux (NID = 21h): WCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0009h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:24

R

00h

N/A (Hard-coded)

Reserved.

23:20

Type

R

3h

N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay

19:16

R

0h

N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1

15:12

Reserved.

11

R

0h

SwapCap

PwrCntrl

DigitalStrm

ConnList

R

1h

Left/right swap support: 1 = yes, 0 = no.

10 1h

Power state support: 1 = yes, 0 = no.

0h

Digital stream support: 1 = yes (digital), 0 = no (analog).

1h N/A (Hard-coded)

R

9

R

8

R

Connection list present: 1 = yes, 0 = no.

269

V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

UnsolCap

7

R

0h

N/A (Hard-coded)

Unsolicited response support: 1 = yes, 0 = no.

0h

Processing state support: 1 = yes, 0 = no.

0h

Striping support: 1 = yes, 0 = no.

0h

Stream format override: 1 = yes, 0 = no.

1h

Amplifier capabilities override: 1 = yes, no.

1h

Output amp present: 1 = yes, 0 = no.

0h

Input amp present: 1 = yes, 0 = no.

1h

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

ProcWidget

Stripe

6

R

N/A (Hard-coded)

5

R

FormatOvrd

AmpParamOvrd

OutAmpPrsnt

InAmpPrsnt

Stereo

4

R

3

R

2

R

1

R

0

R

7.28.1. ADC1Mux (NID = 21h): ConLst

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Eh

Field Name

Bits

R/W

Default

Reset

N/A (Hard-coded)

Rsvd

31:8

R

000000h

Reserved.

270

V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

LForm

7

R

0h

N/A (Hard-coded)

Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)

NID entries.

ConL

6:0

R

05h

N/A (Hard-coded)

Number of NID entries in connection list.

7.28.2. ADC1Mux (NID = 21h): ConLstEntry4

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0204h

Field Name

Bits

R/W

Default

Reset

ConL7

31:24

R

00h

N/A (Hard-coded)

Unused list entry.

23:16

Unused list entry

15:8

ConL6

ConL5

R

00h

N/A (Hard-coded)

R

00h in 40QFN N/A (Hard-coded)

14h in 48QFN

DMic1 Pin widget (0x14) for QFN48, reserved for QFN40

ConL4

7:0

R

00h in 40QFN N/A (Hard-coded)

13h in 48QFN

DMic0 Pin widget (0x13) for QFN48, reserved for QFN40

7.28.3. ADC1Mux (NID = 21h): ConLstEntry0

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0200h

271

V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

ConL3

31:24

R

1Bh

N/A (Hard-coded)

Mixer Summing widget (0x1B)

23 1h

ConL1 .. ConL2 define a selectalbe range input

ConL2Range

R

N/A (Hard-coded)

ConL2

ConL1

ConL0

22:16

Port H Pin widget (0x10)

15:8

Port A Pin widget (0x0A)

7:0

R

11h

0Ah

1Dh

N/A (Hard-coded)

R

Mixer Summing widget (0x0D)

7.28.4. ADC1Mux (NID = 21h): OutAmpCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0012h

Field Name

Bits

R/W

Default

Reset

Mute

31

R

1h

N/A (Hard-coded)

Mute support: 1 = yes, 0 = no.

Rsvd3

30:23

R

00h

05h

N/A (Hard-coded)

Reserved.

22:16

StepSize

Rsvd2

Size of each step in the gain range: 0 to 127 = .25dB to 32dB, in .25dB steps.

15

R

0h

N/A (Hard-coded)

Reserved.

272

V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

NumSteps

14:8

R

0Fh

N/A (Hard-coded)

Number of gains steps (number of possible settings - 1).

Rsvd1

Offset

7

R

0h

N/A (Hard-coded)

Reserved.

6:0

R

00h

N/A (Hard-coded)

Indicates which step is 0dB

7.28.5. ADC1Mux (NID = 21h): OutAmpLeft

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

3A0h

Get

BA000h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

Mute

Rsvd1

Gain

RW

1h

POR - DAFG - ULR

N/A (Hard-coded)

POR - DAFG - ULR

Amp mute: 1 = muted, 0 = not muted.

6:4

R

0h

Reserved.

3:0

RW

0h

Amp gain step number (see OutAmpCap parameter pertaining to this widget).

7.28.6. ADC1Mux (NID = 21h): OutAmpRight

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

390h

Get

B8000h

273

V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

Mute

Rsvd1

Gain

RW

1h

POR - DAFG - ULR

N/A (Hard-coded)

POR - DAFG - ULR

Amp mute: 1 = muted, 0 = not muted.

6:4

R

0h

Reserved.

3:0

RW

0h

Amp gain step number (see OutAmpCap parameter pertaining to this widget).

7.28.7. ADC1Mux (NID = 21h): ConSelectCtrl

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

701h

Get

F0100h

Field Name

Bits

R/W

Default

Reset

Rsvd

31:3

R

00000000h

N/A (Hard-coded)

Reserved.

2:0

Index

RW

0h

POR - DAFG - ULR

Connection select control index.

7.28.8. ADC1Mux (NID = 21h): PwrState

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

705h

Get

F0500h

274

V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

Rsvd4

31:11

Reserved.

10

R

000000h

N/A (Hard-coded)

SettingsReset

R

1h

POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

Rsvd3

Error

9

R

0h

N/A (Hard-coded)

Reserved.

8

R

0h

POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

Rsvd2

Act

7:6

R

0h

N/A (Hard-coded)

POR - DAFG - LR

N/A (Hard-coded)

POR - DAFG - LR

Reserved.

5:4

R

3h

Actual power state of this widget.

Rsvd1

Set

3:2

R

0h

Reserved.

1:0

RW

0h

Current power state setting for this widget.

7.28.9. ADC1Mux (NID = 21h): EAPDBTLLR

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

70Ch

Get

F0C00h

275

V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:3

R

00000000h

N/A (Hard-coded)

Reserved.

2

SwapEn

Rsvd1

RW

0h

POR - DAFG - ULR

Swap enable: 1 = L/R swap enabled, 0 = L/R swap disabled.

1:0

R

0h

N/A (Hard-coded)

Reserved.

276

V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

7.29. Dig0Pin (NID = 22h): WCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0009h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:24

R

00h

N/A (Hard-coded)

Reserved.

23:20

Type

R

4h

N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay

19:16

R

0h

N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1

15:12

Reserved.

11

R

0h

SwapCap

PwrCntrl

Dig

R

0h

Left/right swap support: 1 = yes, 0 = no.

10 1h

Power state support: 1 = yes, 0 = no.

1h

Digital stream support: 1 = yes (digital), 0 = no (analog).

1h N/A (Hard-coded)

R

9

R

ConnList

8

R

Connection list present: 1 = yes, 0 = no.

277

V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

UnSolCap

7

R

1h

N/A (Hard-coded)

Unsolicited response support: 1 = yes, 0 = no.

0h

Processing state support: 1 = yes, 0 = no.

0h

Striping support: 1 = yes, 0 = no.

0h

Stream format override: 1 = yes, 0 = no.

0h

Amplifier capabilities override: 1 = yes, no.

0h

Output amp present: 1 = yes, 0 = no.

0h

Input amp present: 1 = yes, 0 = no.

1h

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

ProcWidget

Stripe

6

R

N/A (Hard-coded)

5

R

FormatOvrd

AmpParOvrd

OutAmpPrsnt

InAmpPrsnt

Stereo

4

R

3

R

2

R

1

R

0

R

7.29.1. Dig0Pin (NID = 22h): PinCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Ch

Field Name

Bits

R/W

Default

Reset

N/A (Hard-coded)

Rsvd2

31:17

R

0000h

Reserved.

278

V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

EapdCap

16

R

0h

N/A (Hard-coded)

EAPD support: 1 = yes, 0 = no.

VrefCntrl

15:8

R

00h

N/A (Hard-coded)

Vref support:

bit 7 = Reserved

bit 6 = Reserved

bit 5 = 100% support (1 = yes, 0 = no)

bit 4 = 80% support (1 = yes, 0 = no)

bit 3 = Reserved

bit 2 = GND support (1 = yes, 0 = no)

bit 1 = 50% support (1 = yes, 0 = no)

bit 0 = Hi-Z support (1 = yes, 0 = no)

Rsvd1

7

R

0h

N/A (Hard-coded)

Reserved.

6

BalancedIO

InCap

R

0h

Balanced I/O support: 1 = yes, 0 = no.

0h

Input support: 1 = yes, 0 = no.

1h

Output support: 1 = yes, 0 = no.

0h

Headphone amp present: 1 = yes, 0 = no.

1h

Presence detection support: 1 = yes, 0 = no.

0h

Trigger required for impedance sense: 1 = yes, 0 = no.

0h N/A (Hard-coded)

5

R

OutCap

4

R

HdphDrvCap

PresDtctCap

TrigRqd

3

R

2

R

1

R

ImpSenseCap

0

R

Impedance sense support: 1 = yes, 0 = no.

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7.29.2. Dig0Pin (NID = 22h): ConLst

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Eh

Field Name

Bits

R/W

Default

Reset

Rsvd

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

LForm

ConL

R

0h

N/A (Hard-coded)

Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)

NID entries.

6:0

R

01h

N/A (Hard-coded)

Number of NID entries in connection list.

7.29.3. Dig0Pin (NID = 22h): ConLstEntry0

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0200h

Field Name

Bits

R/W

Default

Reset

ConL3

31:24

R

00h

N/A (Hard-coded)

Unused list entry.

23:16

Unused list entry.

15:8

Unused list entry.

ConL2

ConL1

R

00h

N/A (Hard-coded)

R

280

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

ConL0

7:0

R

25h

N/A (Hard-coded)

SPDIFOut0 Converter widget (0x25)

7.29.4. Dig0Pin (NID = 22h): PwrState

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

705h

Get

F0500h

Field Name

Bits

R/W

Default

Reset

Rsvd4

31:11

Reserved.

10

R

000000h

N/A (Hard-coded)

SettingsReset

R

1h

POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

Rsvd3

Error

9

R

0h

N/A (Hard-coded)

Reserved.

8

R

0h

POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

Rsvd2

Act

7:6

R

0h

N/A (Hard-coded)

POR - DAFG - LR

N/A (Hard-coded)

POR - DAFG - LR

Reserved.

5:4

R

3h

Actual power state of this widget.

Rsvd1

Set

3:2

R

0h

Reserved.

1:0

RW

0h

Current power state setting for this widget.

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7.29.5. Dig0Pin (NID = 22h): PinWCntrl

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

707h

Get

F0700h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:7

R

0000000h

N/A (Hard-coded)

POR - DAFG - ULR

N/A (Hard-coded)

Reserved.

6

OutEn

Rsvd1

RW

0h

Output enable: 1 = enabled, 0 = disabled.

5:0

R

00h

Reserved.

7.29.6. Dig0Pin (NID = 22h): UnsolResp

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

708h

Get

F0800h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

En

RW

0h

POR - DAFG - ULR

Unsolicited response enable (also enables Wake events for this Widget): 1 =

enabled, 0 = disabled.

Rsvd1

6

R

0h

N/A (Hard-coded)

Reserved.

282

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Field Name

Bits

R/W

Default

Reset

Tag

5:0

RW

00h

POR - DAFG - ULR

Software programmable field returned in top six bits (31:26) of every Unsolicit-

ed Response generated by this node.

7.29.7. Dig0Pin (NID = 22h): ChSense

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

709h

Get

F0900h

Field Name

Bits

R/W

Default

0h

Reset

PresDtct

31

R

POR

Presence detection indicator: 1 = presence detected; 0 = presence not detect-

ed.

Rsvd

30:0

R

00000000h

N/A (Hard-coded)

Reserved.

7.29.8. Dig0Pin (NID = 22h): ConfigDefault

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

71Dh

Byte 1 (Bits 7:0)

71Fh

71Eh

71Ch

Get

F1F00h / F1E00h / F1D00h / F1C00h

Field Name

Bits

R/W

Default

Reset

PortConnectivity

31:30

RW

0h

POR

Port connectivity:

0h = Port complex is connected to a jack

1h = No physical connection for port

2h = Fixed function device is attached

3h = Both jack and internal device attached (info in all other fields refers to in-

tegrated device, any presence detection refers to jack)

283

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Field Name

Bits

R/W

Default

Reset

Location

29:24

RW

1h

POR

Location

Bits [5..4]:

0h = External on primary chassis

1h = Internal

2h = Separate chassis

3h = Other

Bits [3..0]:

0h = N/A

1h = Rear

2h = Front

3h = Left

4h = Right

5h = Top

6h = Bottom

7h-9h = Special

Ah-Fh = Reserved

Device

23:20

RW

4h

POR

Default device:

0h = Line out

1h = Speaker

2h = HP out

3h = CD

4h = SPDIF Out

5h = Digital other out

6h = Modem line side

7h = Modem handset side

8h = Line in

9h = Aux

Ah = Mic in

Bh = Telephony

Ch = SPDIF In

Dh = Digital other in

Eh = Reserved

Fh = Other

284

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Field Name

Bits

R/W

Default

Reset

ConnectionType

19:16

RW

5h

POR

Connection type:

0h = Unknown

1h = 1/8" stereo/mono

2h = 1/4" stereo/mono

3h = ATAPI internal

4h = RCA

5h = Optical

6h = Other digital

7h = Other analog

8h = Multichannel analog (DIN)

9h = XLR/Professional

Ah = RJ-11 (modem)

Bh = Combination

Ch-Eh = Reserved

Fh = Other

Color

15:12

RW

1h

POR

Color:

0h = Unknown

1h = Black

2h = Grey

3h = Blue

4h = Green

5h = Red

6h = Orange

7h = Yellow

8h = Purple

9h = Pink

Ah-Dh = Reserved

Eh = White

Fh = Other

Misc

11:8

RW

1h

POR

Miscellaneous:

Bits [3..1] = Reserved

Bit 0 = Jack detect override

Association

Sequence

7:4

RW

5h

0h

POR

Default assocation.

3:0

RW

Sequence.

285

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Eight channel HD Audio codec optimized for low power

7.30. Dig1Pin (NID = 23h): WCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0009h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:24

R

00h

N/A (Hard-coded)

Reserved.

23:20

Type

R

4h

N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay

19:16

R

0h

N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1

15:12

Reserved.

11

R

0h

SwapCap

PwrCntrl

Dig

R

0h

Left/right swap support: 1 = yes, 0 = no.

10 1h

Power state support: 1 = yes, 0 = no.

1h

Digital stream support: 1 = yes (digital), 0 = no (analog).

1h N/A (Hard-coded)

R

9

R

ConnList

8

R

Connection list present: 1 = yes, 0 = no.

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Field Name

Bits

R/W

Default

Reset

UnSolCap

7

R

1h

N/A (Hard-coded)

Unsolicited response support: 1 = yes, 0 = no.

0h

Processing state support: 1 = yes, 0 = no.

0h

Striping support: 1 = yes, 0 = no.

0h

Stream format override: 1 = yes, 0 = no.

0h

Amplifier capabilities override: 1 = yes, no.

0h

Output amp present: 1 = yes, 0 = no.

0h

Input amp present: 1 = yes, 0 = no.

1h

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

ProcWidget

Stripe

6

R

N/A (Hard-coded)

5

R

FormatOvrd

AmpParOvrd

OutAmpPrsnt

InAmpPrsnt

Stereo

4

R

3

R

2

R

1

R

0

R

7.30.1. Dig1Pin (NID = 23h): PinCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Ch

Field Name

Bits

R/W

Default

Reset

N/A (Hard-coded)

Rsvd2

31:17

R

0000h

Reserved.

287

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Field Name

Bits

R/W

Default

Reset

EapdCap

16

R

0h

N/A (Hard-coded)

EAPD support: 1 = yes, 0 = no.

VrefCntrl

15:8

R

00h

N/A (Hard-coded)

Vref support:

bit 7 = Reserved

bit 6 = Reserved

bit 5 = 100% support (1 = yes, 0 = no)

bit 4 = 80% support (1 = yes, 0 = no)

bit 3 = Reserved

bit 2 = GND support (1 = yes, 0 = no)

bit 1 = 50% support (1 = yes, 0 = no)

bit 0 = Hi-Z support (1 = yes, 0 = no)

Rsvd1

7

R

0h

N/A (Hard-coded)

Reserved.

6

BalancedIO

InCap

R

0h

Balanced I/O support: 1 = yes, 0 = no.

1h

Input support: 1 = yes, 0 = no.

1h

Output support: 1 = yes, 0 = no.

0h

Headphone amp present: 1 = yes, 0 = no.

1h

Presence detection support: 1 = yes, 0 = no.

0h

Trigger required for impedance sense: 1 = yes, 0 = no.

0h N/A (Hard-coded)

5

R

OutCap

4

R

HdphDrvCap

PresDtctCap

TrigRqd

3

R

2

R

1

R

ImpSenseCap

0

R

Impedance sense support: 1 = yes, 0 = no.

288

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Eight channel HD Audio codec optimized for low power

7.30.2. Dig1Pin (NID = 23h): ConLst

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Eh

Field Name

Bits

R/W

Default

Reset

Rsvd

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

LForm

ConL

R

0h

N/A (Hard-coded)

Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)

NID entries.

6:0

R

01h

N/A (Hard-coded)

Number of NID entries in connection list.

7.30.3. Dig1Pin (NID = 20h): ConLstEntry0

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0200h

Field Name

Bits

R/W

Default

Reset

ConL3

31:24

R

00h

N/A (Hard-coded)

Unused list entry.

23:16

Unused list entry.

15:8

Unused list entry.

ConL2

ConL1

R

00h

N/A (Hard-coded)

R

289

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

ConL0

7:0

R

26h

N/A (Hard-coded)

SPDIFOut1 Converter widget (0x26)

7.30.4. Dig1Pin (NID = 23h): PwrState

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

705h

Get

F0500h

Field Name

Bits

R/W

Default

Reset

Rsvd4

31:11

Reserved.

10

R

000000h

N/A (Hard-coded)

SettingsReset

R

1h

POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

Rsvd3

Error

9

R

0h

N/A (Hard-coded)

Reserved.

8

R

0h

POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

Rsvd2

Act

7:6

R

0h

N/A (Hard-coded)

POR - DAFG - LR

N/A (Hard-coded)

POR - DAFG - LR

Reserved.

5:4

R

3h

Actual power state of this widget.

Rsvd1

Set

3:2

R

0h

Reserved.

1:0

RW

0h

Current power state setting for this widget.

290

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Eight channel HD Audio codec optimized for low power

7.30.5. Dig1Pin (NID = 23h): PinWCntrl

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

707h

Get

F0700h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:7

R

0000000h

N/A (Hard-coded)

POR - DAFG - ULR

N/A (Hard-coded)

Reserved.

6

OutEn

InEn

RW

0h

Output enable: 1 = enabled, 0 = disabled.

RW 0h

Input enable: 1 = enabled, 0 = disabled.

5

Rsvd1

4:0

R

00h

Reserved.

7.30.6. Dig1Pin (NID = 20h): ConfigDefault

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

71Dh

Byte 1 (Bits 7:0)

71Fh

71Eh

71Ch

Get

F1F00h / F1E00h / F1D00h / F1C00h

Field Name

Bits

R/W

Default

Reset

PortConnectivity

31:30

RW

2h

POR

Port connectivity:

0h = Port complex is connected to a jack

1h = No physical connection for port

2h = Fixed function device is attached

3h = Both jack and internal device attached (info in all other fields refers to in-

tegrated device, any presence detection refers to jack)

291

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

Location

29:24

RW

18h

POR

Location

Bits [5..4]:

0h = External on primary chassis

1h = Internal

2h = Separate chassis

3h = Other

Bits [3..0]:

0h = N/A

1h = Rear

2h = Front

3h = Left

4h = Right

5h = Top

6h = Bottom

7h-9h = Special

Ah-Fh = Reserved

Device

23:20

RW

5h

POR

Default device:

0h = Line out

1h = Speaker

2h = HP out

3h = CD

4h = SPDIF Out

5h = Digital other out

6h = Modem line side

7h = Modem handset side

8h = Line in

9h = Aux

Ah = Mic in

Bh = Telephony

Ch = SPDIF In

Dh = Digital other in

Eh = Reserved

Fh = Other

292

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

ConnectionType

19:16

RW

6h

POR

Connection type:

0h = Unknown

1h = 1/8" stereo/mono

2h = 1/4" stereo/mono

3h = ATAPI internal

4h = RCA

5h = Optical

6h = Other digital

7h = Other analog

8h = Multichannel analog (DIN)

9h = XLR/Professional

Ah = RJ-11 (modem)

Bh = Combination

Ch-Eh = Reserved

Fh = Other

Color

15:12

RW

0h

POR

Color:

0h = Unknown

1h = Black

2h = Grey

3h = Blue

4h = Green

5h = Red

6h = Orange

7h = Yellow

8h = Purple

9h = Pink

Ah-Dh = Reserved

Eh = White

Fh = Other

Misc

11:8

RW

1h

POR

Miscellaneous:

Bits [3..1] = Reserved

Bit 0 = Jack detect override

Association

Sequence

7:4

RW

6h

0h

POR

Default assocation.

3:0

RW

Sequence.

293

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Eight channel HD Audio codec optimized for low power

7.31. Dig2Pin (NID = 24h): WCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0009h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:24

R

00h

N/A (Hard-coded)

Reserved.

23:20

Type

R

4h

N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay

19:16

R

0h

N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1

15:12

Reserved.

11

R

0h

SwapCap

PwrCntrl

Dig

R

0h

Left/right swap support: 1 = yes, 0 = no.

10 1h

Power state support: 1 = yes, 0 = no.

1h

Digital stream support: 1 = yes (digital), 0 = no (analog).

1h N/A (Hard-coded)

R

9

R

ConnList

8

R

Connection list present: 1 = yes, 0 = no.

294

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Field Name

Bits

R/W

Default

Reset

UnSolCap

7

R

1h

N/A (Hard-coded)

Unsolicited response support: 1 = yes, 0 = no.

0h

Processing state support: 1 = yes, 0 = no.

0h

Striping support: 1 = yes, 0 = no.

0h

Stream format override: 1 = yes, 0 = no.

0h

Amplifier capabilities override: 1 = yes, no.

0h

Output amp present: 1 = yes, 0 = no.

0h

Input amp present: 1 = yes, 0 = no.

1h

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

ProcWidget

Stripe

6

R

N/A (Hard-coded)

5

R

FormatOvrd

AmpParOvrd

OutAmpPrsnt

InAmpPrsnt

Stereo

4

R

3

R

2

R

1

R

0

R

7.31.1. Dig2Pin (NID = 24h): PinCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Ch

Field Name

Bits

R/W

Default

Reset

N/A (Hard-coded)

Rsvd2

31:17

R

0000h

Reserved.

295

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

EapdCap

16

R

0h

N/A (Hard-coded)

EAPD support: 1 = yes, 0 = no.

VrefCntrl

15:8

R

00h

N/A (Hard-coded)

Vref support:

bit 7 = Reserved

bit 6 = Reserved

bit 5 = 100% support (1 = yes, 0 = no)

bit 4 = 80% support (1 = yes, 0 = no)

bit 3 = Reserved

bit 2 = GND support (1 = yes, 0 = no)

bit 1 = 50% support (1 = yes, 0 = no)

bit 0 = Hi-Z support (1 = yes, 0 = no)

Rsvd1

7

R

0h

N/A (Hard-coded)

Reserved.

6

BalancedIO

InCap

R

0h

Balanced I/O support: 1 = yes, 0 = no.

1h

Input support: 1 = yes, 0 = no.

1h

Output support: 1 = yes, 0 = no.

0h

Headphone amp present: 1 = yes, 0 = no.

1h

Presence detection support: 1 = yes, 0 = no.

0h

Trigger required for impedance sense: 1 = yes, 0 = no.

0h N/A (Hard-coded)

5

R

OutCap

4

R

HdphDrvCap

PresDtctCap

TrigRqd

3

R

2

R

1

R

ImpSenseCap

0

R

Impedance sense support: 1 = yes, 0 = no.

296

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Eight channel HD Audio codec optimized for low power

7.31.2. Dig2Pin (NID = 24h): ConLst

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Eh

Field Name

Bits

R/W

Default

Reset

Rsvd

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

LForm

ConL

R

0h

N/A (Hard-coded)

Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)

NID entries.

6:0

R

01h

N/A (Hard-coded)

Number of NID entries in connection list.

7.31.3. Dig1Pin (NID = 20h): ConLstEntry0

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0200h

Field Name

Bits

R/W

Default

Reset

ConL3

31:24

R

00h

N/A (Hard-coded)

Unused list entry.

23:16

Unused list entry.

15:8

Unused list entry.

ConL2

ConL1

R

00h

N/A (Hard-coded)

R

297

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

ConL0

7:0

R

26h

N/A (Hard-coded)

SPDIFOut1 Converter widget (0x26)

7.31.4. Dig2Pin (NID = 24h): PwrState

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

705h

Get

F0500h

Field Name

Bits

R/W

Default

Reset

Rsvd4

31:11

Reserved.

10

R

000000h

N/A (Hard-coded)

SettingsReset

R

1h

POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

Rsvd3

Error

9

R

0h

N/A (Hard-coded)

Reserved.

8

R

0h

POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

Rsvd2

Act

7:6

R

0h

N/A (Hard-coded)

POR - DAFG - LR

N/A (Hard-coded)

POR - DAFG - LR

Reserved.

5:4

R

3h

Actual power state of this widget.

Rsvd1

Set

3:2

R

0h

Reserved.

1:0

RW

0h

Current power state setting for this widget.

298

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Eight channel HD Audio codec optimized for low power

7.31.5. Dig2Pin (NID = 24h): PinWCntrl

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

707h

Get

F0700h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:7

R

0000000h

N/A (Hard-coded)

POR - DAFG - ULR

N/A (Hard-coded)

Reserved.

6

OutEn

InEn

RW

0h

Output enable: 1 = enabled, 0 = disabled.

RW 0h

Input enable: 1 = enabled, 0 = disabled.

5

Rsvd1

4:0

R

00h

Reserved.

7.31.6. Dig1Pin (NID = 20h): ConfigDefault

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

71Dh

Byte 1 (Bits 7:0)

71Fh

71Eh

71Ch

Get

F1F00h / F1E00h / F1D00h / F1C00h

Field Name

Bits

R/W

Default

Reset

PortConnectivity

31:30

RW

2h

POR

Port connectivity:

0h = Port complex is connected to a jack

1h = No physical connection for port

2h = Fixed function device is attached

3h = Both jack and internal device attached (info in all other fields refers to in-

tegrated device, any presence detection refers to jack)

299

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

Location

29:24

RW

01h

POR

Location

Bits [5..4]:

0h = External on primary chassis

1h = Internal

2h = Separate chassis

3h = Other

Bits [3..0]:

0h = N/A

1h = Rear

2h = Front

3h = Left

4h = Right

5h = Top

6h = Bottom

7h-9h = Special

Ah-Fh = Reserved

Device

23:20

RW

Ch

POR

Default device:

0h = Line out

1h = Speaker

2h = HP out

3h = CD

4h = SPDIF Out

5h = Digital other out

6h = Modem line side

7h = Modem handset side

8h = Line in

9h = Aux

Ah = Mic in

Bh = Telephony

Ch = SPDIF In

Dh = Digital other in

Eh = Reserved

Fh = Other

300

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

ConnectionType

19:16

RW

5h

POR

Connection type:

0h = Unknown

1h = 1/8" stereo/mono

2h = 1/4" stereo/mono

3h = ATAPI internal

4h = RCA

5h = Optical

6h = Other digital

7h = Other analog

8h = Multichannel analog (DIN)

9h = XLR/Professional

Ah = RJ-11 (modem)

Bh = Combination

Ch-Eh = Reserved

Fh = Other

Color

15:12

RW

2h

POR

Color:

0h = Unknown

1h = Black

2h = Grey

3h = Blue

4h = Green

5h = Red

6h = Orange

7h = Yellow

8h = Purple

9h = Pink

Ah-Dh = Reserved

Eh = White

Fh = Other

Misc

11:8

RW

1h

POR

Miscellaneous:

Bits [3..1] = Reserved

Bit 0 = Jack detect override

Association

Sequence

7:4

RW

7h

0h

POR

Default assocation.

3:0

RW

Sequence.

301

V1.1 06/11

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Eight channel HD Audio codec optimized for low power

7.32. SPDIFOut0 (NID = 25h): WCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0009h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:24

R

00h

N/A (Hard-coded)

Reserved.

23:20

Type

R

0h

N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay

19:16

R

4h

N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1

15:12

Reserved.

11

R

0h

SwapCap

PwrCntrl

Dig

R

0h

Left/right swap support: 1 = yes, 0 = no.

10 1h

Power state support: 1 = yes, 0 = no.

1h

Digital stream support: 1 = yes (digital), 0 = no (analog).

0h N/A (Hard-coded)

R

9

R

ConnList

8

R

Connection list present: 1 = yes, 0 = no.

302

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

UnSolCap

7

R

0h

N/A (Hard-coded)

Unsolicited response support: 1 = yes, 0 = no.

0h

Processing state support: 1 = yes, 0 = no.

0h

Striping support: 1 = yes, 0 = no.

1h

Stream format override: 1 = yes, 0 = no.

1h

Amplifier capabilities override: 1 = yes, no.

1h

Output amp present: 1 = yes, 0 = no.

0h

Input amp present: 1 = yes, 0 = no.

1h

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

ProcWidget

Stripe

6

R

N/A (Hard-coded)

5

R

FormatOvrd

AmpParOvrd

OutAmpPrsnt

InAmpPrsnt

Stereo

4

R

3

R

2

R

1

R

0

R

7.32.1. SPDIFOut0 (NID = 25h): PCMCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Ah

Field Name

Bits

R/W

Default

Reset

N/A (Hard-coded)

Rsvd2

31:21

R

000h

Reserved.

303

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

B32

20

R

0h

N/A (Hard-coded)

32 bit audio format support: 1 = yes, 0 = no.

19 1h

24 bit audio format support: 1 = yes, 0 = no.

18 1h

20 bit audio format support: 1 = yes, 0 = no.

17 1h

16 bit audio format support: 1 = yes, 0 = no.

16 0h

8 bit audio format support: 1 = yes, 0 = no.

B24

B20

B16

B8

R

N/A (Hard-coded)

R

Rsvd1

R12

R11

R10

R9

15:12

Reserved.

11

R

0h

R

0h

384kHz rate support: 1 = yes, 0 = no.

10 1h

192kHz rate support: 1 = yes, 0 = no.

0h

176.4kHz rate support: 1 = yes, 0 = no.

1h

96kHz rate support: 1 = yes, 0 = no.

1h

88.2kHz rate support: 1 = yes, 0 = no.

1h

48kHz rate support: 1 = yes, 0 = no.

1h

R

9

R

8

R

R8

7

R

R7

6

R

R6

5

R

44.1kHz rate support: 1 = yes, 0 = no.

304

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

R5

4

R

0h

N/A (Hard-coded)

32kHz rate support: 1 = yes, 0 = no.

0h

22.05kHz rate support: 1 = yes, 0 = no.

0h

16kHz rate support: 1 = yes, 0 = no.

0h

11.025kHz rate support: 1 = yes, 0 = no.

0h

8kHz rate support: 1 = yes, 0 = no.

R4

R3

R2

R1

3

R

N/A (Hard-coded)

2

R

1

R

0

R

7.32.2. SPDIFOut0 (NID = 25h): StreamCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Bh

Field Name

Bits

R/W

Default

Reset

Rsvd

31:3

R

00000000h

N/A (Hard-coded)

Reserved.

2

AC3

R

1h

N/A (Hard-coded)

AC-3 formatted data support: 1 = yes, 0 = no.

0h

Float32 formatted data support: 1 = yes, 0 = no.

1h N/A (Hard-coded)

Float32

PCM

1

R

0

R

PCM-formatted data support: 1 = yes, 0 = no.

305

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Eight channel HD Audio codec optimized for low power

7.32.3. SPDIFOut0 (NID = 25h): OutAmpCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0012h

Field Name

Bits

R/W

Default

1h

Reset

Mute

31

R

N/A (Hard-coded)

Mute support: 1 = yes, 0 = no.

Rsvd3

30:23

R

00h

Reserved.

22:16

StepSize

Rsvd2

R

Size of each step in the gain range: 0 to 127 = .25dB to 32dB, in .25dB steps.

15

R

0h

N/A (Hard-coded)

Reserved.

14:8

NumSteps

Rsvd1

R

00h

N/A (Hard-coded)

Number of gains steps (number of possible settings - 1).

7

R

0h

N/A (Hard-coded)

Reserved.

6:0

Offset

R

00h

N/A (Hard-coded)

Indicates which step is 0dB

7.32.4. SPDIFOut0 (NID = 25h): Cnvtr

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

2h

Get

A0000h

306

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:16

Reserved.

15

R

0000h

N/A (Hard-coded)

FrmtNonPCM

FrmtSmplRate

SmplRateMultp

RW

0h

POR - DAFG - ULR

Stream type: 1 = Non-PCM, 0 = PCM.

14 RW 0h

Sample base rate: 1 = 44.1kHz, 0 = 48kHz.

13:11 RW 0h

Sample base rate multiple:

000b= x1 (48kHz/44.1kHz or less)

001b= x2 (96kHz/88.2kHz/32kHz)

010b= x3 (144kHz)

011b= x4 (192kHz/176.4kHz)

100b-111b Reserved

SmplRateDiv

10:8

RW

0h

POR - DAFG - ULR

Sample base rate divider:

000b= Divide by 1 (48kHz/44.1kHz)

001b= Divide by 2 (24kHz/20.05kHz)

010b= Divide by 3 (16kHz/32kHz)

011b= Divide by 4 (11.025kHz)

100b= Divide by 5 (9.6kHz)

101b= Divide by 6 (8kHz)

110b= Divide by 7

111b= Divide by 8 (6kHz)

Rsvd1

7

R

0h

3h

N/A (Hard-coded)

Reserved.

6:4

BitsPerSmpl

RW

POR - DAFG - ULR

Bits per sample:

000b= 8 bits

001b= 16 bits

010b= 20 bits

011b= 24 bits

100b= 32 bits

101b-111b= Reserved

307

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

NmbrChan

3:0

RW

1h

POR - DAFG - ULR

Total number of channels in the stream assigned to this converter:

0000b-1111b= 1-16 channels.

7.32.5. SPDIFOut0 (NID = 25h): OutAmpLeft

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

3A0h

Get

BA000h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

POR - DAFG - ULR

N/A (Hard-coded)

Reserved.

7

Mute

RW

0h

Amp mute: 1 = muted, 0 = not muted.

Rsvd1

6:0

R

00h

Reserved.

7.32.6. SPDIFOut0 (NID = 25h): OutAmpRight

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

390h

Get

B8000h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

Reserved.

308

V1.1 06/11

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

Mute

7

RW

0h

POR - DAFG - ULR

Amp mute: 1 = muted, 0 = not muted.

Rsvd1

6:0

R

00h

N/A (Hard-coded)

Reserved.

7.32.7. SPDIFOut0 (NID = 25h): PwrState

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

705h

Get

F0500h

Field Name

Bits

R/W

Default

Reset

Rsvd4

31:11

Reserved.

10

R

000000h

N/A (Hard-coded)

SettingsReset

R

1h

POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

Rsvd3

Error

9

R

0h

N/A (Hard-coded)

Reserved.

8

R

0h

POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

Rsvd2

Act

7:6

R

0h

N/A (Hard-coded)

POR - DAFG - LR

N/A (Hard-coded)

Reserved.

5:4

R

3h

Actual power state of this widget.

Rsvd1

3:2

R

0h

Reserved.

309

V1.1 06/11

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

Set

1:0

RW

3h

POR - DAFG - LR

Current power state setting for this widget.

7.32.8. SPDIFOut0 (NID = 25h): CnvtrID

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

706h

Get

F0600h

Field Name

Bits

R/W

Default

Reset

Rsvd

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7:4

Strm

Ch

RW

0h

POR - S&DAFG - LR - PS

Stream ID: 0h = Converter "off", 1h-Fh = valid ID's.

3:0 RW 0h POR - S&DAFG - LR - PS

Channel assignment ("Ch" and "Ch+1" assigned as a pair, for a stereo convert-

er).

7.32.9. SPDIFOut0 (NID = 25h): DigCnvtr

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

73Fh

73Eh

70Eh

70Dh

Get

F0E00h / F0D00h

Field Name

Bits

R/W

Default

00h

Reset

N/A (Hard-coded)

Rsvd2

31:24

R

Reserved.

310

V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

KeepAlive

23

RW

0h

POR - DAFG - ULR

Keep Alive Enable: 1 = clocking information maintained during D3, 0 = clock

information not required during D3.

Rsvd1

CC

22:15

R

00h

0h

N/A (Hard-coded)

Reserved.

14:8

RW

POR - DAFG - ULR

CC: Category Code.

RW

L: Generation Level.

RW

PRO: Professional.

RW

/AUDIO: Non-Audio.

RW

COPY: Copyright.

RW

PRE: Preemphasis.

RW

VCFG: Validity Config.

L

7

PRO

AUDIO

COPY

PRE

VCFG

V

6

5

4

3

2

1

RW

V: Validity.

0

DigEn

RW

Digital enable: 1 = converter enabled, 0 = converter disable.

311

V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

7.33. SPDIFOut1 (NID = 26h): WCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0009h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:24

R

00h

N/A (Hard-coded)

Reserved.

23:20

Type

R

0h

N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay

19:16

R

4h

N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1

15:12

Reserved.

11

R

0h

SwapCap

PwrCntrl

Dig

R

0h

Left/right swap support: 1 = yes, 0 = no.

10 1h

Power state support: 1 = yes, 0 = no.

1h

Digital stream support: 1 = yes (digital), 0 = no (analog).

0h N/A (Hard-coded)

R

9

R

ConnList

8

R

Connection list present: 1 = yes, 0 = no.

312

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

UnSolCap

7

R

0h

N/A (Hard-coded)

Unsolicited response support: 1 = yes, 0 = no.

0h

Processing state support: 1 = yes, 0 = no.

0h

Striping support: 1 = yes, 0 = no.

1h

Stream format override: 1 = yes, 0 = no.

1h

Amplifier capabilities override: 1 = yes, no.

1h

Output amp present: 1 = yes, 0 = no.

0h

Input amp present: 1 = yes, 0 = no.

1h

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

ProcWidget

Stripe

6

R

N/A (Hard-coded)

5

R

FormatOvrd

AmpParOvrd

OutAmpPrsnt

InAmpPrsnt

Stereo

4

R

3

R

2

R

1

R

0

R

7.33.1. SPDIFOut1 (NID = 26h): PCMCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Ah

Field Name

Bits

R/W

Default

Reset

N/A (Hard-coded)

Rsvd2

31:21

R

000h

Reserved.

313

V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

B32

20

R

0h

N/A (Hard-coded)

32 bit audio format support: 1 = yes, 0 = no.

19 1h

24 bit audio format support: 1 = yes, 0 = no.

18 1h

20 bit audio format support: 1 = yes, 0 = no.

17 1h

16 bit audio format support: 1 = yes, 0 = no.

16 0h

8 bit audio format support: 1 = yes, 0 = no.

B24

B20

B16

B8

R

N/A (Hard-coded)

R

Rsvd1

R12

R11

R10

R9

15:12

Reserved.

11

R

0h

R

0h

384kHz rate support: 1 = yes, 0 = no.

10 1h

192kHz rate support: 1 = yes, 0 = no.

0h

176.4kHz rate support: 1 = yes, 0 = no.

1h

96kHz rate support: 1 = yes, 0 = no.

1h

88.2kHz rate support: 1 = yes, 0 = no.

1h

48kHz rate support: 1 = yes, 0 = no.

1h

R

9

R

8

R

R8

7

R

R7

6

R

R6

5

R

44.1kHz rate support: 1 = yes, 0 = no.

314

V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

R5

4

R

0h

N/A (Hard-coded)

32kHz rate support: 1 = yes, 0 = no.

0h

22.05kHz rate support: 1 = yes, 0 = no.

0h

16kHz rate support: 1 = yes, 0 = no.

0h

11.025kHz rate support: 1 = yes, 0 = no.

0h

8kHz rate support: 1 = yes, 0 = no.

R4

R3

R2

R1

3

R

N/A (Hard-coded)

2

R

1

R

0

R

7.33.2. SPDIFOut1 (NID = 26h): StreamCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Bh

Field Name

Bits

R/W

Default

Reset

Rsvd

31:3

R

00000000h

N/A (Hard-coded)

Reserved.

2

AC3

R

1h

N/A (Hard-coded)

AC-3 formatted data support: 1 = yes, 0 = no.

0h

Float32 formatted data support: 1 = yes, 0 = no.

1h N/A (Hard-coded)

Float32

PCM

1

R

0

R

PCM-formatted data support: 1 = yes, 0 = no.

315

V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

7.33.3. SPDIFOut1 (NID = 26h): OutAmpCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0012h

Field Name

Bits

R/W

Default

1h

Reset

Mute

31

R

N/A (Hard-coded)

Mute support: 1 = yes, 0 = no.

Rsvd3

30:23

R

00h

Reserved.

22:16

StepSize

Rsvd2

R

Size of each step in the gain range: 0 to 127 = .25dB to 32dB, in .25dB steps.

15

R

0h

N/A (Hard-coded)

Reserved.

14:8

NumSteps

Rsvd1

R

00h

N/A (Hard-coded)

Number of gains steps (number of possible settings - 1).

7

R

0h

N/A (Hard-coded)

Reserved.

6:0

Offset

R

00h

N/A (Hard-coded)

Indicates which step is 0dB

7.33.4. SPDIFOut1 (NID = 26h): Cnvtr

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

2h

Get

A0000h

316

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:16

Reserved.

15

R

0000h

N/A (Hard-coded)

FrmtNonPCM

FrmtSmplRate

SmplRateMultp

RW

0h

POR - DAFG - ULR

Stream type: 1 = Non-PCM, 0 = PCM.

14 RW 0h

Sample base rate: 1 = 44.1kHz, 0 = 48kHz.

13:11 RW 0h

Sample base rate multiple:

000b= x1 (48kHz/44.1kHz or less)

001b= x2 (96kHz/88.2kHz/32kHz)

010b= x3 (144kHz)

011b= x4 (192kHz/176.4kHz)

100b-111b Reserved

SmplRateDiv

10:8

RW

0h

POR - DAFG - ULR

Sample base rate divider:

000b= Divide by 1 (48kHz/44.1kHz)

001b= Divide by 2 (24kHz/20.05kHz)

010b= Divide by 3 (16kHz/32kHz)

011b= Divide by 4 (11.025kHz)

100b= Divide by 5 (9.6kHz)

101b= Divide by 6 (8kHz)

110b= Divide by 7

111b= Divide by 8 (6kHz)

Rsvd1

7

R

0h

3h

N/A (Hard-coded)

Reserved.

6:4

BitsPerSmpl

RW

POR - DAFG - ULR

Bits per sample:

000b= 8 bits

001b= 16 bits

010b= 20 bits

011b= 24 bits

100b= 32 bits

101b-111b= Reserved

317

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

NmbrChan

3:0

RW

1h

POR - DAFG - ULR

Total number of channels in the stream assigned to this converter:

0000b-1111b= 1-16 channels.

7.33.5. SPDIFOut1 (NID = 26h): OutAmpLeft

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

3A0h

Get

BA000h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

POR - DAFG - ULR

N/A (Hard-coded)

Reserved.

7

Mute

RW

0h

Amp mute: 1 = muted, 0 = not muted.

Rsvd1

6:0

R

00h

Reserved.

7.33.6. SPDIFOut1 (NID = 26h): OutAmpRight

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

390h

Get

B8000h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

Reserved.

318

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

Mute

7

RW

0h

POR - DAFG - ULR

Amp mute: 1 = muted, 0 = not muted.

Rsvd1

6:0

R

00h

N/A (Hard-coded)

Reserved.

7.33.7. SPDIFOut1 (NID = 26h): PwrState

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

705h

Get

F0500h

Field Name

Bits

R/W

Default

Reset

Rsvd4

31:11

Reserved.

10

R

000000h

N/A (Hard-coded)

SettingsReset

R

1h

POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

Rsvd3

Error

9

R

0h

N/A (Hard-coded)

Reserved.

8

R

0h

POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

Rsvd2

Act

7:6

R

0h

N/A (Hard-coded)

POR - DAFG - LR

N/A (Hard-coded)

Reserved.

5:4

R

3h

Actual power state of this widget.

Rsvd1

3:2

R

0h

Reserved.

319

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

Set

1:0

RW

3h

POR - DAFG - LR

Current power state setting for this widget.

7.33.8. SPDIFOut1 (NID = 26h): CnvtrID

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

706h

Get

F0600h

Field Name

Bits

R/W

Default

Reset

Rsvd

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7:4

Strm

Ch

RW

0h

POR - S&DAFG - LR - PS

Stream ID: 0h = Converter "off", 1h-Fh = valid ID's.

3:0 RW 0h POR - S&DAFG - LR - PS

Channel assignment ("Ch" and "Ch+1" assigned as a pair, for a stereo convert-

er).

7.33.9. SPDIFOut1 (NID = 26h): DigCnvtr

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

73Fh

73Eh

70Eh

70Dh

Get

F0E00h / F0D00h

Field Name

Bits

R/W

Default

00h

Reset

N/A (Hard-coded)

Rsvd2

31:24

R

Reserved.

320

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

KeepAlive

23

RW

0h

POR - DAFG - ULR

Keep Alive Enable: 1 = clocking information maintained during D3, 0 = clock

information not required during D3.

Rsvd1

CC

22:15

R

00h

0h

N/A (Hard-coded)

Reserved.

14:8

RW

POR - DAFG - ULR

CC: Category Code.

RW

L: Generation Level.

RW

PRO: Professional.

RW

/AUDIO: Non-Audio.

RW

COPY: Copyright.

RW

PRE: Preemphasis.

RW

VCFG: Validity Config.

L

7

PRO

AUDIO

COPY

PRE

VCFG

V

6

5

4

3

2

1

RW

V: Validity.

0

DigEn

RW

Digital enable: 1 = converter enabled, 0 = converter disable.

321

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Eight channel HD Audio codec optimized for low power

7.34. SPDIFIn (NID = 27h): WCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0009h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:24

R

00h

N/A (Hard-coded)

Reserved.

23:20

Type

R

1h

N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay

19:16

R

4h

N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1

15:12

Reserved.

11

R

0h

SwapCap

PwrCntrl

Dig

R

0h

Left/right swap support: 1 = yes, 0 = no.

10 1h

Power state support: 1 = yes, 0 = no.

1h

Digital stream support: 1 = yes (digital), 0 = no (analog).

1h N/A (Hard-coded)

R

9

R

ConnList

8

R

Connection list present: 1 = yes, 0 = no.

322

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

UnSolCap

7

R

0h

N/A (Hard-coded)

Unsolicited response support: 1 = yes, 0 = no.

0h

Processing state support: 1 = yes, 0 = no.

0h

Striping support: 1 = yes, 0 = no.

1h

Stream format override: 1 = yes, 0 = no.

1h

Amplifier capabilities override: 1 = yes, no.

0h

Output amp present: 1 = yes, 0 = no.

1h

Input amp present: 1 = yes, 0 = no.

1h

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

ProcWidget

Stripe

6

R

N/A (Hard-coded)

5

R

FormatOvrd

AmpParOvrd

OutAmpPrsnt

InAmpPrsnt

Stereo

4

R

3

R

2

R

1

R

0

R

7.34.1. SPDIFIn (NID = 27h): PCMCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Ah

Field Name

Bits

R/W

Default

Reset

N/A (Hard-coded)

Rsvd2

31:21

R

000h

Reserved.

323

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

B32

20

R

0h

N/A (Hard-coded)

32 bit audio format support: 1 = yes, 0 = no.

19 1h

24 bit audio format support: 1 = yes, 0 = no.

18 1h

20 bit audio format support: 1 = yes, 0 = no.

17 1h

16 bit audio format support: 1 = yes, 0 = no.

16 0h

8 bit audio format support: 1 = yes, 0 = no.

B24

B20

B16

B8

R

N/A (Hard-coded)

R

Rsvd1

R12

R11

R10

R9

15:12

Reserved.

11

R

0h

R

0h

384kHz rate support: 1 = yes, 0 = no.

10 0h

192kHz rate support: 1 = yes, 0 = no.

0h

176.4kHz rate support: 1 = yes, 0 = no.

1h

96kHz rate support: 1 = yes, 0 = no.

0h

88.2kHz rate support: 1 = yes, 0 = no.

1h

48kHz rate support: 1 = yes, 0 = no.

1h

R

9

R

8

R

R8

7

R

R7

6

R

R6

5

R

44.1kHz rate support: 1 = yes, 0 = no.

324

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

R5

4

R

0h

N/A (Hard-coded)

32kHz rate support: 1 = yes, 0 = no.

0h

22.05kHz rate support: 1 = yes, 0 = no.

0h

16kHz rate support: 1 = yes, 0 = no.

0h

11.025kHz rate support: 1 = yes, 0 = no.

0h

8kHz rate support: 1 = yes, 0 = no.

R4

R3

R2

R1

3

R

N/A (Hard-coded)

2

R

1

R

0

R

7.34.2. SPDIFIn (NID = 27h): StreamCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Bh

Field Name

Bits

R/W

Default

Reset

Rsvd

31:3

R

00000000h

N/A (Hard-coded)

Reserved.

2

AC3

R

1h

N/A (Hard-coded)

AC-3 formatted data support: 1 = yes, 0 = no.

0h

Float32 formatted data support: 1 = yes, 0 = no.

1h N/A (Hard-coded)

Float32

PCM

1

R

0

R

PCM-formatted data support: 1 = yes, 0 = no.

325

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Eight channel HD Audio codec optimized for low power

7.34.3. SPDIFIn (NID = 27h): Cnvtr

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

2h

Get

A0000h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:16

Reserved.

15

R

0000h

N/A (Hard-coded)

POR - DAFG - ULR

FrmtNonPCM

FrmtSmplRate

SmplRateMultp

RW

0h

Stream type: 1 = Non-PCM, 0 = PCM.

14 RW 0h

Sample base rate: 1 = 44.1kHz, 0 = 48kHz.

13:11 RW 0h

Sample base rate multiple:

000b= x1 (48kHz/44.1kHz or less)

001b= x2 (96kHz/88.2kHz/32kHz)

010b= x3 (144kHz)

011b= x4 (192kHz/176.4kHz)

100b-111b Reserved

SmplRateDiv

10:8

RW

0h

POR - DAFG - ULR

Sample base rate divider:

000b= Divide by 1 (48kHz/44.1kHz)

001b= Divide by 2 (24kHz/20.05kHz)

010b= Divide by 3 (16kHz/32kHz)

011b= Divide by 4 (11.025kHz)

100b= Divide by 5 (9.6kHz)

101b= Divide by 6 (8kHz)

110b= Divide by 7

111b= Divide by 8 (6kHz)

Rsvd1

7

R

0h

N/A (Hard-coded)

Reserved.

326

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Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

BitsPerSmpl

6:4

RW

3h

POR - DAFG - ULR

Bits per sample:

000b= 8 bits

001b= 16 bits

010b= 20 bits

011b= 24 bits

100b= 32 bits

101b-111b= Reserved

NmbrChan

3:0

RW

1h

POR - DAFG - ULR

Total number of channels in the stream assigned to this converter:

0000b-1111b= 1-16 channels.

7.34.4. SPDIFIn (NID = 27h): ConLst

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Eh

Field Name

Bits

R/W

Default

Reset

Rsvd

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

LForm

ConL

R

0h

N/A (Hard-coded)

Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)

NID entries.

6:0

R

01h

N/A (Hard-coded)

Number of NID entries in connection list.

7.34.5. SPDIFIn (NID = 27h): ConLstEntry0

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0200h

327

V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

ConL3

31:24

Unused

23:16

Unused

15:8

R

00h

N/A (Hard-coded)

ConL2

ConL1

ConL0

R

00h

24h

N/A (Hard-coded)

Unused

7:0

Dig2Pin pin widget (0x24

7.34.6. SPDIFIn (NID = 27h): PwrState

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

705h

Get

F0500h

Field Name

Bits

R/W

Default

Reset

Rsvd4

31:11

Reserved.

10

R

000000h

N/A (Hard-coded)

SettingsReset

R

1h

POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

Rsvd3

Error

9

R

0h

N/A (Hard-coded)

Reserved.

8

R

0h

POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

328

V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

Rsvd2

7:6

R

0h

N/A (Hard-coded)

Reserved.

5:4

Act

R

3h

POR - DAFG - LR

N/A (Hard-coded)

POR - DAFG - LR

Actual power state of this widget.

Rsvd1

Set

3:2

R

0h

Reserved.

1:0

RW

3h

Current power state setting for this widget.

7.34.7. SPDIFIn (NID = 27h): CnvtrID

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

706h

Get

F0600h

Field Name

Bits

R/W

Default

Reset

Rsvd

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7:4

Strm

Ch

RW

0h

POR - S&DAFG - LR - PS

Stream ID: 0h = Converter "off", 1h-Fh = valid ID's.

3:0 RW 0h POR - S&DAFG - LR - PS

Channel assignment ("Ch" and "Ch+1" assigned as a pair, for a stereo convert-

er).

7.34.8. SPDIFIn (NID = 27h): DigCnvtr

Reg

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Set

73Fh

73Eh

70Eh

70Dh

329

V1.1 06/11

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Eight channel HD Audio codec optimized for low power

7.34.8. SPDIFIn (NID = 27h): DigCnvtr

Reg

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0E00h / F0D00h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:24

Reserved.

23

R

00h

N/A (Hard-coded)

KeepAlive

RW

0h

POR - DAFG - ULR

Keep Alive Enable: 1 = clocking information maintained during D3, 0 = clock

information not required during D3.

Rsvd1

CC

22:15

R

00h

0h

N/A (Hard-coded)

Reserved.

14:8

RW

POR - DAFG - ULR

CC: Category Code.

RW

L: Generation Level.

RW

PRO: Professional.

RW

/AUDIO: Non-Audio.

RW

COPY: Copyright.

RW

PRE: Preemphasis.

RW

VCFG: Validity Config.

L

7

PRO

AUDIO

COPY

PRE

VCFG

V

6

0h

5

0h

4

0h

3

0h

2

0h

1

RW

0h

V: Validity.

330

V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

DigEn

0

RW

0h

POR - DAFG - ULR

Digital enable: 1 = converter enabled, 0 = converter disable.

7.34.9. SPDIFIn (NID = 27h): InAmpCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Dh

Field Name

Bits

R/W

Default

1h

Reset

Mute

31

R

N/A (Hard-coded)

Mute support: 1 = yes, 0 = no.

Rsvd3

30:23

R

00h

05h

Reserved.

22:16

StepSize

Rsvd2

Size of each step in the gain range: 0 to 127 = .25dB to 32dB, in .25dB steps.

15

R

0h

N/A (Hard-coded)

Reserved.

14:8

NumSteps

Rsvd1

00h

Number of gains steps (number of possible settings - 1).

7

R

0h

N/A (Hard-coded)

Reserved.

6:0

Offset

R

00h

N/A (Hard-coded)

Indicates which step is 0dB

331

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Eight channel HD Audio codec optimized for low power

7.34.10. SPDIFIn (NID = 27h): InAmpLeft

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

360h

Get

B2000h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

POR - DAFG - ULR

N/A (Hard-coded)

Reserved.

7

Mute

RW

0h

Amp mute: 1 = muted, 0 = not muted

Rsvd1

6:0

R

0h

Reserved.

7.34.11. SPDIFIn (NID = 27h): InAmpRight

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

350h

Get

B0000h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

Mute

RW

0h

POR - DAFG - ULR

N/A (Hard-coded)

Amp mute: 1 = muted, 0 = not muted

Rsvd1

6:0

R

0h

Reserved.

7.34.12. SPDIFIn (NID = 27h): VS

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

7E8h

Get

FE800h

332

V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

RcvSmplRate

31:29

R

7h

POR - DAFG - ULR

Received Sample Rate:

000b = 44.1kHz

001b = 48kHz

010b = 88.2kHz

011b = 96kHz

100b = 176.4kHz

101b = 192kHz

11Xb = Invalid Rate

Rsvd2

28:26

R

0h

POR - DAFG - ULR

Reserved.

25:22

OrigFS

R

Original Sample Rate (per IEC60958-3 spec):

0000b = Original sampling frequency not indicated

0001b = 192kHz

0010b = 12kHz

0011b = 176.4kHz

0100b = Reserved

0101b = 96kHz

0110b = 8kHz

0111b = 88.2kHz

1000b = 16kHz

1001b = 24kHz

1010b = 11.025kHz

1011b = 22.05kHz

1100b = 32kHz

1101b = 48khz

1110b = Reserved

1111b = 44.1kHz

CA

21:20

R

0h

POR - DAFG - ULR

Clock Accuracy (per IEC60958-3 spec):

00b = Level II

01b = Level I

10b = Level III

11b = Reserved

333

V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

FS

19:16

R

0h

POR - DAFG - ULR

Sample Rate (per IEC60958-3 spec):

0000b = 44.1kHz

0001b = Original sampling frequency not indicated

0010b = 48kHz

0011b = 32kHz

0100b = 22.05kHz

0101b = Reserved

0110b = 24kHz

0111b = Reserved

1000b = 88.2kHz

1001b = Reserved

1010b = 96kHz

1011b = Reserved

1100b = 176.4kHz

1101b = Reserved

1110b = 192kHz

1111b = Reserved

CN

15:12

R

0h

POR - DAFG - ULR

Channel Number (per IEC60958-3 spec):

0000b = Do not take into account

0001b = Channel 1 (Left channel for stereo channel format)

0010b = Channel 2 (Right channel for stereo channel format)

0011b-1111b = Channel 3-15

SamplWrdL

11:9

R

0h

POR - DAFG - ULR

Sample Word Length (per IEC60958-3 spec):

000b = Word length not indicated

001b = Max length - 4

010b = Max length - 2

011b = Reserved

100b = Max length - 1

101b = Max length - 0

110b = Max length - 3

111b = Reserved

MaxWrdL

NoBlkChk

Rsvd

8

R

0h

POR - DAFG - ULR

Max Word Length (per IEC60958-3 spec): 0 = 20 bits, 1 = 24 bits.

7

RW

0h

POR - DAFG - ULR

N/A (Hard-coded)

Disable Sample Block Checking.

6:5

R

0h

Reserved.

334

V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

ParityLimit

4:3

RW

0h

POR - DAFG - ULR

SPDIFIn Parity Limit (DPLL loses lock when the set number of parity errors per

block is detected):

00b = 4 Parity errors

01b = 3 Parity errors

10b = 2 Parity errors

11b = 1 Parity errors

SPRun

SiPerr

2

R

0h

SPDIFIn Running 0 = no signal on SPDIFIn Pin, 1 = Signal on SPDIFIn pin.

RW 0h POR - DAFG - ULR

POR - DAFG - ULR

1

SPDIFIn Parity Error: 0 = No error detected, 1 = Error detected (write 0 to

clear). Not affected by ParityLimit.

CopyInv

0

RW

0h

POR - DAFG - ULR

Copyright Invert: 0 = Do not invert COPY bit, 1 = Invert COPY bit..

335

V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

7.35. InPort0Mux (NID = 28h): WCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0009h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:24

R

00h

N/A (Hard-coded)

Reserved.

23:20

Type

R

3h

N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay

19:16

R

0h

N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1

15:12

Reserved.

11

R

0h

SwapCap

PwrCntrl

DigitalStrm

ConnList

R

0h

Left/right swap support: 1 = yes, 0 = no.

10 1h

Power state support: 1 = yes, 0 = no.

0h

Digital stream support: 1 = yes (digital), 0 = no (analog).

1h N/A (Hard-coded)

R

9

R

8

R

Connection list present: 1 = yes, 0 = no.

336

V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

UnsolCap

7

R

0h

N/A (Hard-coded)

Unsolicited response support: 1 = yes, 0 = no.

0h

Processing state support: 1 = yes, 0 = no.

0h

Striping support: 1 = yes, 0 = no.

0h

Stream format override: 1 = yes, 0 = no.

0h

Amplifier capabilities override: 1 = yes, no.

0h

Output amp present: 1 = yes, 0 = no.

0h

Input amp present: 1 = yes, 0 = no.

1h

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

ProcWidget

Stripe

6

R

N/A (Hard-coded)

5

R

FormatOvrd

AmpParamOvrd

OutAmpPrsnt

InAmpPrsnt

Stereo

4

R

3

R

2

R

1

R

0

R

7.35.1. InPort0Mux (NID = 28h): ConLst

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Eh

Field Name

Bits

R/W

Default

Reset

N/A (Hard-coded)

Rsvd

31:8

R

000000h

Reserved.

337

V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

LForm

7

R

0h

N/A (Hard-coded)

Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)

NID entries.

ConL

6:0

R

04h

N/A (Hard-coded)

Number of NID entries in connection list.

7.35.2. InPort0Mux (NID = 28h): ConLstEntry0

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0200h

Field Name

Bits

R/W

Default

Reset

ConL3

31:24

R

0Fh

N/A (Hard-coded)

Port Fwidget (0x0F)

23:16

Port D Pin widget (0x0D)

15:8

Port B Pin widget (0x0B)

7:0

Port A Pin widget (0x0A)

ConL2

ConL1

ConL0

R

0Dh

0Bh

0Ah

N/A (Hard-coded)

R

7.35.3. InPort0Mux (NID = 28h): ConSelectCtrl

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

701h

Get

F0100h

338

V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

Rsvd

31:3

R

00000000h

N/A (Hard-coded)

Reserved.

2:0

Index

RW

0h

POR - DAFG - ULR

Connection select control index.

7.35.4. InPort0Mux (NID = 28h): PwrState

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

705h

Get

F0500h

Field Name

Bits

R/W

Default

Reset

Rsvd4

31:11

Reserved.

10

R

000000h

N/A (Hard-coded)

SettingsReset

R

1h

POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

Rsvd3

Error

9

R

0h

N/A (Hard-coded)

Reserved.

8

R

0h

POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

Rsvd2

Act

7:6

R

0h

N/A (Hard-coded)

Reserved.

5:4

R

3h

POR - DAFG - LR

Actual power state of this widget.

339

V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

Rsvd1

3:2

R

0h

N/A (Hard-coded)

Reserved.

1:0

Set

RW

0h

POR - DAFG - LR

Current power state setting for this widget.

340

V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

7.36. InPort1Mux (NID = 29h): WCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0009h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:24

R

00h

N/A (Hard-coded)

Reserved.

23:20

Type

R

3h

N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay

19:16

R

0h

N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1

15:12

Reserved.

11

R

0h

SwapCap

PwrCntrl

DigitalStrm

ConnList

R

0h

Left/right swap support: 1 = yes, 0 = no.

10 1h

Power state support: 1 = yes, 0 = no.

0h

Digital stream support: 1 = yes (digital), 0 = no (analog).

1h N/A (Hard-coded)

R

9

R

8

R

Connection list present: 1 = yes, 0 = no.

341

V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

UnsolCap

7

R

0h

N/A (Hard-coded)

Unsolicited response support: 1 = yes, 0 = no.

0h

Processing state support: 1 = yes, 0 = no.

0h

Striping support: 1 = yes, 0 = no.

0h

Stream format override: 1 = yes, 0 = no.

0h

Amplifier capabilities override: 1 = yes, no.

0h

Output amp present: 1 = yes, 0 = no.

0h

Input amp present: 1 = yes, 0 = no.

1h

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

ProcWidget

Stripe

6

R

N/A (Hard-coded)

5

R

FormatOvrd

AmpParamOvrd

OutAmpPrsnt

InAmpPrsnt

Stereo

4

R

3

R

2

R

1

R

0

R

7.36.1. InPort1Mux (NID = 29h): ConLst

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Eh

Field Name

Bits

R/W

Default

Reset

N/A (Hard-coded)

Rsvd

31:8

R

000000h

Reserved.

342

V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

LForm

7

R

0h

N/A (Hard-coded)

Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)

NID entries.

ConL

6:0

R

04h

N/A (Hard-coded)

Number of NID entries in connection list.

7.36.2. InPort1Mux (NID = 29h): ConLstEntry0

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0200h

Field Name

Bits

R/W

Default

Reset

ConL3

31:24

R

11h

N/A (Hard-coded)

Port H Pin widget (0x11)

23:16

Port G Pin widget (0x10)

15:8

Port E Pin widget (0x0E)

7:0

Port A Pin widget (0x0A)

ConL2

ConL1

ConL0

R

10h

0Eh

0Ah

N/A (Hard-coded)

R

7.36.3. InPort1Mux (NID = 29h): ConSelectCtrl

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

701h

Get

F0100h

343

V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

Rsvd

31:3

R

00000000h

N/A (Hard-coded)

Reserved.

2:0

Index

RW

0h

POR - DAFG - ULR

Connection select control index.

7.36.4. InPort1Mux (NID = 29h): PwrState

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

705h

Get

F0500h

Field Name

Bits

R/W

Default

Reset

Rsvd4

31:11

Reserved.

10

R

000000h

N/A (Hard-coded)

SettingsReset

R

1h

POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

Rsvd3

Error

9

R

0h

N/A (Hard-coded)

Reserved.

8

R

0h

POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

Rsvd2

Act

7:6

R

0h

N/A (Hard-coded)

Reserved.

5:4

R

3h

POR - DAFG - LR

Actual power state of this widget.

344

V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

Rsvd1

3:2

R

0h

N/A (Hard-coded)

Reserved.

1:0

Set

RW

0h

POR - DAFG - LR

Current power state setting for this widget.

345

V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

7.37. InPort2Mux (NID = 2Ah): WCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0009h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:24

R

00h

N/A (Hard-coded)

Reserved.

23:20

Type

R

3h

N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay

19:16

R

0h

N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1

15:12

Reserved.

11

R

0h

SwapCap

PwrCntrl

DigitalStrm

ConnList

R

0h

Left/right swap support: 1 = yes, 0 = no.

10 1h

Power state support: 1 = yes, 0 = no.

0h

Digital stream support: 1 = yes (digital), 0 = no (analog).

1h N/A (Hard-coded)

R

9

R

8

R

Connection list present: 1 = yes, 0 = no.

346

V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

UnsolCap

7

R

0h

N/A (Hard-coded)

Unsolicited response support: 1 = yes, 0 = no.

0h

Processing state support: 1 = yes, 0 = no.

0h

Striping support: 1 = yes, 0 = no.

0h

Stream format override: 1 = yes, 0 = no.

0h

Amplifier capabilities override: 1 = yes, no.

0h

Output amp present: 1 = yes, 0 = no.

0h

Input amp present: 1 = yes, 0 = no.

1h

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

ProcWidget

Stripe

6

R

N/A (Hard-coded)

5

R

FormatOvrd

AmpParamOvrd

OutAmpPrsnt

InAmpPrsnt

Stereo

4

R

3

R

2

R

1

R

0

R

7.37.1. InPort2Mux (NID = 2Ah): ConLst

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Eh

Field Name

Bits

R/W

Default

Reset

N/A (Hard-coded)

Rsvd

31:8

R

000000h

Reserved.

347

V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

LForm

7

R

0h

N/A (Hard-coded)

Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)

NID entries.

ConL

6:0

R

04h

N/A (Hard-coded)

Number of NID entries in connection list.

7.37.2. InPort2Mux (NID = 2Ah): ConLstEntry0

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0200h

Field Name

Bits

R/W

Default

Reset

ConL3

31:24

R

11h

N/A (Hard-coded)

Port H Pin widget (0x11)Port H Pin widget (0x11)

ConL2

ConL1

ConL0

23:16

Port G Pin widget (0x10)

15:8

Port C Pin widget (0x0C)

7:0

Port B Pin widget (0x0B)

R

10h

0Ch

0Bh

N/A (Hard-coded)

R

7.37.3. InPort2Mux (NID = 2Ah): ConSelectCtrl

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

701h

Get

F0100h

348

V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

Rsvd

31:3

R

00000000h

N/A (Hard-coded)

Reserved.

2:0

Index

RW

0h

POR - DAFG - ULR

Connection select control index.

7.37.4. InPort2Mux (NID = 2Ah): PwrState

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

705h

Get

F0500h

Field Name

Bits

R/W

Default

Reset

Rsvd4

31:11

Reserved.

10

R

000000h

N/A (Hard-coded)

SettingsReset

R

1h

POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

Rsvd3

Error

9

R

0h

N/A (Hard-coded)

Reserved.

8

R

0h

POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

Rsvd2

Act

7:6

R

0h

N/A (Hard-coded)

Reserved.

5:4

R

3h

POR - DAFG - LR

Actual power state of this widget.

349

V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

Rsvd1

3:2

R

0h

N/A (Hard-coded)

Reserved.

1:0

Set

RW

0h

POR - DAFG - LR

Current power state setting for this widget.

350

V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

7.38. InPort3Mux (NID = 2Bh): WCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0009h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:24

R

00h

N/A (Hard-coded)

Reserved.

23:20

Type

R

3h

N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay

19:16

R

0h

N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1

15:12

Reserved.

11

R

0h

SwapCap

PwrCntrl

DigitalStrm

ConnList

R

0h

Left/right swap support: 1 = yes, 0 = no.

10 1h

Power state support: 1 = yes, 0 = no.

0h

Digital stream support: 1 = yes (digital), 0 = no (analog).

1h N/A (Hard-coded)

R

9

R

8

R

Connection list present: 1 = yes, 0 = no.

351

V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

UnsolCap

7

R

0h

N/A (Hard-coded)

Unsolicited response support: 1 = yes, 0 = no.

0h

Processing state support: 1 = yes, 0 = no.

0h

Striping support: 1 = yes, 0 = no.

0h

Stream format override: 1 = yes, 0 = no.

0h

Amplifier capabilities override: 1 = yes, no.

0h

Output amp present: 1 = yes, 0 = no.

0h

Input amp present: 1 = yes, 0 = no.

1h

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

ProcWidget

Stripe

6

R

N/A (Hard-coded)

5

R

FormatOvrd

AmpParamOvrd

OutAmpPrsnt

InAmpPrsnt

Stereo

4

R

3

R

2

R

1

R

0

R

7.38.1. InPort3Mux (NID = 2Bh): ConLst

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Eh

Field Name

Bits

R/W

Default

Reset

N/A (Hard-coded)

Rsvd

31:8

R

000000h

Reserved.

352

V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

LForm

7

R

0h

N/A (Hard-coded)

Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)

NID entries.

ConL

6:0

R

04h

N/A (Hard-coded)

Number of NID entries in connection list.

7.38.2. InPort3Mux (NID = 2Bh): ConLstEntry0

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0200h

Field Name

Bits

R/W

Default

Reset

ConL3

31:24

R

18h

N/A (Hard-coded)

DAC3 widget (0x18)

23:16

DAC2 widget (0x17)

15:8

DAC1 widget (0x16)

7:0

DAC0 widget (0x15

ConL2

ConL1

ConL0

R

17h

16h

15h

N/A (Hard-coded)

R

7.38.3. InPort3Mux (NID = 2Bh): ConSelectCtrl

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

701h

Get

F0100h

353

V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

Rsvd

31:3

R

00000000h

N/A (Hard-coded)

Reserved.

2:0

Index

RW

0h

POR - DAFG - ULR

Connection select control index.

7.38.4. InPort3Mux (NID = 2Bh): PwrState

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

705h

Get

F0500h

Field Name

Bits

R/W

Default

Reset

Rsvd4

31:11

Reserved.

10

R

000000h

N/A (Hard-coded)

SettingsReset

R

1h

POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

Rsvd3

Error

9

R

0h

N/A (Hard-coded)

Reserved.

8

R

0h

POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

Rsvd2

Act

7:6

R

0h

N/A (Hard-coded)

Reserved.

5:4

R

3h

POR - DAFG - LR

Actual power state of this widget.

354

V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

Field Name

Bits

R/W

Default

Reset

Rsvd1

3:2

R

0h

N/A (Hard-coded)

Reserved.

1:0

Set

RW

0h

POR - DAFG - LR

Current power state setting for this widget.

355

V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

8. PINOUTS AND PACKAGING

8.1. 48QFP

8.1.1.

48 QFP Pin Assignment

DVDD_LV

1

36

35

34

33

32

31

30

29

28

27

26

25

PORTD_R

PORTD_L

SENSE_B

CAP 2

DMIC_CLK/GPIO3

DVDD_IO

DMIC_0/GPIO4

SDO

2

3

4

5

SENSE_C

VREFOUT-E/GPIO2

DMIC1/GPIO6

VREFOUT-C

VREFOUT-B

VREFFILT

AVSS1

BITCLK

6

48-QFP

DVSS

7

SDI

8

DVDD

9

SYNC

10

11

12

RESET#

PCBeep

AVDD1

Figure 14. Pin Assignment

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8.1.2.

48QFP Pin Table

Internal Pull-up 48 pin

Pin Name

Pin Function

I/O

Pull-down

location

DVDD_LV

1.5V Digital Core Regulator Filter Cap

Digital Mic Clock Output/GPIO3

Reference Voltage (1.5V or 3.3V)

Digital Mic 01 Input/GPIO4

HD Audio Serial Data output from controller

HD Audio Bit Clock

Digital Ground

O(Power)

I/O(Digital)

I(Power)

None

1

DMIC_CLK/GPIO3

DVDD_IO

DMIC0/GPIO4

SDATA_OUT

BITCLK

60K Pull-down 2

None

60K Pull-down 4

3

I/O(Digital)

I(Digital)

None

5

I(Digital)

6

DVSS

I(Digital)

7

SDATA_IN

DVDD

HD Audio Serial Data Input to controller

Digital Vdd= 3.3V

I/O(Digital)

I(Power)

8

9

SYNC

HD Audio Frame Sync

HD Audio Reset

I(Digital)

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

RESET#

I(Digital)

PCBeep

PC Beep Input

I(Analog)

I/O(Analog)

I(Analog)

I/O(Analog)

I(Analog)

O(Analog)

SENSE_A

PORTE_L

PORTE_R

PORTF_L

PORTF_R

CD Left

Jack insertion detection

Port E Left

Port E Right

Port F Left

Port F Right

CD Left

CD Common

CD Right

CD L/R return

CD Right

PORTB_L (HP)

PORTB_R (HP)

PORTC_L

PORTC_R

AVDD1

Port B Output Left

Port B Output Right

Port C Left

Port C Right

Analog Vdd=5.0V or 3.3V

Analog Ground

AVSS1

VREFFILT

Analog Virtual Ground

Reference Voltage out drive (intended for mic

bias)

VREFOUT-B

O(Analog)

None

28

29

Reference Voltage out drive (intended for mic

bias)

VREFOUT-C

O (Analog)

I/O (Analog)

O(Analog)

DMIC1 / GPIO6

VREFOUT-E / GPIO2

Digital Mic 23 Input/GPIO6

60K Pull-down 30

Reference Voltage out drive (intended for mic

bias) or General Purpose I/O

None

31

SENSE_C

CAP 2

Jack insertion detection

I(Analog)

O(Analog)

I(Analog)

None

32

33

34

ADC reference bypass capacitor

Jack insertion detection

SENSE_B

Table 31. 48QFP Pin Table

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Eight channel HD Audio codec optimized for low power

Internal Pull-up 48 pin

Pin Name

PORTD_L (HP)

Pin Function

I/O

Pull-down

location

Port D Output Left

Port D Output Right

I/O(Analog)

None

35

36

PORTD_R (HP)

None

Reference Voltage out drive (intended for mic

bias) or General Purpose I/O

VREFOUT-A / GPIO1

O(Analog)

None

37

AVDD2

Analog Supply for VREG

Port A Output Left

I(Power)

None

38

39

PORTA_L (HP)

I/O(Analog)

I/O(AVDD

supply)

SPDIFOUT1/ GPIO5

SPDIF Output, or General Purpose I/O

60K Pull-down

40

PORTA_R (HP)

AVSS

Port A Output Right

Analog Ground

Port G Left

I/O(Analog)

I(Power)

None

41

42

43

44

45

46

PORTG_L

PORTG_R

PORTH_L

PORTH_R

I/O(Analog)

Port G Right

Port H Left

Port H Right

EAPD/SPDIF_IN/GPIO0/SPDIF_OUT

1

60K

Pull-Up/Down

EAPD, SPDIF input, SPDIF output 1, GPIO0

I/O(Digital)

O(Digital)

47

48

SPDIFOUT0

SPDIF 0utput

60K pull-down

Table 31. 48QFP Pin Table

8.1.3.

48QFP Package Outline and Package Dimensions

Package dimensions are kept current with JEDEC Publication No. 95

A2

QFP Dimensions in mm

Key

Min

1.40

0.05

1.35

8.80

6.90

8.80

6.90

0.45

Nom

1.50

0.10

1.40

9.00

7.00

9.00

7.00

0.60

0.50

-

Max

D

A

A1

A2

D

1.60

0.15

1.45

9.20

7.10

9.20

7.10

0.75

A1

D1

b

D1

E

48 pin LQFP

E1

L

e

c

0.09

0.17

0.20

0.27

Pin 1

b

0.22

c

Figure 15. 48QFP Package Diagram

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Eight channel HD Audio codec optimized for low power

8.2.

40QFN

8.2.1.

40QFN Pin Assignment

SPDIF OUT0

DVDD_LV

SDATA_OUT

BITCLK

1

30

29

28

27

26

25

24

23

22

21

PORTD_R

PORTD_L

SENSE_B

Cap 2

2

3

4

SDATA_IN

DVDD*

5

VrefOut-E/GPIO2

VrefOut-B

VrefFilt

40-QFN

6

SYNC

7

RESET#

8

AVSS1

PCBeep

9

AVDD1

SENSE_A

10

PORTC_R

Figure 16. Pin Assignment

The DAP pad must be connected to DVSS on the 40-pin package.

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Eight channel HD Audio codec optimized for low power

8.2.2.

40QFN Pin Table)

Internal Pull-up 40 pin

Pin Name

Pin Function

I/O

Pull-down

60K pull-down

None

location

SPDIFOUT0

DVDD_LV

SPDIF 0utput

1.5V Digital Core Regulator Filter Cap

O(Digital)

O(Power)

1

2

SDATA_OUT

BITCLK

HD Audio Serial Data output from controller I(Digital)

None

3

HD Audio Bit Clock

HD Audio Serial Data Input to controller

Digital Vdd= 3.3V

HD Audio Frame Sync

HD Audio Reset

PC Beep input

I(Digital)

None

4

SDATA_IN

DVDD

I/O(Digital)

I(Power)

None

5

None

6

SYNC

I(Digital)

None

7

RESET#

I(Digital)

None

8

PCBeep

I(Analog)

I/O(Analog)

I(Analog)

I/O(Analog)

I(Analog)

O(Analog)

None

9

SENSE_A

PORTE_L

PORTE_R

PORTF_L

PORTF_R

CD Left

Jack insertion detection

Port E Left

None

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

None

Port E Right

None

Port F Left

None

Port F Right

None

CD Left

None

CD Common

CD Right

PORTB_L (HP)

PORTB_R (HP)

PORTC_L

PORTC_R

AVDD1

CD L/R return

None

CD Right

None

Port B Output Left

Port B Output Right

Port C Left

None

Port C Right

None

Analog Vdd=5.0V or 3.3V

Analog Ground

None

AVSS1

None

VREFFILT

Analog Virtual Ground

None

Reference Voltage out drive (intended for mic

bias)

VREFOUT-B

O(Analog)

None

25

26

Reference Voltage out drive (intended for mic

bias) or General Purpose I/O

VREFOUT-E / GPIO2

None

CAP 2

ADC reference bypass capacitor

Jack insertion detection

Port D Output Left

O(Analog)

I(Analog)

None

27

28

29

30

SENSE_B

PORTD_L (HP)

PORTD_R (HP)

I/O(Analog)

Port D Output Right

Reference Voltage out drive (intended for mic

bias) or General Purpose I/O

VREFOUT-A / GPIO1

O(Analog)

None

31

AVDD2

Analog Supply for VREG

Port A Output Left

I(Power)

None

32

33

34

PORTA_L (HP)

PORTA_R (HP)

I/O(Analog)

Port A Output Right

Table 32. 40QFN Pin Table

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Eight channel HD Audio codec optimized for low power

Internal Pull-up 40 pin

Pin Name

Pin Function

I/O

Pull-down

location

AVSS

Analog Ground

Port G Left

I(Power)

None

35

36

37

38

39

PORTG_L

PORTG_R

PORTH_L

PORTH_R

I/O(Analog)

None

Port G Right

Port H Left

Port H Right

60K

Pull-Up/Down

EAPD/SPDIF_IN/GPIO0/SPDIF_OUT1

EAPD, SPDIF input, SPDIF output 1, GPIO0 I/O(Digital)

40

The DAP pad must be connected to DVSS on the 40-pin package

Table 32. 40QFN Pin Table

8.2.3.

40QFN Package Outline and Package Dimensions

Package dimensions are kept current with JEDEC Publication No. 95

Figure 17. 40QFN Package Diagram

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Eight channel HD Audio codec optimized for low power

8.3. 48QFP and 40QFN Standard Reflow Profile Data

Note: These devices can be hand soldered at 360 ^oC for 3 to 5 seconds.

FROM: IPC / JEDEC J-STD-020C “Moisture/Reflow Sensitivity Classification for Nonhermetic Solid

State Surface Mount Devices” (www.jedec.org/download).

Profile Feature

Pb Free Assembly

Average Ramp-Up Rate (Ts_max- Tp)

3 ^oC / second max

Temperature Min (Ts_min

Temperature Max (Ts_max

Time (ts_min- ts_max

)

150 ^oC

Preheat:

200 ^oC

60 - 180 seconds

Temperature (T_L)

Time (t_L)

217 ^oC

60 - 150 seconds

Time maintained above:

Peak / Classification Temperature (Tp)

Time within 5 ^oC of actual Peak Temperature (tp)

Ramp-Down rate

See “Package Classification Reflow Temperatures”

20 - 40 seconds

6 ^oC / second max

Time 25 ^oC to Peak Temperature

8 minutes max

Note: All temperatures refer to topside of the package, measured on the package body surface.

Table 33. Standard Reflow Profile

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Eight channel HD Audio codec optimized for low power

9. DISCLAIMER

While the information presented herein has been checked for both accuracy and reliability, manufac-

turer assumes no responsibility for either its use or for the infringement of any patents or other rights

of third parties, which would result from its use. No other circuits, patents, or licenses are implied.

This product is intended for use in normal commercial applications. Any other applications, such as

those requiring extended temperature range, high reliability, or other extraordinary environmental

requirements, are not recommended without additional processing by manufacturer. Manufacturer

reserves the right to change any circuitry or specifications without notice. Manufacturer does not

authorize or warrant any product for use in life support devices or critical medical instruments.

363

V1.1 06/11

92HD89D

Eight channel HD Audio codec optimized for low power

10.DOCUMENT REVISION HISTORY

Revision

0.5

Date

Description of Change

May 2009

July 2009

April 2010

Initial release

0.9

added widget details

1.0

updated electricals with typicals based on validation

Corrected 40QFN functional block diagrams to remove DMIC0/1 as inputs to the ADC MUX0/1. The

40QFN package option does not support digital mics.

2.0

June 2011

364

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92HD89D

Eight channel HD Audio codec optimized for low power

6024 Silver Creek Valley Road

San Jose, California 95138

DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications de-

scribed herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and perfor-

mance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined

in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained

herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s

products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This

document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.

IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be

reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own

risk, absent an express, written agreement by IDT.

Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, in-

cluding protected names, logos and designs, are the property of IDT or their respective third party owners.


型号：	92HD89D1X5NDGXYYX8
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	Consumer Circuit, CMOS, ROHS COMPLIANT, QFN-40
文件：	总365页 (文件大小：4044K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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