93776AFLFT [IDT]
Clock Driver, PDSO28;
| 型号： | 93776AFLFT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Driver, PDSO28 光电二极管 |
| 文件： | 总8页 (文件大小：82K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS93776
Integrated
Circuit
Systems,Inc.
LowCostDDRPhaseLockLoopZeroDelayBuffer
Recommended Application:
DDR Zero Delay Clock Buffer
PinConfiguration
DDRC0
DDRT0
VDD
DDRT1
DDRC1
GND
SCLK
CLK_INT
CLK_INC
1
2
3
4
5
6
7
8
9
28 GND
27 DDRC5
26 DDRT5
25 DDRC4
24 DDRT4
23 VDD
22 SDATA
21 FB_INC
20 FB_INT
19 FB_OUTT
18 FB_OUTC
17 DDRT3
16 DDRC3
15 GND
ProductDescription/Features:
•
•
•
•
Low skew, low jitter PLL clock driver
Max frequency supported = 266MHz (DDR 533)
I2C for functional and output control
Feedback pins for input to output synchronization
•
•
Spread Spectrum tolerant inputs
3.3V tolerant CLK_INT/C input
VDDA 10
GND 11
VDD 12
DDRT2 13
DDRC2 14
Switching Characteristics:
•
•
•
CYCLE - CYCLE jitter: <100ps
OUTPUT - OUTPUT skew: <100ps
DUTY CYCLE: 48% - 52%
28-Pin 209mil SSOP
BlockDiagram
Functionality
INPUTS
OUTPUTS
PLL State
AVDD CLK_INT CLKT CLKC FB_OUTT
FB_OUTT
FB_OUTC
2.5V
L
L
H
L
L
on
on
Coonnttrrooll
SCLK
(nom)
DDRT0
DDRC0
Looggiicc
SDATA
2.5V
(nom)
H
H
H
DDRT1
DDRC1
DDRT2
DDRC2
FB_INC
FB_INT
DDRT3
DDRC3
PLLLL
DDRT4
DDRC4
CLK_INT
CLK_INC
DDRT5
DDRC5
0793A—03/08/05
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.
ICS93776
PinDescriptions
PIN # PIN NAME
PIN TYPE DESCRIPTION
1
2
3
4
5
6
7
8
DDRC0
DDRT0
VDD
DDRT1
DDRC1
GND
OUT
OUT
PWR
OUT
OUT
PWR
IN
"Complementary" Clock of differential pair output.
"True" Clock of differential pair output.
Power supply, nominal 2.5V
"True" Clock of differential pair output.
"Complementary" Clock of differential pair output.
Ground pin.
Clock pin of SMBus circuitry, 5V tolerant.
"True" reference clock input.
SCLK
CLK_INT
CLK_INC
VDDA
GND
IN
IN
9
"Complementary" reference clock input.
2.5V power for the PLL core.
Ground pin.
10
11
12
13
14
15
16
17
PWR
PWR
PWR
OUT
OUT
PWR
OUT
OUT
VDD
Power supply, nominal 2.5V
DDRT2
DDRC2
GND
DDRC3
DDRT3
"True" Clock of differential pair output.
"Complementary" Clock of differential pair output.
Ground pin.
"Complementary" Clock of differential pair output.
"True" Clock of differential pair output.
Complement single-ended feedback output, dedicated
external feedback. It switches at the same frequency
as other DDR outputs, This output must be connect to
FB_INC.
18
19
FB_OUTC
FB_OUTT
OUT
OUT
True single-ended feedback output, dedicated external
feedback. It switches at the same frequency as other
DDR outputs, This output must be connect to FB_INT.
True single-ended feedback input, provides feedback
signal to internal PLL for synchronization with
CLK_INT to eliminate phase error.
Complement single-ended feedback input, provides
feedback signal to internal PLL for synchronization
with CLK_INT to eliminate phase error.
Data pin for SMBus circuitry, 5V tolerant.
Power supply, nominal 2.5V
"True" Clock of differential pair output.
"Complementary" Clock of differential pair output.
"True" Clock of differential pair output.
"Complementary" Clock of differential pair output.
Ground pin.
20
21
FB_INT
FB_INC
IN
IN
22
23
24
25
26
27
28
SDATA
VDD
I/O
PWR
OUT
OUT
OUT
OUT
PWR
DDRT4
DDRC4
DDRT5
DDRC5
GND
0793A—03/08/05
2
ICS93776
AbsoluteMaximumRatings
Supply Voltage (VDD & AVDD) . . . . . . . . . . -0.5V to 3.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature. . . . . . . . . 0°C to +85°C
Storage Temperature. . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above
those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
Electrical Characteristics - Input / Supply / Common Output parameters
TA = 0 - 70°C; Supply Voltage AVDD, VDD = 2.50V 0.20V (unless otherwise stated)
PARAMETER
Operating Supply Current
Output High Current
SYMBOL
CONDITIONS
RT = 120W, CL = 12 pF at 100MHz
RT = 120W, CL = 12 pF at 133MHz
CL=0 pF
MIN
TYP MAX UNITS
300
mA
300
IDD2.5
IDDPD
IOH
100
-29
37
mA
mA
VDD = 2.5V, VOUT = 1V
-48
29
Output Low Current
High Impedance
Ouptut Current
mA
mA
V
IOL
VDD = 2.5V, VOUT = 1.2V
IOZ
VDD = 2.7V, VOUT = VDD or GND
10
VDD = min to max, IOH = -1mA
2
High-level Output Voltage
VOH
V
DD = 2.3V, IOH = -12mA
VDD = min to max, IOH = 1mA
DD = 2.3V, IOH = 12mA
VI = VDD or GND
V
0.1
0.4
Low-level Output Voltage
Output Capacitance1
VOL
V
pF
COUT
1. Guaranteed by design, not 100% tested in production.
Recommended Operation Conditions
TA = 0 - 70°C; Supply Voltage AVDD, VDD = 2.50V 0.20V (unless otherwise stated)
PARAMETER
Analog / Core Supply Voltage
Input Voltage Level
SYMBOL
AVDD
CONDITIONS
MIN
2.3
2
TYP MAX UNITS
2.7
3
V
V
VIN
0793A—03/08/05
3
ICS93776
Timing Requirements
TA = 0 - 70°C; Supply Voltage AVDD, VDD = 2.50V (unless otherwise stated)
PARAMETER
Operating Clock Frequency1
Input Clock Duty Cycle1
Clock Stabilization1
SYMBOL
freqop
dtin
CONDITIONS
Input Voltage level: 0-2.50V
MIN
22
40
TYP
MAX UNITS
340
60
MHz
%
50
tSTAB
from VDD = 2.5V to 1% target frequency
100
µs
1. Guaranteed by design, not 100% tested in production.
Switching Characteristics
TA = 0 - 70°C; Supply Voltage AVDD, VDD = 2.50V 0.20V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
Cycle to cycle Jitter1,2
tc-c
ps
66 MHz to 266 MHz
100
Phase Error1
tpe
Tskew
DC
-150
48
150
100
52
ps
ps
%
Output to output Skew1
Duty Cycle (Sign Ended)1,3
66 MHz to 267 MHz
Load=120Ω/14pF
Rise Time, Fall Time4
Output Differential Pair
Crossing Voltage
tR , tf
950
ps
VOC
VDD=2.50V
1.23
1.32
V
1. Guaranteed by design, not 100% tested in production.
2. Refers to transistion on non-inverting period.
3. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies.
This is due to the formular: duty_cycle=twH/tC, where the cycle time (tC)decreases as the frequency increases.
0793A—03/08/05
4
ICS93776
General SMBus serial interface information
How to Read:
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D4 (H)
• ICS clock will acknowledge
• Controller (host) will send start bit.
• Controller (host) sends the write address D4 (H)
• ICS clock will acknowledge
• Controller (host) sends the begining byte location = N
• ICS clock will acknowledge
• Controller (host) sends the begining byte
location = N
• Controller (host) sends the data byte count = X
• ICS clock will acknowledge
• Controller (host) starts sending Byte N through
Byte N + X -1
• ICS clock will acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address D5(H)
• ICS clock will acknowledge
(see Note 2)
• ICS clock will send the data byte count = X
• ICS clock sends Byte N + X -1
• ICS clock will acknowledge each byte one at a time
• ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
• Controller (host) sends a Stop bit
• Controller (host) will need to acknowledge each byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Read Operation
Index Block Write Operation
Controller (Host)
ICS (Slave/Receiver)
Controller (Host)
ICS (Slave/Receiver)
starT bit
T
starT bit
T
Slave Address D4(H)
Slave Address D4(H)
WR
WRite
WR
WRite
ACK
ACK
ACK
ACK
ACK
ACK
Beginning Byte = N
Beginning Byte = N
Data Byte Count = X
Beginning Byte N
RT
Repeat starT
Slave Address D5(H)
RD
ReaD
ACK
Data Byte Count = X
Beginning Byte N
ACK
ACK
Byte N + X - 1
ACK
P
stoP bit
Byte N + X - 1
N
P
Not acknowledge
stoP bit
0793A—03/08/05
5
ICS93776
Bytes 2 to 6 are reseved power up default = 1. This allows operation with main clock.
BYTE
0
Affected Pin
Name
Bit Control
Control Function
Type
Pin #
2, 1
4, 5
-
0
1
PWD
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DDR0(T&C)
DDR1(T&C)
Output Control
Output Control
Reserved
RW DISABLE ENABLE
RW DISABLE ENABLE
1
1
1
1
1
1
1
1
-
-
X
X
-
-
-
-
-
Reserved
13, 14
26, 27
-
DDR2(T&C)
DDR5(T&C)
-
Output Control
Output Control
Reserved
RW DISABLE ENABLE
RW DISABLE ENABLE
X
-
-
24, 25
DDR4(T&C)
Output Control
RW DISABLE ENABLE
Note: PWD = Power Up Default
BYTE
1
Affected Pin
Name
Bit Control
Type
Control Function
Pin #
-
16,17
-
-
-
-
-
-
0
-
1
-
PWD
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
Reserved
Output Control
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
X
1
1
0
0
0
0
0
0
DDR3(T&C)
RW DISABLE ENABLE
-
-
-
-
-
-
X
X
RW
X
RW
X
-
-
-
-
-
-
-
-
-
-
-
-
Note: PWD = Power Up Default
0793A—03/08/05
6
ICS93776
c
N
In Millimeters
In Inches
SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS
MIN
--
0.05
1.65
0.22
0.09
MAX
2.00
--
1.85
0.38
0.25
MIN
--
.002
.065
.009
.0035
MAX
.079
--
.073
.015
.010
L
A
A1
A2
b
E1
E
INDEX
AREA
c
D
E
E1
e
SEE VARIATIONS
SEE VARIATIONS
7.40
5.00
8.20
5.60
.291
.197
.323
.220
1
22
0.65 BASIC
0.0256 BASIC
α
L
0.55
0.95
.022
.037
D
A
N
α
SEE VARIATIONS
SEE VARIATIONS
A2
0°
8°
0°
8°
A1
VARIATIONS
- CC --
D mm.
D (inch)
N
e
SEATING
PLANE
MIN
9.90
MAX
10.50
MIN
.390
MAX
b
28
.413
Reference Doc.: JEDEC Publication 95, MO-150
.10 (.004) C
10-0033
209 mil SSOP
Ordering Information
ICS93776yFLF-T
Example:
ICS XXXX y F LF- T
Designation for tape and reel packaging
Annealed Lead Free (Optional)
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
0793A—03/08/05
7
ICS93776
Revision History
Rev.
N/A
N/A
Issue Date Description
Page #
8/12/2004 Updated I2c
8/20/2004 Updated I2c
6
6
0793A—03/08/05
8
相关型号：
93776AFT
PLL Based Clock Driver, 93776 Series, 6 True Output(s), 0 Inverted Output(s), PDSO28, 0.209 INCH, MO-150, SSOP-28
IDT
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