93857GT [IDT]
Clock Driver;
| 型号： | 93857GT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Driver |
| 文件： | 总5页 (文件大小：289K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS93857
Integrated
Circuit
Systems, Inc.
Preliminary Product Preview
DDR Phase Lock Loop Clock Driver
RecommendedApplication:
DDR Memory Modules
Pin Configuration
GND
CLKC0
CLKT0
VDD
CLKT1
CLKC1
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
GND
ProductDescription/Features:
CLKC5
CLKT5
VDD
CLKT6
CLKC6
GND
Low skew, low jitter PLLclock driver
1 to 10 differential clock distribution
Feedback pins for input to output synchronization
Active high OE to enable outputs
GND
GND
CLKC2
CLKT2
VDD
CLKC7
CLKT7
VDD
Spread Spectrum tolerant inputs
VDD
OE
CLK_INT
CLK_INC
VDD
AVDD
AGND
GND
CLKC3
CLKT3
VDD
CLKT4
CLKC4
GND
FB_INT
FB_INC
VDD
FB_OUTC
FB_OUTT
GND
CLKC8
CLKT8
VDD
CLKT9
CLKC9
GND
Specifications:
Input/Output Level
Inputs and outputs are compatible to JEDEC SSTL-2
standard.
Switching Characteristics:
PEAK-PEAKjitter(66MHz):<120ps
PEAK-PEAKjitter(>100MHz):<75ps
CYCLE-CYCLEjitter(66MHz):<120ps
CYCLE-CYCLEjitter(>100MHz):<65ps
OUTPUT-OUTPUTskew:<100ps
Output Rise and Fall Time: 650ps - 950ps
DUTYCYCLE:49.5%-50.5%
48-Pin TSSOP
Block Diagram
FB_OUTT
FB_OUTC
CLKT0
CLKC0
Functionality
CLKT1
CLKC1
INPUTS
OUTPUTS
PLL State
AVDD OE
CLK_INT CLK_INC CLKT CLKC FB_OUTT FB_OUTC
Control
Logic
CLKT2
CLKC2
OE
GND
GND
H
H
L
H
L
L
H
L
L
H
L
Bypassed/off
Bypassed/off
H
H
H
CLKT3
CLKC3
2.5V
(nom)
L
L
L
H
L
H
L
H
L
Z
Z
L
H
Z
Z
Z
H
L
Z
Z
Z
L
H
Z
Z
Z
H
L
Z
off
off
on
on
off
CLKT4
CLKC4
2.5V
(nom)
FB_INT
FB_INC
CLKT5
CLKC5
2.5V
(nom)
PLL
H
H
X
CLK_INC
CLK_INT
CLKT6
CLKC6
2.5V
(nom)
H
CLKT7
CLKC7
2.5V
(nom)
<20MHz)(1)
CLKT8
CLKC8
CLKT9
CLKC9
PRODUCT PREVIEW documents contain information on new
93857 Rev C 11/03/00
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.
ICS93857
Preliminary Product Preview
Pin Descriptions
PIN NUMBER
PIN NAME
VDD
TYPE
DESCRIPTION
4, 11, 12, 15, 21, 28,
34, 38, 45,
PWR
Power supply 2.5V
Ground
1, 7, 8, 18, 24, 25,
31, 41, 42, 48
GND
PWR
16
17
AVDD
AGND
PWR
PWR
Analog power supply, 2.5V
Analog ground.
27, 29, 39, 44, 46,
22, 20, 10, 5, 3
CLKT(9:0)
CLKC(9:0)
OUT
OUT
"True" Clock of differential pair outputs.
26, 30, 40, 43, 47,
23, 19, 9, 6, 2
"Complementory" clocks of differential pair outputs.
14
13
CLK_INC
CLK_INT
IN
IN
"Complementory" reference clock input
"True" reference clock input
"Complementory" Feedback output, dedicated for external feedback. It
switches at the same frequency as the CLK. This output must be wired to
FB_INC.
33
FB_OUTC
OUT
"True" " Feedback output, dedicated for external feedback. It switches at the
same frequency as the CLK. This output must be wired to FB_INT.
32
36
FB_OUTT
FB_INT
OUT
IN
"True" Feedback input, provides feedback signal to the internal PLL for
synchronization with CLK_INT to eliminate phase error.
"Complementory" Feedback input, provides signal to the internal PLL for
synchronization with CLK_INC to eliminate phase error.
35
37
FB_INC
OE
IN
IN
Active High output enable pin
2
ICS93857
Preliminary Product Preview
Absolute Maximum Ratings
SupplyVoltage (VDD &AVDD) . . . . . . . . . . . . . -0.5Vto4.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 85C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
SYMBOL
IIH
MIN
TYP
MAX
±10
UNITS
µA
PARAMETER
Input Current
CONDITIONS
VI = VDD or GND
IIL
Input Low Current
VI = VDD or GND
CL = 0pf
±10
µA
mA
µA
IDD2.5
IDDPD
IOH
250
50
Operating Supply Current
100
±10
CL = 0pf
VDD = 2.3V, VOUT = 1V
Output High Current
Output Low Current
-18
26
-32
mA
mA
IOL
IOZ
VDD = 2.3V, VOUT = 1.2V
30
High Impedance
Output Current
VDD=2.7V, Vout=VDD or GND
µA
VDD = min to max,
IOH = -1 mA
VDD = 2.3V,
IOH = -12 mA
VDD = min to max
IOL=1 mA
VDD = 2.3V
IOH=12 mA
VI = GND or VDD
VDD -0.1
1.7
V
VOH
High-level output voltage
V
0.1
VOL
Low-level output voltage
0.6
9
V
pF
V
Input Capacitance1
Output differential-pair
crossing voltage
CIN
VOC
(VDD/2) -0.2 VDD/2 (VDD/2) +0.2
1Guaranteed by design, not 100% tested in production.
Recommended Operating Condition
TA = 0 - 85C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
2.5
MAX
2.7
UNITS
V
AVDD
Analog/core supply voltage
2.3
Input High Voltage
Input Low Voltage
Input voltage level
VIH
VIL
VIN
OE input
OE input
0.7 x VDD
V
V
V
0.3 x VDD
VDD +0.3
-0.3
1Guaranteed by design, not 100% tested in production.
3
ICS93857
Preliminary Product Preview
Timing Requirem ents
TA = 0 - 85C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
CONDITIONS
PARAMETER
Operating clock frequency
Input clock duty cycle
SYMBOL
freqop
MIN
66
MAX
170
60
UNITS
MHz
%
dtin
40
from VDD = 3.3V to 1%
target freq.
CLK stabilization
TSTAB
100
µs
Switching Characteristics
PARAMETER
SYMBOL
CONDITION
MIN
1.5
TYP
3.5
MAX UNITS
Low-to high level propagation
delay time, bypass mode
1
CLK_IN to any output
6
6
ns
tPLH
High-to low level propagation
delay time
1
CLK_IN to any output
1.5
3.5
ns
tPLL
tEN
Output enable time
Output disable time
Jitter; peak to peak jitter
Cycle to Cycle Jitter1
Phase error, static
OE to any output
OE to any output
100/125/133/167MHz
100/125/133/167MHz
3
3
ns
ns
ps
ps
ps
ps
%
ps
tdis
Tjitter
75
75
Tcyc-Tcyc
t(phase error)
Tskew
-150
49
150
100
51
Output to Output Skew
Duty cycle
Rise Time, Fall Time
2
100MHz to 167MHz
DC
tr, tf
800
950
Load = 120Ω/16pF
Notes:
1. Refers to transition on noninverting output in PLL bypass mode.
4
ICS93857
Preliminary Product Preview
SYMBOL
In Millimeters
In Inches
COMMON DIMENSIONS
COMMON DIMENSIONS
MIN
-
MAX
1.20
0.15
1.05
0.27
0.20
MIN
-
MAX
.047
.006
.041
.011
.008
A
A1
A2
b
0.05
0.80
0.17
0.09
.002
.032
.007
.0035
c
SEE VARIATIONS
8.10 BASIC
SEE VARIATIONS
0.319
D
E
E1
e
6.00
6.20
0.50 BASIC
0.75
.236
.244
0.020 BASIC
L
0.45
.018
.30
SEE VARIATIONS
SEE VARIATIONS
N
0°
-
8°
0°
-
8°
α
aaa
0.10
.004
VARIATIONS
D mm.
D (inch)
N
MIN
MAX
MIN
.488
MAX
6.10 mm. Body, 0.50 mm. pitch TSSOP
(0.020 mil)
48
12.40
12.60
.496
7/6/00 Rev B
(240 mil)
MO-153 JEDEC
Doc.# 10-0039
Ordering Information
ICS93857yGT
Example:
ICS XXXX y G - PPP - T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
G=TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.
5
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