950211BFT [IDT]
Processor Specific Clock Generator, 205MHz, PDSO56, 0.300 INCH, SSOP-56;
| 型号： | 950211BFT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Processor Specific Clock Generator, 205MHz, PDSO56, 0.300 INCH, SSOP-56 光电二极管 |
| 文件： | 总21页 (文件大小：323K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems, Inc.
ICS950211
Preliminary Product Preview
Programmable Timing Control Hub for P4
Pin Configuration
Recommended Application:
CK-408 clock with driven mode only for Brookdale chipset with P4
processor.
VDDREF
X1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
REF1
FS1
FS0
X2
GND
Output Features:
CPU_STOP#*
CPUCLKT0
CPUCLKC0
VDDCPU
CPUCLKT1
CPUCLKC1
GND
VDDCPU
CPUCLKT2
CPUCLKC2
MULTSEL0*
I REF
GND
FS2
48MHz_USB/FS3**
48MHz_DOT
VDD48
1PCICLK_F0
1PCICLK_F1
PCICLK_F2
VDDPCI
GND
•
•
•
•
•
•
3 - Pairs of differential CPU clocks (differential current mode)
5 - 3V66 @ 3.3V
10 - PCI @ 3.3V
2 - 48MHz @ 3.3V fixed
1 - REF @ 3.3V, 14.318MHz
1*WDEN/PCICLK0
PCICLK1
PCICLK2
PCICLK3
VDDPCI
GND
1 - VCH/3V66 @ 3.3V, 48 MHz or 66.6 MHz
Features/Benefits:
PCICLK4
PCICLK5
PCICLK6
VDD3V66
GND
3V66_2
3V66_3
3V66_4
3V66_5
•
•
•
•
•
•
Programmable output frequency.
Programmable output divider ratios.
Programmable output rise/fall time.
GND
Programmable output skew.
3V66_1/VCH_CLK/FS4**
PCI_STOP#*
3V66_0
VDD3V66
GND
Programmable spread percentage for EMI control.
Watchdog timer technology to reset system
if system malfunctions.
*PD#
VDDA
GND
*Vtt_PWRGD#
SCLK
SDATA
•
•
•
Programmable watch dog safe frequency.
Support I2C Index read/write and block read/write operations.
Uses external 14.318MHz crystal.
56-Pin 300-mil SSOP
1. These outputs have 2X drive strength.
* Internal Pull-up resistor of 120K to VDD
Key Specifications:
•
•
•
CPU Output Jitter <150ps
3V66 Output Jitter <250ps
CPU Output Skew <100ps
** these inputs have 120K internal pull-down
to GND
Frequency Table
CPUCLK 3V66 PCICLK
FS4 FS3 FS2 FS1 FS0
MHz
MHz
MHz
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
66ꢀ66
100ꢀ00
200ꢀ00
133ꢀ33
100ꢀ90
105ꢀ00
109ꢀ00
114ꢀ00
117ꢀ00
127ꢀ00
130ꢀ00
132ꢀ50
205ꢀ00
170ꢀ00
180ꢀ00
190ꢀ00
66ꢀ66
66ꢀ66
66ꢀ66
66ꢀ66
67ꢀ27
70ꢀ00
72ꢀ67
76ꢀ00
78ꢀ00
72ꢀ86
74ꢀ29
75ꢀ71
70ꢀ00
56ꢀ67
60ꢀ00
63ꢀ33
33ꢀ33
33ꢀ33
33ꢀ33
33ꢀ33
33ꢀ63
35ꢀ00
36ꢀ33
38ꢀ00
39ꢀ00
36ꢀ43
37ꢀ14
37ꢀ89
35ꢀ00
28ꢀ33
30ꢀ00
31ꢀ67
Block Diagram
PLL2
48MHz_USB
48MHz_DOT
X1
X2
XTAL
OSC
3V66_0/VCH_CLK
REF
PLL1
Spread
Spectrum
CPUCLKT (2:0)
CPUCLKC (2:0)
CPU
DIVDER
3
Stop
Stop
3
PCI
DIVDER
PCICLK (6:0)
7
3
WDEN
PD#
CPU_STOP#
PCI_STOP#
MULTSEL0
FS (4:0)
SDATA
SCLK
Vtt_PWRGD#
PCICLK_F (2:0)
Control
Logic
3V66
3V66 (5:2, 0)
I REF
DIVDER
5
Config.
Reg.
For additional frequency selections please refer to Byte 0.
Power Groups
VDDA = Analog Core PLL
VDDREF = REF, Xtal
AVDD48 = 48MHz
950211 Rev
A 01/23/02
PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change
without notice.
Integrated
Circuit
Systems, Inc.
ICS950211
Preliminary Product Preview
General Description
The ICS950211 is a single chip clock solution for desktop designs using the Intel Brookdale chipset with PC133 or DDR
memory. It provides all necessary clock signals for such a system.
The ICS950211 is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). This part
incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a
serially programmable I2C interface, this device can adjust the output clocks by configuring the frequency setting, the output
divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each
individual output clock. M/N control can configure output frequency with resolution up to 0.1MHz increment.
Pin Description
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
1, 8, 14, 19,
37, 46, 50
VDD
PWR 3ꢀ3V power supplyꢀ
2
3
X1
X2
IN
Crystal input, has internal load cap (33pF) and feedback resistor from X2ꢀ
Crystal output, nominally 14ꢀ318MHzꢀ Has internal load cap (33pF)ꢀ
OUT
4, 9, 15, 20, 27, 31,
36, 41, 47
GND
PWR Ground pins for 3ꢀ3V supplyꢀ
24, 23, 22, 21, 33
3V66 (5:2, 0)
OUT
3ꢀ3V Fixed 66MHz clock outputs for HUBꢀ
PCICLK_F(2:0)
FS0
OUT
IN
3ꢀ3V PCI clock output
7,6,5
Logic input frequency select bitꢀ Input latched at power onꢀ
Hardware enable of watch dog circuitꢀ Enabled when latched highꢀ
WDEN
IN
10
PCICLK0
OUT
OUT
3ꢀ3V PCI clock outputꢀ
3ꢀ3V PCI clock outputsꢀ
18, 17, 16, 13, 12, 11 PCICLK (6:1)
Asynchronous active low input pin used to power down the device into a low
power stateꢀ The internal clocks are disabled and the VCO and the crystal are
stoppedꢀ The latency of the power down will not be greater than 3msꢀ
25
PD#
IN
26
28
VDDA
PWR Analog power 3ꢀ3Vꢀ
This 3ꢀ3V LVTTL input is a level sensitive strobe used to determine when FS (4:0)
inputs are valid and are ready to be sampled (active low)ꢀ
Clock pin for I2C circuitry 5V tolerantꢀ
Vtt_PWRGD#
IN
30
29
SCLK
IN
SDATA
I/O
Data pin for I2C circuitry 5V tolerantꢀ
Halts PCICLK clocks at logic 0 level, when input low except PCICLK_F which are
free runningꢀ
34
PCI_STOP#
IN
3ꢀ3V output selectable through I2C to be 66MHz from internal VCO or
48MHz (non-SSC)ꢀ
Logic input frequency select bitꢀ Input latched at power onꢀ
3V66_1/VCH_CLK
OUT
IN
35
FS4
AVDD48
48MHz_DOT
FS3
PWR Analog power 3ꢀ3Vꢀ
38
39
OUT
IN
3ꢀ3V Fixed 48MHz clock output for DOTꢀ
Logic input frequency select bitꢀ Input latched at power onꢀ
3ꢀ3V Fixed 48MHz clock output for USBꢀ
48MHz_USB
OUT
This pin establishes the reference current for the CPUCLK pairsꢀ This pin requires a
fixed precision resistor tied to ground in order to establish the appropriate currentꢀ
3ꢀ3V LVTTL input for selecting the current multiplier for CPU outputs
"Complementory" clocks of differential pair CPU outputsꢀ These are current outputs
and external resistors are required for voltage biasꢀ
42
43
I REF
OUT
IN
MULTSEL0
CPUCLKC (2:0)
44, 48, 51
OUT
"True" clocks of differential pair CPU outputsꢀ These are current outputs and external
resistors are required for voltage biasꢀ
Logic input frequency select bitꢀ Input latched at power onꢀ
Halts CPUCLK clocks at logic 0 level, when input low except CPUCLK_F which are
free runningꢀ
3ꢀ3V, 14ꢀ318MHz reference clock outputꢀ
45, 49, 52
40, 55, 54
53
CPUCLKT (2:0)
FS (2:0)
OUT
IN
CPU_STOP#
REF
IN
56
OUT
Third party brands and names are the property of their respective owners.
2
Integrated
Circuit
Systems, Inc.
ICS950211
Preliminary Product Preview
Maximum Allowed Current
Max 3.3V supply consumption
Max discrete cap loads,
Vdd = 3.465V
All static inputs = Vdd or GND
Condition
Powerdown Mode
(PWRDWN# = 0)
40mA
Full Active
360mA
Host Swing Select Functions
Reference R,
Iref =
VDD/(3*Rr)
Board Target
MULTISEL0
Output
Current
Voh @ Z
Trace/Term Z
Rr = 221 1%,
Iref = 5.00mA
0
1
50 ohms
50 ohms
Ioh = 4* I REF 1.0V @ 50
Ioh = 6* I REF 0.7V @ 50
Rr = 475 1%,
Iref = 2.32mA
Third party brands and names are the property of their respective owners.
3
Integrated
Circuit
Systems, Inc.
ICS950211
Preliminary Product Preview
General I2C serial interface information
How to Write:
How to Read:
Controller (host) sends a start bit.
• Controller (host) sends the write address D2(H)
• ICS clock will acknowledge
• Controller (host) will send start bit.
• Controller (host) sends the write address D2(H)
• ICS clock will acknowledge
• Controller (host) sends the begining byte location = N
• ICS clock will acknowledge
• Controller (host) sends the begining byte
location = N
• Controller (host) sends the data byte count = X
• ICS clock will acknowledge
• Controller (host) starts sending Byte N through
Byte N + X -1
• ICS clock will acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address D3(H)
• ICS clock will acknowledge
(see Note 2)
• ICS clock will send the data byte count = X
• ICS clock sends Byte N + X -1
• ICS clock will acknowledge each byte one at a time
• ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
• Controller (host) sends a Stop bit
• Controller (host) will need to acknowledge each byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Read Operation
Index Block Write Operation
Controller (Host)
ICS (Slave/Receiver)
Controller (Host)
ICS (Slave/Receiver)
T
starT bit
starT bit
T
Slave Address D2(H)
Slave Address D2(H)
WR
WRite
WR
WRite
ACK
ACK
ACK
ACK
ACK
ACK
Beginning Byte = N
Beginning Byte = N
Data Byte Count = X
Beginning Byte N
RT
Repeat starT
Slave Address D3(H)
RD
ReaD
ACK
Data Byte Count = X
Beginning Byte N
ACK
ACK
Byte N + X - 1
ACK
P
stoP bit
Byte N + X - 1
N
P
Not acknowledge
stoP bit
*See notes on the following pageꢀ
Third party brands and names are the property of their respective owners.
4
Integrated
Circuit
Systems, Inc.
ICS950211
Preliminary Product Preview
Byte 0: Functionality and frequency select register (Default=0)
Bit
PWD
Description
Bit2 Bit7 Bit6 Bit5 Bit4
FS4 FS3 FS2 FS1 FS0
CPUCLK 3V66 PCICLK
Spread %
MHz
MHz
MHz
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
66ꢀ66
100ꢀ00
200ꢀ00
133ꢀ33
100ꢀ90
105ꢀ00
109ꢀ00
114ꢀ00
117ꢀ00
127ꢀ00
130ꢀ00
132ꢀ50
205ꢀ00
170ꢀ00
180ꢀ00
190ꢀ00
133ꢀ90
133ꢀ33
120ꢀ00
125ꢀ00
134ꢀ90
137ꢀ00
139ꢀ00
141ꢀ00
143ꢀ00
145ꢀ00
150ꢀ00
155ꢀ00
160ꢀ00
150ꢀ00
160ꢀ00
170ꢀ00
66ꢀ66
66ꢀ66
66ꢀ66
66ꢀ66
67ꢀ27
70ꢀ00
72ꢀ67
76ꢀ00
78ꢀ00
72ꢀ86
74ꢀ29
75ꢀ71
70ꢀ00
56ꢀ67
60ꢀ00
63ꢀ33
66ꢀ95
66ꢀ67
60ꢀ00
62ꢀ50
67ꢀ45
68ꢀ50
69ꢀ50
70ꢀ50
71ꢀ50
72ꢀ50
75ꢀ00
77ꢀ50
80ꢀ00
64ꢀ29
68ꢀ57
72ꢀ86
33ꢀ33
33ꢀ33
33ꢀ33
33ꢀ33
33ꢀ63
35ꢀ00
36ꢀ33
38ꢀ00
39ꢀ00
36ꢀ43
37ꢀ14
37ꢀ89
35ꢀ00
28ꢀ33
30ꢀ00
31ꢀ67
33ꢀ48
33ꢀ33
30ꢀ00
31ꢀ25
33ꢀ73
34ꢀ25
34ꢀ75
35ꢀ25
35ꢀ75
36ꢀ25
37ꢀ50
38ꢀ75
40ꢀ00
32ꢀ14
34ꢀ29
36ꢀ43
0 to -0ꢀ5% down spread
0 to -0ꢀ5% down spread
0 to -0ꢀ5% down spread
0 to -0ꢀ5% down spread
+/-0ꢀ35% center spread
+/-0ꢀ35% center spread
+/-0ꢀ35% center spread
+/-0ꢀ35% center spread
+/-0ꢀ35% center spread
+/-0ꢀ35% center spread
+/-0ꢀ35% center spread
+/-0ꢀ35% center spread
+/-0ꢀ35% center spread
+/-0ꢀ35% center spread
+/-0ꢀ35% center spread
+/-0ꢀ35% center spread
+/-0ꢀ35% center spread
+/-0ꢀ35% center spread
+/-0ꢀ35% center spread
+/-0ꢀ35% center spread
+/-0ꢀ35% center spread
+/-0ꢀ35% center spread
+/-0ꢀ35% center spread
+/-0ꢀ35% center spread
+/-0ꢀ35% center spread
+/-0ꢀ35% center spread
+/-0ꢀ35% center spread
+/-0ꢀ35% center spread
+/-0ꢀ35% center spread
+/-0ꢀ35% center spread
+/-0ꢀ35% center spread
+/-0ꢀ35% center spread
Bit
(2,7:4)
Note 1
0 - Frequency is selected by hardware select, latched inputs
1 - Frequency is selected by Bit 2,7:4
0 - Normal
Bit 3
Bit 1
0
1
1 - Spread spectrum enable
0 - Watch dog safe frequency will be selected by latch inputs
1 - Watch dog safe frequency will be programmed by Byte 10 bit (4:0)
Bit 0
0
Notes:
1. Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
Third party brands and names are the property of their respective owners.
5
Integrated
Circuit
Systems, Inc.
ICS950211
Preliminary Product Preview
Byte 1: Output Control Register
(1 = enable, 0 = disable)
Bit
Pin#
PWD
Description
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
44, 45
48, 49
51, 52
1
1
1
X
X
X
X
X
CPUT/C2
CPUT/C1
CPUT/C0
FS4 Read back
FS3 Read back
FS2 Read back
FS1 Read back
FS0 Read back
-
-
-
-
-
Byte 2: Output Control Register
(1 = enable, 0 = disable)
Bit
Pin#
-
PWD
Description
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
X
1
1
1
1
1
1
1
MULTSEL (Read back)
PCICLK_6
PCICLK_5
PCICLK_4
PCICLK_3
PCICLK_2
PCICLK_1
PCICLK_0
18
17
16
13
12
11
10
Byte 3: Output Control Register
(1 = enable, 0 = disable)
Bit
Pin#
38
39
-
-
35
7
PWD
Description
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
1
1
1
X
0
1
1
1
48MHZ_DOT
48MHz_USB
Reset gear shift detect 1 = Enable, 0 = Disable
Reserved
3V66_1/VCH_CLK, (default) = 66ꢀ66MHz, 1=48MHz
PCICLK_F2
PCICLK_F1
PCICLK_F0
6
5
Byte 4: Output Control Register
(1 = enable, 0 = disable)
Bit
Pin#
PWD
Description
Asyncꢀ 3V66 control bit
Bit 7
-
1
0 : 3V66 / PCI = 64/32 MHz asynchronous with CPU
1 : 3V66 / PCI = 66ꢀ6/33ꢀ3 MHz synchronous with CPU
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
X
1
1
1
1
1
1
Reserved
3V66_0
3V66_1/VCH_CLK
3V66_5
3V66_4
3V66_3
33
35
24
23
22
21
3V66_2
Notes:
1. PWD = Power on Default
2. For disabled clocks, they stop low for single ended clocks. Differential CPU clocks stop with CPUCLKT at high,
CPUCLKC off, and external resistor termination will bring CPUCLKC low.
Third party brands and names are the property of their respective owners.
6
Integrated
Circuit
Systems, Inc.
ICS950211
Preliminary Product Preview
Byte 5: Programming Edge Rate
(1 = enable, 0 = disable)
Bit
Pin#
X
X
X
X
X
X
X
X
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
Byte 6: Vendor ID Register
(1 = enable, 0 = disable)
Bit
Name
PWD
X
X
X
X
0
0
0
1
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Revision ID Bit3
Revision ID Bit2
Revision ID Bit1
Revision ID Bit0
Vendor ID Bit3
Vendor ID Bit2
Vendor ID Bit1
Vendor ID Bit0
Revision ID values will be based on individual device's revision
(Reserved)
(Reserved)
(Reserved)
(Reserved
)
Byte 7: Revision ID and Device ID Register
Bit
Name
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Device ID7
Device ID6
Device ID5
Device ID4
Device ID3
Device ID2
Device ID1
Device ID0
0
0
1
0
0
0
1
0
Device ID values will be based on individual device
"22H" in this caseꢀ
Byte 8: Byte Count Read Back Register
Bit
Name
Byte7
Byte6
Byte5
Byte4
Byte3
Byte2
Byte1
Byte0
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
1
1
1
1
Note: Writing to this register will configure byte count and how
many bytes will be read back, default is 0FH = 15 bytes.
Third party brands and names are the property of their respective owners.
7
Integrated
Circuit
Systems, Inc.
ICS950211
Preliminary Product Preview
Byte 9: Watchdog Timer Count Register
Bit
Name
WD7
WD6
WD5
WD4
WD3
WD2
WD1
WD0
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
1
0
0
0
The decimal representation of these 8 bits correspond to X
290ms the watchdog timer will wait before it goes to alarm mode
and reset the frequency to the safe settingꢀ Default at power up is
8 290ms = 2ꢀ3 secondsꢀ
Byte 10: Programming Enable bit 8 Watchdog Control Register
Bit
Name
PWD
Description
Programming Enable bit
Program
Enable
Bit 7
0
0 = no programmingꢀ Frequencies are selected by HW latches or Byte0 1
= enable all I2C programingꢀ
Watchdog Enable bitꢀ
This bit will over write WDEN latched valueꢀ 0 = disable, 1 = Enableꢀ
Bit 6
WD Enable
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WD Alarm
SF4
0
0
1
0
0
0
Watchdog Alarm Status 0 = normal 1= alarm status
SF3
SF2
SF1
SF0
Watchdog safe frequency bitsꢀ Writing to these bits will configure the safe
frequency corrsponding to Byte 0 Bit 2, 7:4 table
Byte 11: VCO Frequency M Divider (Reference divider) Control Register
Bit
Name
Ndiv 8
Mdiv 6
Mdiv 5
Mdiv 4
Mdiv 3
Mdiv 2
Mdiv 1
Mdiv 0
PWD
X
X
X
X
X
X
X
X
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
N divider bit 8
The decimal respresentation of Mdiv (6:0) corresposd to the
reference divider valueꢀ Default at power up is equal to the
latched inputs selectionꢀ
Byte 12: VCO Frequency N Divider (VCO divider) Control Register
Bit
Name
Ndiv 7
Ndiv 6
Ndiv 5
Ndiv 4
Ndiv 3
Ndiv 2
Ndiv 1
Ndiv 0
PWD
X
X
X
X
X
X
X
X
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The decimal representation of Ndiv (8:0) correspond to the
VCO divider value. Default at power up is equal to the
latched inputs selecton. Notice Ndiv 8 is located in Byte 11.
Third party brands and names are the property of their respective owners.
8
Integrated
Circuit
Systems, Inc.
ICS950211
Preliminary Product Preview
Byte 13: Spread Spectrum Control Register
Bit
Name
SS 7
SS 6
SS 5
SS 4
SS 3
SS 2
SS 1
SS 0
PWD
X
X
X
X
X
X
X
X
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The Spread Spectrum (12:0) bit will program the spread
precentageꢀ Spread precent needs to be calculated based on the
VCO frequency, spreading profile, spreading amount and spread
frequencyꢀ It is recommended to use ICS software for spread
programmingꢀ Default power on is latched FS dividerꢀ
Byte 14: Spread Spectrum Control Register
Bit
Name
Reserved
Reserved
Reserved
SS 12
SS 11
SS 10
SS 9
SS 8
PWD
X
X
X
X
X
X
X
X
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
Spread Spectrum Bit 12
Spread Spectrum Bit 11
Spread Spectrum Bit 10
Spread Spectrum Bit 9
Spread Spectrum Bit 8
Byte 15: Output Divider Control Register
Bit
Name
PWD
X
X
X
X
X
X
X
X
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
Reserved
CPU Div 3
CPU Div 2
CPU Div 1
CPU Div 0
Reserved
CPU clock divider ratio can be configured via these 4
bits individually. For divider selection table refer to
Table 1. Default at power up is latched FS divider.
Byte 16: Output Divider Control Register
Bit
Name
PWD
X
X
X
X
X
X
X
X
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PCI Div 3
PCI Div 2
PCI Div 1
PCI Div 0
3V66 Div 3
3V66 Div 2
3V66 Div 1
3V66 Div 0
PCI clock divider ratio can be configured via these 4
bits individually. For divider selection table refer to
Table 2. Default at power up is latched FS divider.
3V66 clock divider ratio can be configured via these 4
bits individually. For divider selection table refer to
Table 1. Default at power up is latched FS divider.
Third party brands and names are the property of their respective owners.
9
Integrated
Circuit
Systems, Inc.
ICS950211
Preliminary Product Preview
Byte 17: Output Divider Control Register
Bit
Name
PCI_INV
PWD
X
X
X
X
X
X
X
X
Description
PCICLK Phase Inversion bit
3V66 Phase Inversion bit
Reserved
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
3V66_INV
Reserved
CPU_INV
Reserved
Reserved
Reserved
Reserved
CPUCLK Phase Inversion bit
Reserved
Table 1
Table 2
Div (3:2)
Div (3:2)
00
01
10
11
00
01
10
11
Div (1:0)
Div (1:0)
00
01
10
11
/2
/3
/5
/7
/4
/6
/8
/16
/24
/40
/56
00
01
10
11
/4
/3
/5
/9
/8
/6
/16
/12
/20
/36
/32
/24
/40
/72
/12
/20
/28
/10
/14
/10
/18
Byte 18: Group Skew Control Register
Bit
Name
PWD
Description
These 2 bits delay the CPUCLKC/T2 with respect to
CPUCLKC/T (1:0)
00 = 0ps 01 = 250ps 10 = 500ps 11 =750ps
Bit 7
CPU_Skew 1
0
Bit 6
CPU_Skew 0
1
Bit 5
Bit 4
Reserved
Reserved
0
0
Reserved
Reserved
These 2 bits delay the CPUCLKC/T (1:0) clock with respect to
CPUCLKC/T2
00 = 0ps 01 = 250ps 10 = 500ps 11 = 750ps
Bit 3
Bit 2
CPU_Skew 1
CPU_Skew 0
0
1
Bit 1
Bit 0
Reserved
Reserved
0
0
Reserved
Reserved
Byte 19: Group Skew Control Register
Bit
Name
PWD
Programming Sequence
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
1
1
1
1
1
0
0
1
1
1
0
1
0
1
1
0
0
0
0
0
0
0
0
0
1
0ps Reserved
150ps Reserved
300ps Reserved
450ps Reserved
600ps Reserved
These 4bits control
CPU-3V66(3:1)
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
1
0
1
750ps Reserved
900ps Reserved
Reserved
These 4 bits control
CPU-3V66_0
Reserved
Third party brands and names are the property of their respective owners.
10
Integrated
Circuit
Systems, Inc.
ICS950211
Preliminary Product Preview
Byte 20: Group Skew Control Register
Bit
Name
PWD
Programming Sequence
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
1
1
1
1
1
0
0
1
1
1
0
1
0
1
1
0
0
0
0
0
0
0
0
0
1
0ps Reserved
150ps Reserved
300ps Reserved
450ps Reserved
600ps Reserved
750ps Reserved
These 4bits control
CPU-PCI(6:0)
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
1
0
1
These 4 bits control
CPU-PCIF(1:0)
900ps Reserved
Reserved
Reserved
Byte 21: Slew Rate Control Register
Bit
Name
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
PCIF Slew 1
PCIF Slew 0
0
0
1
0
1
0
1
0
Reserved
Reserved
PCIF(1:0) clock slew rate control bitsꢀ
01 = strong: 11 = normal; 10 = weak
3V66 (3:1) clock slew rate control bitsꢀ
01 = strong: 11 = normal; 10 = weak
3V66_0 clock slew rate control bitsꢀ
01 = strong: 11 = normal; 10 = weak
3V66 (3:1)_Slew 1
3V66 (3:1)_Slew 1
3V66_0_Slew 1
3V66_0_Slew 0
Byte 22: Slew Rate Control Register
Bit
Name
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
REF Slew 1
REF Slew 0
1
0
1
0
1
0
1
0
REF clock slew rate control bitsꢀ
01 = strong: 11 = normal; 10 = weak
PCI (6:4) clock slew rate control bitsꢀ
01 = strong: 11 = normal; 10 = weak
PCI (6:4) Slew 1
PCI (6:4) Slew 0
PCI (3:1) Slew 1
PCI (3:1) Slew 0
PCI0 Slew 1
PCI (3:1) clock slew rate control bitsꢀ
01 = strong: 11 = normal; 10 = weak
PCI0 clock slew rate control bitsꢀ
01 = strong: 11 = normal; 10 = weak
PCI0 Slew 0
Byte 23: Slew Rate Control Register
Bit
Name
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
X
X
1
0
1
0
1
0
Reserved
VCH Slew 1
VCH Slew 0
48USB Slew 1
48USB Slew 0
48DOT Slew 1
48DOT Slew 0
VCH clock slew rate control bitsꢀ
01 = strong: 11 = normal; 10 = weakk
48USB clock slew rate control bitsꢀ
01 = strong: 11 = normal; 10 = weakk
48DOT clock slew rate control bitsꢀ
01 = strong: 11 = normal; 10 = weak
Third party brands and names are the property of their respective owners.
11
Integrated
Circuit
Systems, Inc.
ICS950211
Preliminary Product Preview
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . . . . . 0°C to +70°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +5%
PARAMETER
SYMBOL
CONDITIONS
MIN
2
TYP
MAX
VDD+0.3
0.8
UNITS
V
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
VIH
VIL
IIH
VSS-0.3
-5
V
VIN = VDD
5
m A
m A
m A
m A
m A
m A
m A
MHz
nH
IIL1
IIL2
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
CL = 0 pF; Select @ 66M
CL = Full load
-5
-200
100
360
25
Operating
IDD3.3OP
IDD3.3PD
Supply Current
Power Down
Supply Current
IREF=2.32
IREF= 5m A
45
Input frequency
Pin Inductance
Fi
Lpin
VDD = 3.3 V;
14.318
7
5
CIN
Logic Inputs
pF
Input Capacitance1
Cout
CINX
Ttrans
Ts
Out put pin capacitance
6
pF
X1 & X2 pins
27
36
45
3
pF
Transition Time1
Settling Time1
Clk Stabilization1
To 1st crossing of target Freq.
From 1st crossing to 1% target Freq.
From VDD = 3.3 V to 1% target Freq.
output enable delay (all outputs)
output disable delay (all outputs)
mS
mS
m S
nS
3
TSTAB
3
t
PZH,tPZH
1
1
10
10
Delay
t
PLZ,tPZH
nS
1Guarenteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
12
Integrated
Circuit
Systems, Inc.
ICS950211
Preliminary Product Preview
Electrical Characteristics - CPUCLK
TA = 0 - 70º C; VDD = 3.3 V +/-5%; (unless otherwise stated)
PARAMETER
Current Source
Output Impedance
Output High Voltage
SYMBOL
ZO
CONDITIONS
MIN
TYP
MAX UNITS
VO = VX
3000
Ω
VOH
IOH
tr
0.71
1.2
V
mA
ps
VR = 475W +1%; IREF = 2.32mA; IOH = 6*IREF
Output High Current
Rise Time1
Differential Crossover
Voltage1
Duty Cycle1
Skew1, CPU to CPU
Jitter, Cycle-to-cycle1
-13.92
VOL = 20%, VOH = 80%
Note 3
175
45
700
55
VX
50
51
%
dt
tsk
VT = 50%
VT = 50%
VT = VX
45
55
%
ps
ps
100
150
tjcyc-cyc
Notes:
1 - Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCICLK
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise stated)
PARAMETER
Output Frequency
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
F01
CONDITIONS
MIN
TYP
MAX UNITS
MHz
33.33
1
RDSN1
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
12
55
Ω
V
VOH1
VOL1
IOH1
IOL1
2.4
0.55
-33
38
V
VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V
VOL@ MIN = 1.95 V, VOL@ MAX= 0.4
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
-33
30
mA
mA
1
tr1
0.5
0.5
45
2
ns
ns
%
1
Fall Time
tf1
2
1
Duty Cycle
dt1
55
1
Skew
tsk1
VT = 1.5 V
500
250
ps
ps
1
tjcyc-cyc
VT = 1.5 V
Jitter
1Guarenteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
13
Integrated
Circuit
Systems, Inc.
ICS950211
Preliminary Product Preview
Electrical Characteristics - 3V66
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL =10-30 pF (unless otherwise stated)
PARAMETER
Output Frequency
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
FO1
CONDITIONS
MIN
TYP
MAX UNITS
MHz
66.66
1
RDSP1
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
12
55
Ω
V
VOH1
VOL1
IOH1
IOL1
2.4
0.4
-33
38
2
V
VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V
VOL@ MIN = 1.95 V, VOL@ MAX= 0.4
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
-33
30
mA
mA
1
tr1
0.5
0.5
45
ns
ns
%
1
Fall Time
tf1
2
1
Duty Cycle
dt1
55
500
250
1
Skew
tsk1
VT = 1.5 V
ps
ps
tjcyc-cyc1
VT = 1.5 V
Jitter
1Guarenteed by design, not 100% tested in production.
Electrical Characteristics - VCH, 48MHz DOT, 48MHz, USB
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise stated)
PARAMETER
Output Frequency
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
48DOT Rise Time
48DOT Fall Time
SYMBOL
CONDITIONS
MIN
TYP
48
MAX UNITS
MHz
1
FO
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -1 mA
1
RDSN1
12
55
Ω
V
VOH1
VOL1
IOH1
IOL1
2.4
IOL = 1 mA
0.55
-23
27
1
V
VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V
VOL@ MIN = 1.95 V, VOL@ MAX= 0.4
VOL = 0.4 V, VOH = 2.4 V
-29
29
mA
mA
ns
ns
1
tr1
0.5
0.5
1
tf1
VOH = 2.4 V, VOL = 0.4 V
1
VCH 48 USB
Rise Time
VCH 48 USB
Fall Time
tr1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT=1.5V
1
1
2
2
1
ns
ns
ns
tf1
48 DOT to 48 USB
Skew
tskew1
1
Duty Cycle
dt1
VT = 1.5 V
VT = 1.5 V
45
55
%
1
tjcyc-cyc
Jitter
350
ps
1Guarenteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
14
Integrated
Circuit
Systems, Inc.
ICS950211
Preliminary Product Preview
Electrical Characteristics - REF
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL =10-20 pF (unless otherwise stated)
PARAMETER
Output Frequency
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
FO1
CONDITIONS
MIN
TYP
MAX UNITS
MHz
1
RDSP1
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
20
60
Ω
V
VOH1
VOL1
IOH1
IOL1
2.4
0.4
-23
27
4
V
VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V
VOL@ MIN = 1.95 V, VOL@ MAX= 0.4
VOL = 0.4 V, VOH = 2.4 V
-29
29
1
mA
mA
ns
ns
%
1
tr1
1
Fall Time
tf1
VOH = 2.4 V, VOL = 0.4 V
1
4
1
Duty Cycle
dt1
VT = 1.5 V
VT = 1.5 V
45
55
500
tjcyc-cyc
Jitter
ps
1Guarenteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
15
Integrated
Circuit
Systems, Inc.
ICS950211
Preliminary Product Preview
Shared Pin Operation -
Input/Output Pins
a switch or 2 pin header is used. With no jumper is installed
the pin will be pulled high. With the jumper in place the pin
will be pulled low. If programmability is not necessary, than
only a single resistor is necessary. The programming
resistors should be located close to the series termination
resistor to minimize the current loop area. It is more important
to locate the series termination resistor close to the driver
than the programming resistor.
The I/O pins designated by (input/output) serve as dual
signal functions to the device. During initial power-up, they
act as input pins. The logic level (voltage) that is present on
these pins at this time is read and stored into a 5-bit internal
data latch. At the end of Power-On reset, (see AC
characteristics for timing values), the device changes the
mode of operations for these pins to an output function. In
this mode the pins produce the specified buffered clocks to
external loads.
To program (load) the internal configuration register for
these pins, a resistor is connected to either the VDD (logic 1)
power supply or the GND (logic 0) voltage potential. A 10
Kilohm (10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Figure 1 shows a means of implementing this function when
Via to
VDD
Programming
Header
2K W
Via to Gnd
Device
Pad
8.2K W
Clock trace to load
Series Term. Res.
Fig. 1
Third party brands and names are the property of their respective owners.
16
Integrated
Circuit
Systems, Inc.
ICS950211
Preliminary Product Preview
Un-Buffered Mode 3V66 & PCI Phase Relationship
All 3V66 clocks are to be in pphase with each other. In the case where 3V66_1 is configured as 48MHz VCH clock, there is no
defined phase relationship between 3V66_1/VCH and other 3V66 clocks. The PCI group should lag 3V66 by the standard
skew described below as Tpci.
3V66
Tpci
PCICLK_F and PCICLK
Group Skews at Common Transition Edges: (Un-Buffered Mode)
GROUP
SYMBOL
CONDITIONS
3V66 pin to pin skew
PCI_F and PCI pin to pin skew
MIN
TYP MAX UNITS
3V66
PCI
3V66
PCI
0
0
500
500
3.5
ps
ps
ns
3V66 to PCI
S3V66-PCI 3V66 leads 33MHz PCI
1.5
1Guarenteed by design, not 100% tested in production.
PD# Functionality
PCICLK_F
PCICLK
USB/DOT
48MHz
CPU_STOP#
CPUT
CPUC
3V66
66MHz_OUT
PCICLK
1
0
Normal
Normal
Float
66MHz
Low
66MHz_IN
Low
66MHz_IN 66MHz_IN
Low Low
48MHz
Low
iref * Mult
Third party brands and names are the property of their respective owners.
17
Integrated
Circuit
Systems, Inc.
ICS950211
Preliminary Product Preview
PCI_STOP# - Assertion (transition from logic "1" to logic "0")
The impact of asserting the PCI_STOP# signal will be the following. All PCI[6:0] and stoppable PCI_F[2,0] clocks will latch low
in their next high to low transition. The PCI_STOP# setup time tsu is 10 ns, for transitions to be recognized by the next rising
edge.
Assertion of PCI_STOP# Waveforms
PCI_STOP#
PCI_F[2:0] 33MHz
PCI[6:0] 33MHz
tsu
CPU_STOP# - Assertion (transition from logic "1" to logic "0")
The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I2C configuration to be stoppable via
assertion of CPU_STOP# are to be stopped after their next transition following the two CPU clock edge sampling as shown.
The final state of the stopped CPU signals is CPUT=High and CPUC=Low. There is to be no change to the output drive current
values. The CPUT will be driven high with a current value equal to (MULTSEL0) X (I REF), the CPUC signal will not be driven.
Assertion of CPU_STOP# Waveforms
CPU_STOP#
CPUT
CPUC
CPU_STOP# Functionality
CPU_STOP#
CPUT
CPUC
1
0
Normal
Normal
Float
iref * Mult
Third party brands and names are the property of their respective owners.
18
Integrated
Circuit
Systems, Inc.
ICS950211
Preliminary Product Preview
c
N
In Millimeters
In Inches
SYMBOL
COMMON DIMENSIONS COMMON DIMENSIONS
L
MIN
2.41
0.20
0.20
0.13
MAX
2.80
0.40
0.34
0.25
MIN
.095
.008
.008
.005
MAX
.110
.016
.0135
.010
A
A1
b
E1
E
INDEX
AREA
c
D
E
E1
e
SEE VARIATIONS
SEE VARIATIONS
1
2
10.03
7.40
10.68
7.60
.395
.291
.420
.299
hh xx 4455°°
D
0.635 BASIC
0.025 BASIC
h
L
0.38
0.50
0.64
1.02
.015
.020
.025
.040
A
N
α
SEE VARIATIONS
SEE VARIATIONS
0°
8°
0°
8°
A1
- CC --
VARIATIONS
D mm.
D (inch)
e
SEATING
PLANE
N
b
MIN
18.31
MAX
18.55
MIN
.720
MAX
.730
.10 (.004) C
56
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
300 mil SSOP Package
Ordering Information
ICS950211yFT
Example:
ICS XXXX y F - T
Designation for tape and reel packaging
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
Registered Company
9001
For more information on Integrated Circuit Systems Inc. or any of our products please visit our web site at:
http://www.icst.com
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950211 (Desktop Chipsets)
Description
Brookdale and Brookdale -G chipset with P4 processor.
Market Group
PC CLOCK
Additional Info
The ICS950211 is a single chip clock solution for desktop designs using the Intel Brookdale chipset with PC133 or DDR memory. It provides all
necessary clock signals for such a system. The ICS950211 is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing
Control Hub). This part incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a
serially programmable I2C interface, this device can adjust the output clocks by configuring the frequency setting, the output divider ratios,
selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each individual output clock. M/N control can
configure output frequency with resolution up to 0.1MHz increment. • 3 - Pairs of differential CPU clocks (differential current mode) • 5 - 3V66 @
3.3V • 10 - PCI @ 3.3V • 2 - 48MHz @ 3.3V fixed • 1 - REF @ 3.3V, 14.318MHz • 1 - VCH/3V66 @ 3.3V, 48 MHz or 66.6 MHz
Related Orderable Parts
Attributes
950211BF
950211BFLF
950211BFLFT
950211BFT
3.3 V (PV56)
3.3 V (PVG56)
3.3 V (PVG56)
3.3 V (PV56)
SSOP 56
NA
Voltage
Package
Speed
SSOP 56
NA
SSOP 56
NA
SSOP 56
NA
C
C
C
C
Temperature
Active
Yes
Active
Yes
Active
No
Active
No
Status
Sample
130
156
1000
1000
1000
Minimum Order Quantity
Factory Order Increment
26
26
1000
Related Documents
Type
Title
Size
Revision Date
Datasheet
Model - IBIS
950211 Datasheet
950211 IBIS Model
184 KB
220 KB
11/08/2006
03/24/2006
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