950508FT [IDT]
Clock Generator, PDSO56;
| 型号： | 950508FT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, PDSO56 光电二极管 |
| 文件： | 总19页 (文件大小：161K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
ICS950508
Systems, Inc.
Programmable Timing Control Hub™ for PII/III™
Recommended Application:
810/810E/815 and 815 B-Step type chipset
Pin Configuration
VDDREF
X1
X2
GND
GND
3V66_0
3V66_1
3V66_2
VDD3V66
VDDPCI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
REF0/FS41*
VDDLAPIC
IOAPIC
VDDLCPU
CPUCLK0
CPUCLK1
GND
Output Features:
•
•
•
•
•
•
•
2 - CPUs @ 2.5V
13 - SDRAM @ 3.3V
3 - 3V66 @ 3.3V
GND
8 - PCI @3.3V
SDRAM0
SDRAM1
SDRAM2
VDDSDR
SDRAM3
SDRAM4
SDRAM5
GND
SDRAM6
SDRAM7
SDRAM_F
VDDSDR
GND
24_48MHz/FS2*
48MHZ/FS3*
VDD48
VDDSDR
SDRAM8
SDRAM9
GND
1 - 24/48MHz@ 3.3V
1 - 48MHz @ 3.3V fixed
1 - REF @3.3V, 14.318MHz
1*FS0/PCICLK0
1*FS1/PCICLK1
1*SEL24_48#/PCICLK2
GND
PCICLK3
PCICLK4
PCICLK5
VDDPCI
PCICLK6
PCICLK7
GND
Features/Benefits:
•
•
•
•
•
•
Programmable output frequency.
Programmable output divider ratios.
Programmable output rise/fall time.
Programmable output skew.
Programmable spread percentage for EMI control.
Watchdog timer technology to reset system
if system malfunctions.
Vtt_PWRGD/PD#
SCLK
SDATA
VDDSDR
SDRAM11
SDRAM10
GND
•
•
Programmable watch dog safe frequency.
Support I2C Index read/write and block read/write
operations.
56-Pin 300-mil SSOP
1. These pins will have 1.5 to 2X drive strength.
* Internal Pull-up resistor of 120K to VDD
•
Uses external 14.318MHz crystal.
Key Specifications:
•
•
CPU Output Jitter: <250ps
IOAPIC Output Jitter: <500ps
48MHz, 3V66, PCI Output Jitter: <500ps
Ref Output Jitter. <1000ps
CPU Output Skew: <175ps
PCI Output Skew: <500ps
3V66 Output Skew <175ps
For group skew timing, please refer to the
Group Timing Relationship Table.
Block Diagram
•
•
•
•
•
•
PLL2
48MHz
24_48MHz
/ 2
X1
X2
XTAL
OSC
REF0
PLL1
Spread
CPU
DIVDER
CPUCLK (1:0)
2
Spectrum
SDRAM
DIVDER
SDRAM (11:0)
SDRAM_F
IOAPIC
12
FS(4:0)
Control
Logic
IOAPIC
DIVDER
PD#
SEL24_48#
Vtt_PWRGD
SDATA
Config.
Reg.
PCI
DIVDER
PCICLK (7:0)
3V66 (2:0)
8
3
SCLK
3V66
DIVDER
0470E—04/06/05
Integrated
Circuit
ICS950508
Systems, Inc.
General Description
The ICS950508 is a single chip clock solution for desktop designs using the 810/810E, 815 and 815 B-Step style chipset. It
provides all necessary clock signals for such a system.
The ICS950508 is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). ICS is the
first to introduce a whole product line which offers full programmability and flexibility on a single clock device. This part
incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a
serially programmable I2C interface, this device can adjust the output clocks by configuring the frequency setting, the output
divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each
individual output clock. TCH also incorporates ICS's Watchdog Timer technology and a reset feature to provide a safe setting
under unstable system conditions. M/N control can configure output frequency with resolution up to 0.1MHz increment. With
all these programmable features ICS's, TCH makes mother board testing, tuning and improvement very simple.
Pin Description
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
1, 9, 10, 18, 25, 32, 33, 37, 45 VDD
PWR 3.3V power supply
Crystal input, has internal load cap (33pF) and feedback resistor
from X2
Crystal output, nominally 14.318MHz. Has internal load cap
(33pF)
2
3
X1
X2
IN
OUT
4, 5, 14, 21, 28, 29, 36,
41, 49
GND
PWR Ground pins for 3.3V supply
8, 7, 6
3V66 (2:0)
OUT
3.3V Fixed 66MHz clock outputs for HUB
PCICLK01
FS0
PCICLK11
OUT
IN
3.3V PCI clock output, with Synchronous CPUCLKs
Logic input frequency select bit. Input latched at power on.
3.3V PCI clock output, with Synchronous CPUCLKs
11
OUT
12
FS1
IN
Logic input frequency select bit. Input latched at power on.
SEL_24_48#
PCICLK21
IN
Logic input to select output.
13
OUT
OUT
3.3V PCI clock output, with Synchronous CPUCLKs
3.3V PCI clock outputs, with Synchronous CPUCLKs
20, 19, 17, 16, 15
PCICLK (7:3)
Asynchronous active low input pin used to power down the device
into a low power state. The internal clocks are disabled and the
VCO and the crystal are stopped. The latency of the power down
will not be greater than 3ms.
This pin acts as a dual function input pin for Vtt_PWRGD and
PD# signal. When Vtt_PWRGD goes high the frequency select
will be latched at power on; thereafter the pin is an asynchronous
active low power down pin.
Clock pin for I2C circuitry 5V tolerant
Data pin for I2C circuitry 5V tolerant
Logic input frequency select bit. Input latched at power on.
3.3V Fixed 48MHz clock output for USB
Logic input frequency select bit. Input latched at power on.
PD#
IN
IN
22
Vtt_PWRGD
23
24
SCLK
SDATA
FS3
48MHz
FS2
IN
I/O
IN
OUT
IN
34
35
3.3V 24_48MHz output, selectable through pin 13, default is
24MHz.
24_48MHz
SDRAM_F
SDRAM (11:0)
GNDL
OUT
OUT
OUT
38
48, 46, 47, 44, 43, 42, 40, 39,
31, 30, 27, 26
3.3V SDRAM output can be turned off through I2C
3.3V output. All SDRAM outputs can be turned off through I2C
50
PWR Ground for 2.5V power supply for CPU & APIC
2.5V Host bus clock output. Output frequency derived from FS
51, 52
CPUCLK (1:0)
OUT
pins.
53, 55
54
VDDL
IOAPIC
FS4
PWR 2.5V power suypply for CPU, IOAPIC
OUT
IN
2.5V clock outputs running at 16.67MHz.
Logic input frequency select bit. Input latched at power on.
3.3V, 14.318MHz reference clock output.
56
REF01
OUT
0470E—04/06/05
2
Integrated
Circuit
ICS950508
Systems, Inc.
General I2C serial interface information
How to Read:
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2(H)
• ICS clock will acknowledge
• Controller (host) will send start bit.
• Controller (host) sends the write address D2(H)
• ICS clock will acknowledge
• Controller (host) sends the begining byte location = N
• ICS clock will acknowledge
• Controller (host) sends the begining byte
location = N
• Controller (host) sends the data byte count = X
• ICS clock will acknowledge
• Controller (host) starts sending Byte N through
Byte N + X -1
• ICS clock will acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address D3(H)
• ICS clock will acknowledge
(see Note 2)
• ICS clock will send the data byte count = X
• ICS clock sends Byte N + X -1
• ICS clock will acknowledge each byte one at a time
• ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
• Controller (host) sends a Stop bit
• Controller (host) will need to acknowledge each byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Read Operation
Index Block Write Operation
Controller (Host)
ICS (Slave/Receiver)
Controller (Host)
ICS (Slave/Receiver)
T
starT bit
starT bit
T
Slave Address D2(H)
Slave Address D2(H)
WR
WRite
WR
WRite
ACK
ACK
ACK
ACK
ACK
ACK
Beginning Byte = N
Beginning Byte = N
Data Byte Count = X
Beginning Byte N
RT
Repeat starT
Slave Address D3(H)
RD
ReaD
ACK
Data Byte Count = X
Beginning Byte N
ACK
ACK
Byte N + X - 1
ACK
P
stoP bit
Byte N + X - 1
N
P
Not acknowledge
stoP bit
*See notes on the following page.
0470E—04/06/05
3
Integrated
Circuit
ICS950508
Systems, Inc.
Byte 0: Functionality and frequency select register (Default=0)
Bit
Description
PWD
Bit2 Bit7 Bit6 Bit5 Bit4
FS4 FS3 FS2 FS1 FS0
CPUCLK SDRAM 3V66 PCICLK IOAPIC
MHz
MHz
MHz
MHz
MHz
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
66.43
60.00
66.80
68.33
70.00
75.00
80.00
83.00
99.65
90.00
99.65
90.00
66.43
60.00
33.21
30.00
33.40
34.17
35.00
37.50
40.00
41.50
33.21
30.00
33.41
34.33
35.00
36.67
38.33
66.66
33.21
41.67
33.41
34.25
35.00
36.25
37.50
40.00
33.21
41.67
33.41
34.25
35.00
36.25
37.50
40.00
16.61
15.00
16.70
17.08
17.50
18.75
20.00
20.75
16.61
15.00
16.70
17.17
17.50
18.33
19.17
33.33
16.61
20.83
16.70
17.13
17.50
18.13
18.75
20.00
16.61
20.83
16.7
100.20 66.80
102.50 68.33
105.00 70.00
112.50 75.00
120.00 80.00
124.50 83.00
99.65
90.00
66.43
60.00
100.23 100.23 66.84
103.00 103.00 68.67
105.00 105.00 70.00
110.00 110.00 73.33
115.00 115.00 76.67
200.00 200.00 133.33
132.86 132.86 66.43
166.67 166.67 83.34
133.64 133.64 66.82
137.00 137.00 68.50
140.00 140.00 70.00
145.00 145.00 72.50
150.00 150.00 75.00
160.00 160.00 80.00
Bit
(2,7:4)
Note 1
132.86
99.65
66.93
166.67 125.00 83.34
133.64 100.23 66.82
137.00 102.75 68.50
140.00 105.00 70.00
145.00 108.75 72.50
150.00 112.50 75.00
160.00 120.00 80.00
17.13
17.50
18.13
18.75
20.00
0-Frequency is selected by hardware select, latched inputs
1- Frequency is selected by Bit 2,7:4
0- Normal
Bit 3
Bit 1
Bit 0
0
1
0
1- Spread spectrum enable 0.35% Center Spread
0- Running
1- Tristate all outputs
Notes:
1. Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
0470E—04/06/05
4
Integrated
Circuit
ICS950508
Systems, Inc.
Byte 1: Output Control Register
(1 = enable, 0 = disable)
Bit
Pin#
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
35
-
34
-
X
X
X
1
1
1
Readback FS3#
Readback FS0#
Readback FS2#
24MHz
(Reserved)
48MHz
1
1
(Reserved)
SDRAM_F
38
Byte 2: Output Control Register
(1 = enable, 0 = disable)
Bit
Pin#
39
40
42
43
44
46
47
48
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
SDRAM7
SDRAM6
SDRAM5
SDRAM4
SDRAM3
SDRAM2
SDRAM1
SDRAM0
Byte 3: Output Control Register
(1 = enable, 0 = disable)
Bit
Pin#
20
19
17
16
15
13
12
11
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
PCICLK7
PCICLK6
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
Byte 4: Output Control Register
(1 = enable, 0 = disable)
Bit
Pin#
8
6
7
-
54
-
51
52
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
X
1
X
1
1
3V66_2
3V66_0
3V66_1
Readback FS4#
IOAPIC
Readback FS1#
CPUCLK1
CPUCLK0
0470E—04/06/05
5
Integrated
Circuit
ICS950508
Systems, Inc.
Byte 5: Output Control Register
Bit
Pin# PWD
Description
Readback (SEL24, 48#)#
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
X
1
1
0
1
1
1
1
(Reserved)
(Reserved)
(Reserved)
SDRAM11
SDRAM10
SDRAM9
-
-
26
27
30
31
SDRAM8
Byte 6: Vendor ID Register
Bit
Name
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
X
X
X
X
X
0
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
-
Vendor ID2
Vendor ID1
Vendor ID0
ICS vendor ID is 001 as in number 1 in
frequency timing generation.
0
1
Byte 7: Revision ID and Device ID Register
Bit
Name
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Revision ID2
Revision ID1
Revision ID0
Device ID4
Device ID3
Device ID2
Device ID1
Device ID0
0
0
0
0
0
0
0
1
Device ID and Revision ID values will be
based on individual device and it's revisio,
"01h" in this case.
Byte 8: Byte Count Read Back Register
Bit
Name
Byte7
Byte6
Byte5
Byte4
Byte3
Byte2
Byte1
Byte0
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
1
0
0
0
Note: Writing to this register will configure
byte count and how many bytes will be
read back, default is 0FH = 15 bytes.
0470E—04/06/05
6
Integrated
Circuit
ICS950508
Systems, Inc.
Byte 9: Watchdog Timer Count Register
Bit
Name
WD7
WD6
WD5
WD4
WD3
WD2
WD1
WD0
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
1
0
0
0
0
The decimal representation of these 8 bits
correspond to X • 290ms the watchdog
timer will wait before it goes to alarm mode
and reset the frequency to the safe setting.
Default at power up is 16 • 290ms = 4.6
seconds.
Byte 10: Programming Enable bit 8 Watchdog Control Register
Bit
Name
PWD
Description
Programming Enable bit
Program
Enable
0 = no programming. Frequencies are selected by
HW latches or Byte0
Bit 7
0
1 = enable all I2C programing.
Bit 6 WD Enable
Bit 5 WD Alarm
0
0
0
0
0
0
0
Watchdog Enable bit
Watchdog Alarm Status 0 = normal 1= alarm status
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SF4
SF3
SF2
SF1
SF0
Watchdog safe frequency bits. Writing to these bits
will configure the safe frequency corrsponding to
Byte 0 Bit 2, 7:4 table
Byte 11: VCO Frequency M Divider (Reference divider) Control Register
Bit
Name
Ndiv 8
Mdiv 6
Mdiv 5
Mdiv 4
Mdiv 3
Mdiv 2
Mdiv 1
Mdiv 0
PWD
X
X
X
X
X
X
X
X
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
N divider bit 8
The decimal respresentation of Mdiv (6:0)
corresposd to the reference divider value.
Default at power up is equal to the latched
inputs selection.
Byte 12: VCO Frequency N Divider (VCO divider) Control Register
Bit
Name
Ndiv 7
Ndiv 6
Ndiv 5
Ndiv 4
Ndiv 3
Ndiv 2
Ndiv 1
Ndiv 0
PWD
X
X
X
X
X
X
X
X
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The decimal representation of Ndiv (8:0)
correspond to the VCO divider value.
Default at power up is equal to the latched
inputs selecton. Notice Ndiv 8 is located in
Byte 11.
0470E—04/06/05
7
Integrated
Circuit
ICS950508
Systems, Inc.
Byte 13: Spread Spectrum Control Register
Name
PWD
Description
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SS 7
SS 6
SS 5
SS 4
SS 3
SS 2
SS 1
SS 0
X
X
X
X
X
X
X
X
The Spread Spectrum (12:0) bit will
program the spread precentage. Spread
precent needs to be calculated based on
the VCO frequency, spreading profile,
spreading amount and spread frequency. It
is recommended to use the ICS spread
programming guide for spread
programming. Default power on is latched
FS divider.
Byte 14: Spread Spectrum Control Register
Bit
Name
Reserved
Reserved
Reserved
SS 12
SS 11
SS 10
SS 9
SS 8
PWD
X
X
X
X
X
X
X
X
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
Spread Spectrum Bit 12
Spread Spectrum Bit 11
Spread Spectrum Bit 10
Spread Spectrum Bit 9
Spread Spectrum Bit 8
Byte 15: Output Divider Control Register
Bit
Name
PWD
X
X
X
X
X
X
X
X
Description
SDRAM clock divider ratio can be
configured via these 4 bits individually.
For divider selection table refer to
Table 1. Default at power up is latched
FS divider.
CPU clock divider ratio can be
configured via these 4 bits individually.
For divider selection table refer to
Table 1. Default at power up is latched
FS divider.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SD Div 3
SD Div 2
SD Div 1
SD Div 0
CPU Div 3
CPU Div 2
CPU Div 1
CPU Div 0
Byte 16: Output Divider Control Register
Bit
Name
PWD
X
X
X
X
X
X
X
X
Description
PCI clock divider ratio can be
configured via these 4 bits individually.
For divider selection table refer to
Table 2. Default at power up is latched
FS divider.
AGP clock divider ratio can be
configured via these 4 bits individually.
For divider selection table refer to
Table 1. Default at power up is latched
FS divider.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PCI Div 3
PCI Div 2
PCI Div 1
PCI Div 0
AGP Div 3
AGP Div 2
AGP Div 1
AGP Div 0
0470E—04/06/05
8
Integrated
Circuit
ICS950508
Systems, Inc.
Byte 17: Output Divider Control Register
Bit
Name
PCI_INV
3V66_INV
SD_INV
CPU_INV
APIC Div 3
APIC Div 2
APIC Div 1
APIC Div 0
PWD
X
X
X
X
X
X
X
X
Description
PCICLK Phase Inversion bit
3V66 Phase Inversion bit
SDRAM Phase Inversion bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CPUCLK Phase Inversion bit
IOAPIC clock divider ratio can be
configured via these 4 bits individually. For
divider selection table refer to table 2.
Default at power up is latched FS divider.
Table 1
Table 2
Div (3:2)
Div (3:2)
00
01
10
11
00
01
10
11
Div (1:0)
Div (1:0)
00
01
10
11
/2
/3
/5
/7
/4
/6
/8
/16
/24
/40
/56
00
01
10
11
/4
/3
/5
/9
/8
/6
/16
/12
/20
/36
/32
/24
/40
/72
/12
/20
/28
/10
/14
/10
/18
Byte 18: Group Skew Control Register
Bit
Name
PWD
Description
These 2 bits delay the SDRAM with respect to
Bit 7
SD_Skew 0
1
CPUCLK
Bit 6
SD_Skew 1
0
00 = 0ps 01 = 250ps 10 = 500ps 11 =750ps
Bit 5
Bit 4
Reserved
Reserved
0
0
Reserved
Reserved
These 2 bits delay the CPU clock with respect
to all other clocks.
00 = 0ps 01 = 250ps 10 = 500ps 11 = 750ps
Reserved
Bit 3
Bit 2
CPU_Skew 1
CPU_Skew 0
1
0
Bit 1
Bit 0
Reserved
Reserved
0
0
Reserved
Byte 19: Group Skew Control Register
Bit
Name
PWD
Description
These 4 bits can change the 3V66 to PCI
skew from 1.4ns - 2.9ns. Each binary
increment or decrement of PCI_SKEW (3:0)
will increase or decrease the delay of the PCI
clocks by 100ps.
Bit 7
Bit 6
Bit 5
Bit 4
PCI_Skew 3
PCI_Skew 2
PCI_Skew 1
PCI_Skew 0
0
0
1
0
These 2 bits delay the 3V66 with respect to
Bit 3
Bit 2
3V66_Skew 1
3V66_Skew 0
1
0
CPUCLK
00 = 0ps 01 = 250ps 10 = 500ps 11 =750ps
Bit 1
Bit 0
Reserved
Reserved
0
0
Reserved
Reserved
0470E—04/06/05
9
Integrated
Circuit
ICS950508
Systems, Inc.
Byte 20: Group Skew Control Register
Bit
Name
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Reserved
Reserved
Reserved
Reserved
0
0
0
0
Reserved
Reserved
Reserved
Reserved
These 4 bits can change the 3V66 to APIC
skew from 1.4ns - 2.9ns. Default at power
up is - 2.5ns. Each binary increment or
decrement of APIC_SKEW (3:0) will
increase or decrease the delay of the PCI
clocks by 100ps.
Bit 3
Bit 2
Bit 1
Bit 0
APIC_Skew 3
APIC_Skew 2
APIC_Skew 1
APIC_Skew 0
0
0
1
0
Byte 21: Slew Rate Control Register
Bit
Name
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
24/48_Slew 1
24/48_Slew 0
3V66_Slew 1
3V66_Slew 0
APIC_Slew 1
APIC_Slew 0
REF_Slew 1
REF_Slew 0
0
1
0
1
0
1
0
1
24/48 MHz clock slew rate control bits.
10 = strong: 11 = normal; 01 = weak
3V66 clock slew rate control bits.
10 = strong: 11 = normal; 01 = weak
IOAPIC clock slew rate control bits.
10 = strong: 11 = normal; 01 = weak
REF clock slew rate control bits.
10 = strong: 11 = normal; 01 = weak
Byte 22: Slew Rate Control Register
Bit
Name
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
SD_F Slew 1
SD_F Slew 0
SD(11:8) Slew 1
SD(11:8) Slew 0
0
1
0
1
0
SDRAM_F clock slew rate control bits.
10 = strong: 11 = normal; 01 = weak
SDRAM (11:8) clock slew rate control bits.
10 = strong: 11 = normal; 01 = weak
SD(7:4) Slew 1
SD(7:4) Slew 0
SD(3:0) Slew 1
SD(3:0) Slew 0
SDRAM (7:4) clock slew rate control bits.
10 = strong: 11 = normal; 01 = weak
Bit 2
Bit 1
Bit 0
1
0
1
SDRAM (3:0) clock slew rate control bits.
10 = strong: 11 = normal; 01 = weak
Byte 23: Slew Rate Control Register
Bit
Name
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
PCI (7:4) Slew 1
PCI (7:4) Slew 0
PCI (3:0) Slew 1
PCI (3:0) Slew 0
0
1
0
1
0
PCI (7:4) clock slew rate control bits.
10 = strong: 11 = normal; 01 = weak
PCI (3:0) clock slew rate control bits.
10 = strong: 11 = normal; 01 = weak
CPU 1 Slew 1
CPU 1 Slew 0
CPU 0 Slew 1
CPU 0 Slew 0
CPUCLK 1 clock slew rate control bits.
10 = strong: 11 = normal; 01 = weak
Bit 2
Bit 1
Bit 0
1
0
1
CPUCLK 0 clock slew rate control bits.
10 = strong: 11 = normal; 01 = weak
0470E—04/06/05
10
Integrated
Circuit
ICS950508
Systems, Inc.
Absolute Maximum Ratings
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . 4.6 V
I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . 3.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Group Timing Relationship Table1
Group
CPU 66MHz
CPU 100MHz
CPU 133MHz
SDRAM 100MHz
CPU 133MHz
SDRAM 133MHz
SDRAM 100MHz
SDRAM 100MHz
Offset Tolerance Offset Tolerance Offset Tolerance Offset Tolerance
CPU to SDRAM 2.5ns
CPU to 3V66 7.5ns
SDRAM to 3V66 0.0ns
500ps
500ps
500ps
5.0ns
5.0ns
0.0ns
500ps
500ps
500ps
0.0ns
0.0ns
0.0ns
500ps
500ps
500ps
3.75ns
0.0ns
500ps
500ps
500ps
3.75ns
1.5 -
3.5ns
3V66 to PCI
1.5-3.5ns 500ps 1.5-3.5ns 500ps 1.5-3.5ns 500ps
500ps
PCI to PCI
0.0ns
1.0ns
N/A
0.0ns
1.0ns
N/A
0.0ns
1.0ns
N/A
0.0ns
1.0ns
N/A
USB & DOT
Asynch
Asynch
Asynch
Asynch
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +5%, VDDL=2.5 V+ 5%(unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
Operating
SYMBOL
VIH
CONDITIONS
MIN
TYP
MAX
VDD + 0.3
0.8
UNITS
V
2
VSS - 0.3
-5
VIL
V
IIH
VIN = VDD
5
mA
mA
mA
mA
IIL1
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
-5
IIL2
-200
IDD3.3OP CL = 0 pF; Select @ 66M
100
600
Supply Current
Power Down
IDD3.3PD CL = 0 pF; With input address to Vdd or GND
mA
Supply Current
Input frequency
Pin Inductance
Input Capacitance1
Fi
Lpin
VDD = 3.3 V;
14.318
MHz
nH
pF
7
5
CIN
Logic Inputs
Cout
CINX
Ttrans
Ts
Out put pin capacitance
X1 & X2 pins
6
pF
27
45
3
pF
Transition Time1
Settling Time1
Clk Stabilization1
Delay
To 1st crossing of target Freq.
From 1st crossing to 1% target Freq.
From VDD = 3.3 V to 1% target Freq.
mS
mS
mS
nS
3
TSTAB
3
tPZH,tPZH output enable delay (all outputs)
PLZ,tPZH
1
1
10
10
t
output disable delay (all outputs)
nS
1Guaranteed by design, not 100% tested in production.
0470E—04/06/05
11
Integrated
Circuit
ICS950508
Systems, Inc.
Electrical Characteristics - CPU
TA = 0 - 70°C; VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
RDSP2B
RDSN2B
VOH2B
CONDITIONS
MIN
13.5
13.5
2
TYP
15
MAX UNITS
Output Impedance1
Output Impedance1
Output High Voltage
Output Low Voltage
Vo=VDD*(0.5)
Vo=VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
45
45
Ω
Ω
V
V
16.5
2.48
0.04
-60
-7
VOL2B
0.4
-27
VOH@MIN = 1 V
IOH2B
IOL2B
Output High Current
mA
mA
VOH@MAX = 2.375V
VOL@MIN = 1.2 V
VOL@MAX =0.3V
-27
27
63
20
Output Low Current
30
1.6
1.6
55
Rise Time1
Fall Time1
Duty Cycle1
Skew1
tr2B
tf2B
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
0.4
0.4
45
0.95
0.85
50
ns
ns
%
dt2B
tsk2B
VT = 1.25 V
32
175
ps
VT = 1.25 V, CPU 66, SDRAM 100
200
165
400
180
250
250
450
250
CPU 100, SDRAM 100
CPU 133, SDRAM 100
CPU 133, SDRAM 133
Jitter, Cycle-to-cycle1
tjcyc-cyc2B
ps
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - IOAPIC
TA = 0 - 70°C; VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
RDSP4B
RDSN4B
VOH4B
CONDITIONS
MIN
9
TYP
MAX UNITS
Output Impedance1
Output Impedance1
Output High Voltage
Output Low Voltage
Vo=VDD*(0.5)
Vo=VDD*(0.5)
IOH = -5.5 mA
IOL = 9 mA
V
V
V
V
30
30
Ω
Ω
V
V
9
2
VOL4B
0.4
-21
OH@MIN = 1.4 V
IOH4B
IOL4B
Output High Current
mA
mA
OH@MAX = 2.5V
OL@MIN = 1.0 V
OL@MAX =0.2V
-36
36
Output Low Current
31
1.6
1.6
55
Rise Time1
Fall Time1
tr4B
tf4B
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
0.4
0.4
45
0.9
1
ns
ns
%
Duty Cycle1
dt4B
50
250
Jitter, Cycle-to-cycle1
tjcyc-cyc4B VT = 1.25 V
500
ps
1Guaranteed by design, not 100% tested in production.
0470E—04/06/05
12
Integrated
Circuit
ICS950508
Systems, Inc.
Electrical Characteristics - SDRAM
TA = 0 - 70°C; VDD = 3.3 V +/-5%, CL = 20 - 30 pF (unless otherwise stated)
PARAMETER
SYMBOL
RDSP3
RDSN3
VOH3
CONDITIONS
Vo=VDD*(0.5)
MIN
10
TYP
MAX UNITS
Output Impedance1
Output Impedance1
Output High Voltage
Output Low Voltage
24
24
Ω
Ω
V
V
Vo=VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
10
2.4
VOL3
0.4
-46
V
V
V
V
OH@MIN = 2 V
OH@MAX = 3.135V
OL@MIN = 1 V
IOH3
IOL3
Output High Current
mA
mA
-54
54
Output Low Current
OL@MAX =0.4V
53
1.6
1.6
55
Rise Time1
Fall Time1
tr3
tf3
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
0.4
0.4
45
1.2
0.9
50
ns
ns
%
Duty Cycle1
dt3
Skew1
tsk3
tjcyc-cyc3
VT = 1.5 V
VT = 1.5 V
218
225
250
250
ps
ps
Jitter, cycle-to-cycle1
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 3V66
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
SYMBOL
RDSP1
RDSN1
VOH1
CONDITIONS
MIN
TYP
MAX UNITS
Output Impedance1
Output Impedance1
Output High Voltage
Output Low Voltage
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -1 mA
12
12
2.4
55
55
Ω
Ω
V
V
VOL1
IOL = 1 mA
0.55
-33
VOH @ MIN = 1.0 V
OH @ MAX = 3.135 V
IOH1
IOL1
Output High Current
mA
mA
V
-33
30
VOL @ MIN = 1.95 V
VOL @ MAX = 0.4 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
Output Low Current
38
2
Rise Time1
Fall Time1
tr1
tf1
dt1
0.4
0.4
45
1.55
1.65
53
ns
ns
%
2
Duty Cycle1
55
175
500
Skew 1
tsk1
tjcyc-cyc1
VT = 1.5 V
VT = 1.5 V
94
ps
ps
Jitter, Cycle-to-cycle1
350
1Guaranteed by design, not 100% tested in production.
0470E—04/06/05
13
Integrated
Circuit
ICS950508
Systems, Inc.
Electrical Characteristics - PCI
TA = 0 - 70°C; VDD = 3.3 V +/-5%, CL = 10 - 30 pF (unless otherwise stated)
PARAMETER
SYMBOL
RDSP1
RDSN1
VOH1
CONDITIONS
MIN
12
TYP
MAX UNITS
Output Impedance1
Output Impedance1
Output High Voltage
Output Low Voltage
Vo=VDD*(0.5)
Vo=VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
55
55
Ω
Ω
V
V
12
2.4
VOL1
0.55
-33
VOH@MIN = 1 V
IOH1
IOL1
tr1
Output High Current
Output Low Current
mA
mA
ns
VOH@MAX = 3.135V
VOL@MIN = 1.95 V
OL@MAX =0.4V
-33
30
V
38
2
V
OL = 0.4 V, VOH = 2.4 V, PCI0-2
1.2
2.1
1
Rise Time1
0.5
PCI3-7
VOL = 2.4 V, VOH = 0.4 V, PCI0-2
PCI3-7
2.25
2
Fall Time1
tf1
0.5
45
ns
2
51
480
300
2.25
55
Duty Cycle1
dt1
tsk1
tjcyc-cyc1
VT = 1.5 V
VT = 1.5 V
VT = 1.5 V
%
ps
ps
Skew1
500
500
Jitter, cycle-to-cycle1
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - REF, 24_48MHz, 48MHz
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
RDSP5
RDSN5
VOH5
CONDITIONS
MIN
20
TYP
MAX UNITS
Output Impedance1
Output Impedance1
Output High Voltage
Output Low Voltage
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -1 mA
60
60
Ω
Ω
V
V
20
2.4
VOL5
IOL = 1 mA
0.4
-23
V
V
V
V
OH @ MIN = 1.0 V
IOH5
IOL5
Output High Current
mA
mA
OH @ MAX = 3.135 V
OL @ MIN = 1.95 V
OL @ MAX = 0.4 V
-29
29
Output Low Current
27
4
Rise Time1
Fall Time1
Duty Cycle1
tr5
tf5
dt5
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
0.4
0.4
45
1
1
53
ns
ns
%
4
55
VT = 1.5 V, 24, 48 MHz
VT = 1.5 V, Ref clocks
1Guaranteed by design, not 100% tested in production.
250
2000
500
3000
Jitter, cycle-to-cycle1
tjcyc-cyc5
ps
0470E—04/06/05
14
Integrated
Circuit
ICS950508
Systems, Inc.
Shared Pin Operation -
Input/Output Pins
Figure 1 shows a means of implementing this function
when a switch or 2 pin header is used. With no jumper is
installed the pin will be pulled high. With the jumper in
place the pin will be pulled low. If programmability is not
necessary, than only a single resistor is necessary. The
programming resistors should be located close to the series
termination resistor to minimize the current loop area. It is
more important to locate the series termination resistor
close to the driver than the programming resistor.
The I/O pins designated by (input/output) serve as dual
signal functions to the device. During initial power-up, they
act as input pins. The logic level (voltage) that is present on
these pins at this time is read and stored into a 5-bit internal
data latch. At the end of Power-On reset, (see AC
characteristics for timing values), the device changes the
mode of operations for these pins to an output function. In
this mode the pins produce the specified buffered clocks to
external loads.
To program (load) the internal configuration register for
these pins, a resistor is connected to either the VDD (logic 1)
power supply or the GND (logic 0) voltage potential. A 10
Kilohm (10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Via to
VDD
Programming
Header
2K W
Via to Gnd
Device
Pad
8.2K W
Clock trace to load
Series Term. Res.
Fig. 1
0470E—04/06/05
15
Integrated
Circuit
ICS950508
Systems, Inc.
Power Down Waveform
0ns
50ns
2
25ns
1
VCO Internal
CPU 100MHz
3.3V 66MHz
PCI 33MHz
APIC 16.7MHz
PD#
SDRAM 100MHz
REF 14.318MHZ
48MHZ
Note
1. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all
the output clocks are driven Low on their next High to Low tranistiion.
2. Power-up latency <3ms.
3. Waveform shown for 100MHz
0470E—04/06/05
16
Integrated
Circuit
ICS950508
Systems, Inc.
0ns
10ns
20ns
30ns
40ns
Cycle Repeats
CPU 66MHz
CPU 100MHz
CPU 133MHz
SDRAM 100MHz
SDRAM 133MHz
3.5V 66MHz
PCI 33MHz
APIC 16.7MHz
REF 14.318MHz
USB 48MHz
Group Offset Waveforms
0470E—04/06/05
17
Integrated
Circuit
ICS950508
Systems, Inc.
In Millimeters
COMMON DIMENSIONS COMMON DIMENSIONS
In Inches
c
N
SYMBOL
MIN
2.41
0.20
0.20
0.13
MAX
2.80
0.40
0.34
0.25
MIN
.095
.008
.008
.005
MAX
.110
.016
.0135
.010
A
A1
b
c
D
E
L
E1
E
INDEX
AREA
SEE VARIATIONS
10.03
7.40
SEE VARIATIONS
.395
.291
10.68
7.60
.420
.299
E1
e
1
22
0.635 BASIC
0.025 BASIC
a
h
L
0.38
0.50
0.64
1.02
.015
.020
.025
.040
h x 45°
D
N
α
SEE VARIATIONS
SEE VARIATIONS
0°
8°
0°
8°
A
VARIATIONS
D mm.
D (inch)
A1
N
MIN
18.31
MAX
18.55
MIN
.720
MAX
.730
- C -
56
e
Reference Doc.: JEDEC Publication 95, M O-118
SEATING
PLANE
b
10 - 0 0 3 4
.10 ((..000044)) CC
Ordering Information
ICS950508yFLF-T
Example:
ICS XXXX y F LF- T
Designation for tape and reel packaging
Annealed Lead Free (Optional)
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
0470E—04/06/05
18
Integrated
Circuit
ICS950508
Systems, Inc.
Revision History
Rev.
D
Issue Date Description
Page #
9-10
8
3/15/2005 Update default values of Bytes 18-20
E
4/6/2005 Update Byte 13 spread programming information
0470E—04/06/05
19
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