952623YFT [IDT]
Processor Specific Clock Generator, 400MHz, CMOS, PDSO56;
| 型号： | 952623YFT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Processor Specific Clock Generator, 400MHz, CMOS, PDSO56 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总28页 (文件大小：242K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
ICS952623
Systems, Inc.
Programmable Timing Control Hub™ for Next Gen P4™ processor
Recommended Application:
Features/Benefits:
CK409 clock, Intel Yellow Cover part
•
•
Supports tight ppm accuracy clocks for Serial-ATA
Supports spread spectrum modulation, 0 to -0.5%
down spread and +/- 0.25% center spread
Output Features:
•
•
•
•
•
•
•
•
•
3 - 0.7V current-mode differential CPU pairs
1 - 0.7V current-mode differential SRC pair
7 - PCI (33MHz)
3 - PCICLK_F, (33MHz) free-running
1 - USB, 48MHz
1 - DOT, 48MHz
2 - REF, 14.318MHz
4 - 3V66, 66.66MHz
1 - VCH/3V66, selectable 48MHz or 66MHz
•
•
•
Supports CPU clks up to 400MHz in test mode
Uses external 14.318MHz crystal
Supports undriven differential CPU, SRC pair in PD#
and CPU_STOP# for power management.
Pin Configuration
REF0
REF1
VDDREF
X1
1
2
3
4
5
6
7
8
9
56 FS_B
55 VDDA
54 GNDA
53 GND
52 IREF
51 FS_A
50 CPU_STOP#
49 PCI_STOP#
48 VDDCPU
47 CPUCLKT2
46 CPUCLKC2
45 GND
44 CPUCLKT1
43 CPUCLKC1
42 VDDCPU
41 CPUCLKT0
40 CPUCLKC0
39 GND
Key Specifications:
•
•
•
•
•
CPU/SRC outputs cycle-cycle jitter < 125ps
3V66 outputs cycle-cycle jitter < 250ps
PCI outputs cycle-cycle jitter < 250ps
CPU outputs skew: < 100ps
X2
GND
PCICLK_F0
PCICLK_F1
PCICLK_F2
+/- 300ppm frequency accuracy on CPU & SRC clocks
VDDPCI 10
GND 11
Functionality
PCICLK0 12
PCICLK1 13
PCICLK2 14
PCICLK3 15
VDDPCI 16
GND 17
PCICLK4 18
PCICLK5 19
PCICLK6 20
PD# 21
CPU
B6b5 FS_A FS_B MHz
SRC
MHz
3V66 PCI
MHz MHz
REF USB/DOT
MHz
MHz
48.00
0
0
0
1
1
1
0
0
1
1
0
100 100/200 66.66 33.33 14.318
MID Ref/N0 Ref/N1 Ref/N2 Ref/N3 Ref/N4 Ref/N5
1
0
1
200 100/200 66.66 33.33 14.318
133 100/200 66.66 33.33 14.318
166 100/200 66.66 33.33 14.318
48.00
48.00
48.00
Hi-Z
48.00
48.00
48.00
48.00
0
1
MID Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
0
1
0
1
200 100/200 66.66 33.33 14.318
400 100/200 66.66 33.33 14.318
266 100/200 66.66 33.33 14.318
333 100/200 66.66 33.33 14.318
38 SRCCLKT
37 SRCCLKC
36 VDD
3V66_0 22
3V66_1 23
VDD3V66 24
GND 25
3V66_2 26
3V66_3 27
SCLK 28
35 Vtt_PWRGD#
34 VDD48
33 GND
32 48MHz_DOT
31 48MHz_USB
30 SDATA
29 3V66_4/VCH
56-pin SSOP & TSSOP
0758A—02/06/07
Integrated
Circuit
ICS952623
Systems, Inc.
Pin Description
PIN
#
1
2
3
4
5
6
7
PIN NAME
PIN TYPE
DESCRIPTION
14.318 MHz reference clock.
14.318 MHz reference clock.
Ref, XTAL power supply, nominal 3.3V
Crystal input, Nominally 14.318MHz.
Crystal output, Nominally 14.318MHz
Ground pin.
Free running PCI clock not affected by PCI_STOP# .
Free running PCI clock not affected by PCI_STOP# .
Free running PCI clock not affected by PCI_STOP# .
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clock output.
PCI clock output.
PCI clock output.
PCI clock output.
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clock output.
PCI clock output.
PCI clock output.
REF0
REF1
OUT
OUT
PWR
IN
VDDREF
X1
X2
GND
OUT
PWR
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
PCICLK_F0
PCICLK_F1
PCICLK_F2
VDDPCI
GND
PCICLK0
PCICLK1
PCICLK2
PCICLK3
VDDPCI
GND
8
9
10
11
12
13
14
15
16
17
18
19
20
PCICLK4
PCICLK5
PCICLK6
Asynchronous active low input pin used to power down the device
into a low power state. The internal clocks are disabled and the
VCO and the crystal are stopped. The latency of the power down
will not be greater than 1.8ms. Internal pull-up of 150K nominal.
21
PD#
IN
22
23
24
25
26
27
28
3V66_0
3V66_1
VDD3V66
GND
3V66_2
3V66_3
SCLK
OUT
OUT
PWR
PWR
OUT
OUT
IN
3.3V 66.66MHz clock output
3.3V 66.66MHz clock output
Power pin for the 3V66 clocks.
Ground pin.
3.3V 66.66MHz clock output
3.3V 66.66MHz clock output
Clock pin of I2C circuitry 5V tolerant
0758A—02/06/07
2
Integrated
Circuit
ICS952623
Systems, Inc.
Pin Description (Continued)
PIN
#
PIN NAME
PIN TYPE
DESCRIPTION
66.66MHz clock output for AGP support. AGP-PCI should be
aligned with a skew window tolerance of 500ps.
VCH is 48MHz clock output for video controller hub.
Data pin for I2C circuitry 5V tolerant
48MHz clock output.
48MHz clock output.
Ground pin.
Power for 48MHz output buffers and fixed PLL core.
29
3V66_4/VCH
OUT
30
31
32
33
34
SDATA
I/O
48MHz_USB
48MHz_DOT
GND
OUT
OUT
PWR
PWR
VDD48
This 3.3V LVTTL input is a level sensitive strobe used to determine
when latch inputs are valid and are ready to be sampled. This is an
active low input.
35
Vtt_PWRGD#
IN
36
37
VDD
PWR
OUT
Power supply for SRC clocks, nominal 3.3V
Complement clock of differential pair for S-ATA support.
+/- 300ppm accuracy required.
SRCCLKC
True clock of differential pair for S-ATA support.
+/- 300ppm accuracy required.
Ground pin.
38
39
SRCCLKT
GND
OUT
PWR
"Complementary" clocks of differential pair CPU outputs. These are
current mode outputs. External resistors are required for voltage
bias.
40
CPUCLKC0
OUT
"True" clocks of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
41
42
CPUCLKT0
VDDCPU
OUT
PWR
"Complementary" clocks of differential pair CPU outputs. These are
current mode outputs. External resistors are required for voltage
bias.
43
CPUCLKC1
OUT
"True" clocks of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
Ground pin.
44
45
CPUCLKT1
GND
OUT
PWR
"Complementary" clocks of differential pair CPU outputs. These are
current mode outputs. External resistors are required for voltage
bias.
46
CPUCLKC2
OUT
"True" clocks of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
47
48
CPUCLKT2
VDDCPU
OUT
PWR
Stops all PCICLKs and SRC pair besides the PCICLK_F clocks at
logic 0 level, when input low. PCI and SRC clocks can be set to
Free_Running through I2C. Internal pull-up of 150K nominal.
Stops all CPUCLK besides the free running clocks. Internal pull-up
of 150K nominal
Frequency select pin, see Frequency table for functionality
IREF establishes the reference current for the CPUCLK pairs. A
fixed precision resistor tied to ground is required to establish the
appropriate current.
49
PCI_STOP#
IN
50
51
CPU_STOP#
FS_A
IN
IN
52
IREF
OUT
53
54
55
56
GND
PWR
PWR
PWR
IN
Ground pin.
Ground pin for core.
3.3V power for the PLL core.
Frequency select pin, see Frequency table for functionality
GNDA
VDDA
FS_B
0758A—02/06/07
3
Integrated
Circuit
ICS952623
Systems, Inc.
General Description
ICS952623 follows Intel CK409 Yellow Cover specification. This clock synthesizer provides a single chip solution for next
generation P4 Intel processors and Intel chipsets. ICS952623 is driven with a 14.318MHz crystal. It generates CPU outputs up
to 200MHz. It also provides a tight ppm accuracy output for Serial ATA support.
Block Diagram
Frequency
Dividers
48MHz, USB, DOT
PLL2
X1
X2
XTAL
REF (1:0)
CPUCLKT (2:0)
CPUCLKC (2:0)
SRCCLKT0
SRCCLKC0
3V66(4:0)
Programmable
Spread
Programmable
Frequency
Dividers
STOP
Logic
SCLK
SDATA
PLL1
CPU_STOP#
PCI_STOP#
Vtt_PWRGD#
PD#
PCICLK (6:0)
PCICLKF (2:0)
Control
Logic
FS_A
I REF
FS_B
Power Groups
Pin Number
Description
VDD
3
GND
6
Xtal, Ref
3V66 [0:3]
24
25
10,16
36
55
11,17
39
54
PCICLK outputs
SRCCLK outputs
Master clock, CPU Analog
48MHz, PLL
34
33
N/A
48, 42
53
45
IREF
CPUCLK clocks
0758A—02/06/07
4
Integrated
Circuit
ICS952623
Systems, Inc.
Absolute Max
Symbol
Parameter
Min
Max
Units
VDD_A
3.3V Core Supply Voltage
VDD + 0.5V
VDD + 0.5V
V
V
VDD_In 3.3V Logic Input Supply Voltage GND - 0.5
Ts
Tambient
Tcase
Storage Temperature
Ambient Operating Temp
Case Temperature
-65
0
150
70
115
°C
°C
°C
Input ESD protection
human body model
ESD prot
2000
V
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
Input High Voltage
Input MID Voltage
Input Low Voltage
Input High Current
VIH
VMID
VIL
3.3 V +/-5%
3.3 V +/-5%
2
VDD + 0.3
V
V
1
VSS - 0.3
-5
1.8
0.8
5
3.3 V +/-5%
V
IIH
VIN = VDD
uA
VIN = 0 V; Inputs with no pull-
up resistors
IIL1
IIL2
Operating Supply Current IDD3.3OP
-5
uA
Input Low Current
VIN = 0 V; Inputs with pull-up
resistors
-200
uA
Full Active, CL = Full load;
350
mA
all diff pairs driven
all differential pairs tri-stated
VDD = 3.3 V
35
12
mA
mA
MHz
nH
pF
Powerdown Current
IDD3.3PD
Input Frequency3
Pin Inductance1
Fi
14.31818
3
1
1
1
1
Lpin
7
5
6
5
CIN
Logic Inputs
Output pin capacitance
X1 & X2 pins
Input Capacitance1
COUT
CINX
pF
pF
From VDD Power-Up or de-
assertion of PD# to 1st clock
Triangular Modulation
SRC output enable after
PCI_Stop# de-assertion
CPU output enable after
PD# de-assertion
Clk Stabilization1,2
Modulation Frequency
Tdrive_SRC
TSTAB
1.8
ms
1,2
30
33
15
kHz
ns
1
1
Tdrive_PD#
300
us
1
Tfall_Pd#
Trise_Pd#
PD# fall time of
PD# rise time of
5
5
ns
ns
1
2
CPU output enable after
CPU_Stop# de-assertion
PD# fall time of
Tdrive_CPU_Stop#
10
us
1
Tfall_CPU_Stop#
Trise_CPU_Stop#
5
5
ns
ns
1
2
PD# rise time of
1Guaranteed by design, not 100% tested in production.
2See timing diagrams for timing requirements.
3 Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet
ppm frequency accuracy on PLL outputs.
0758A—02/06/07
5
Integrated
Circuit
ICS952623
Systems, Inc.
Electrical Characteristics - CPU & SRC 0.7V Current Mode Differential Pair
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF
PARAMETER
SYMBOL
Zo1
CONDITIONS
VO = Vx
MIN
TYP
MAX
850
UNITS NOTES
Current Source Output
Impedance
3000
Ω
1
Statistical measurement on
single ended signal using
oscilloscope math function.
Voltage High
Voltage Low
VHigh
VLow
660
1
1
mV
-150
150
Max Voltage
Min Voltage
Crossing Voltage (abs)
Vovs
Vuds
Vcross(abs)
Measurement on single ended
signal using absolute value.
1150
1
1
1
mV
mV
mV
-300
250
550
140
Variation of crossing over all
edges
see Tperiod min-max values
200MHz nominal
Crossing Voltage (var)
Long Accuracy
d-Vcross
ppm
1
-300
300
ppm
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
1,2
2
2
2
2
2
2
2
2
1,2
1,2
1,2
1,2
1
4.9985
4.9985
5.9982
5.9982
7.4978
7.4978
9.9970
9.9970
4.8735
5.8732
7.3728
9.8720
175
5.0015
5.0266
6.0018
6.0320
7.5023
5.4000
10.0030
10.0533
200MHz spread
166.66MHz nominal
166.66MHz spread
133.33MHz nominal
133.33MHz spread
100.00MHz nominal
100.00MHz spread
Average period
Tperiod
200MHz nominal
166.66MHz nominal/spread
133.33MHz nominal/spread
100.00MHz nominal/spread
VOL = 0.175V, VOH = 0.525V
Absolute min period
Tabsmin
Rise Time
Fall Time
tr
700
700
125
125
tf
VOH = 0.525V VOL = 0.175V
175
ps
ps
ps
1
1
1
Rise Time Variation
Fall Time Variation
d-tr
d-tf
Measurement from differential
wavefrom
VT = 50%
Measurement from differential
wavefrom
Duty Cycle
Skew
dt3
tsk3
45
55
%
ps
ps
1
1
1
100
125
Jitter, Cycle to cycle
tjcyc-cyc
1Guaranteed by design, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at
14.31818MHz
SRC clock outputs run at only 100MHz or 200MHz, specs for 133.33 and 166.66 do not apply to SRC clock pair.
0758A—02/06/07
6
Integrated
Circuit
ICS952623
Systems, Inc.
Electrical Characteristics - 3V66 Mode: 3V66 [4:0]
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
Long Accuracy
SYMBOL
ppm
CONDITIONS
see Tperiod min-max values
66.66MHz output nominal
66.66MHz output spread
IOH = -1 mA
MIN
-300
14.9955
14.9955
2.4
TYP
MAX
300
15.0045
15.0799
UNITS Notes
ppm
ns
1,2
2
Clock period
Tperiod
ns
2
Output High Voltage
Output Low Voltage
VOH
VOL
V
IOL = 1 mA
0.55
-33
V
V OH @ MIN = 1.0 V
VOH @ MAX = 3.135 V
VOL @ MIN = 1.95 V
-33
30
mA
mA
Output High Current
Output Low Current
IOH
IOL
mA
mA
V
OL @ MAX = 0.4 V
Rising edge rate
Falling edge rate
38
4
4
Edge Rate
Edge Rate
Rise Time
1
1
0.5
V/ns
V/ns
ns
1
1
1
tr1
tf1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
2
Fall Time
Duty Cycle
Skew
0.5
45
2
ns
%
1
1
1
1
dt1
55
tsk1
VT = 1.5 V
250
250
ps
ps
Jitter
tjcyc-cyc
VT = 1.5 V 3V66
1Guaranteed by design, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is
at 14.31818MHz
Electrical Characteristics - PCICLK/PCICLK_F
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
Long Accuracy
Clock period
SYMBOL
ppm
CONDITIONS
MIN
TYP MAX
UNITS Notes
see Tperiod min-max values
33.33MHz output nominal
33.33MHz output spread
IOH = -1 mA
-300
29.9910
29.9910
2.4
300
30.0090
30.1598
ppm
ns
1,2
2
Tperiod
ns
2
Output High Voltage
Output Low Voltage
VOH
VOL
V
IOL = 1 mA
V OH @MIN = 1.0 V
VOH@ MAX = 3.135 V
VOL @ MIN = 1.95 V
VOL @ MAX = 0.4 V
Rising edge rate
0.55
-33
V
mA
mA
mA
mA
V/ns
V/ns
ns
-33
30
Output High Current
Output Low Current
IOH
IOL
38
4
Edge Rate
Edge Rate
Rise Time
Fall Time
Duty Cycle
Skew
1
1
1
1
1
1
1
1
Falling edge rate
1
4
2
tr1
tf1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
0.5
0.5
45
2
ns
dt1
55
500
250
%
tsk1
VT = 1.5 V
ps
Jitter
tjcyc-cyc
VT = 1.5 V 3V66
ps
1Guaranteed by design, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref
output is at 14.31818MHz
0758A—02/06/07
7
Integrated
Circuit
ICS952623
Systems, Inc.
Electrical Characteristics - 48MHz DOT Clock
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 5-10 pF (unless otherwise specified)
PARAMETER
Long Accuracy
SYMBOL
ppm
CONDITIONS
MIN
-200
TYP MAX
UNITS Notes
see Tperiod min-max
values
48MHz output nominal 20.8257
200
ppm
1,2
2
Clock period
Output High Voltage
Output Low Voltage
Tperiod
VOH
20.8340
ns
V
IOH = -1 mA
IOL = 1 mA
2.4
-33
30
VOL
0.55
-33
V
V
OH @ MIN = 1.0 V
mA
mA
mA
mA
V/ns
V/ns
Output High Current
Output Low Current
IOH
IOL
V
OH @ MAX = 3.135 V
V
OL @ MIN = 1.95 V
OL @ MAX = 0.4 V
Rising edge rate
Falling edge rate
V
38
4
Edge Rate
Edge Rate
2
2
1
1
4
Rise Time
tr1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
0.5
1
ns
1
Fall Time
tf1
0.5
45
1
ns
%
1
1
Duty Cycle
dt1
VT = 1.5 V
55
125us period jitter
(8kHz frequency
Long Term Jitter
2
ns
1
modulation amplitude)
1Guaranteed by design, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref
output is at 14.31818MHz
0758A—02/06/07
8
Integrated
Circuit
ICS952623
Systems, Inc.
Electrical Characteristics - VCH, 48MHz, USB
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS Notes
Long Accuracy
Clock period
Output High Voltage
Output Low Voltage
ppm
Tperiod
VOH
see Tperiod min-max values
48MHz output nominal
IOH = -1 mA
-200
20.8257
2.4
200
20.8340 ns
V
ppm
1,2
2
VOL
IOL = 1 mA
0.55
V
V OH @ MIN = 1.0 V
VOH@ MAX = 3.135 V
VOL @MIN = 1.95 V
VOL @ MAX = 0.4 V
Rising edge rate
-33
30
mA
mA
mA
mA
V/ns
V/ns
Output High Current
Output Low Current
IOH
IOL
-33
38
2
Edge Rate
Edge Rate
Rise Time
Fall Time
1
1
1
1
1
1
1
Falling edge rate
2
tr1
tf1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
1
2
2
ns
ns
%
1
Duty Cycle
dt1
VT = 1.5 V
125us period jitter
(8kHz frequency modulation
amplitude)
45
55
Long Term Jitter
6
ns
1
1Guaranteed by design, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref
output is at 14.31818MHz
0758A—02/06/07
9
Integrated
Circuit
ICS952623
Systems, Inc.
Electrical Characteristics - REF-14.318MHz
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
ppm
ppm1
Tperiod
Long Accuracy
Clock period
see Tperiod min-max values
14.318MHz output nominal
IOH = -1 mA
-300
69.8270
2.4
300
69.8550
ns
V
1
Output High Voltage
Output Low Voltage
VOH
1
IOL = 1 mA
0.4
-23
V
VOL
V OH @MIN = 1.0 V,
V OH@MAX = 3.135 V
VOL @MIN = 1.95 V,
VOL @MAX = 0.4 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1
Output High Current
Output Low Current
-29
29
mA
mA
IOH
1
27
IOL
1
Rise Time
Fall Time
Skew
1
1
2
2
ns
ns
ps
%
tr1
1
tf1
1
500
55
tsk1
1
Duty Cycle
Jitter
dt1
VT = 1.5 V
VT = 1.5 V
45
1
tjcyc-cyc
1000
ps
1Guaranteed by design, not 100% tested in production.
Group to Group Skews at Common Transition Edges
GROUP
3V66 to PCI
DOT-USB
DOT-VCH
SYMBOL
S3V66-PCI
SDOT_USB
SDOT_VCH
CONDITIONS
MIN TYP MAX UNITS
3V66 (4:0) leads 33MHz PCI 1.50
3.50
1.00
1.00
ns
ns
ns
180 degrees out of phase
in phase
0.00
0.00
0758A—02/06/07
10
Integrated
Circuit
ICS952623
Systems, Inc.
I2C Table: Read-Back Register
Byte 0
Bit 7
Bit 6
Bit 5
Bit 4
Pin #
Name
RESERVED
RESERVED
RESERVED
RESERVED
PCI_STOP#
Control Function
RESERVED
Type
-
-
-
-
0
1
PWD
X
X
X
X
-
-
-
-
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
PCI STOP# Read
Back
CPU STOP Read
Back
Freq Select 1 Read
Back
Freq Select 0 Read
Back
-
-
-
-
R
R
R
R
READBACK
READBACK
X
X
X
Bit 3
Bit 2
Bit 1
Bit 0
CPU_STOP#
FSB
READBACK of CPU(2:0)
Frequency
FSA
X
I2C Table: Spreading and Device Behavior Control Register
Byte 1
Pin #
Name
Control Function
SRC Free-Running
Control
Type
0
1
PWD
37,38
SRC/SRC#
RW
FREE-RUN STOPPABLE
0
Bit 7
37,38
46,47
43,44
40,41
46,47
43,44
40,41
SRC
Output Control
RW
RW
RW
RW
RW
RW
RW
Disable Enable
1
1
1
1
1
1
1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CPUT2/CPUC2
CPUT1/CPUC1
CPUT0/CPUC0
CPUT2/CPUC2
CPUT1/CPUC1
CPUT0/CPUC0
FREE-RUN STOPPABLE
FREE-RUN STOPPABLE
FREE-RUN STOPPABLE
CPU FREE-RUNNING
CONTROL
Output Control
Output Control
Output Enable
Disable
Disable
Disable
Enable
Enable
Enable
I2C Table: Output Control Register
Byte 2 Pin #
Name
SRC_PD#
Control Function
Type
0
1
PWD
37,38
Bit 7
0: Driven in PD#
RW
Driven
Hi-Z
0
Drive Mode
SRC_Stop#
Drive Mode
CPUT2_PD# Drive
Mode
0: Driven in
PCI_Stop#
37,38
RW
RW
RW
RW
RW
RW
RW
Driven
Driven
Driven
Driven
Driven
Driven
Driven
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
0
0
0
0
0
0
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
46,47
43,44
0:driven in PD#
1: Tri-stated
CPUT1_PD# Drive
Mode
CPUT0_PD# Drive
Mode
40,41
CPUT2_Stop Drive
Mode
CPUT1_Stop Drive
Mode
46,47
43,44
0:driven when stopped
1: Tri-stated
CPUT0_Stop Drive
Mode
40,41
0758A—02/06/07
11
Integrated
Circuit
ICS952623
Systems, Inc.
I2C Table: Output Control Register
Byte 3
Pin #
Name
Control Function
Type
0
1
PWD
PCI_Stop# Control
0:all stoppable PCI
are stopped
7,8,9,12,13,14,15,
18,19,20,37,38,
PCI_Stop#
RW
Enable
Disable
1
Bit 7
20
19
18
15
14
13
12
PCICLK6
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
RW
RW
RW
RW
RW
RW
RW
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
1
1
1
1
1
1
1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
I2C Table: Output Control Register
Byte 4 Pin #
Name
Control Function
0=2x drive
Type
0
1
PWD
48MHz_USB
2x output drive
48MHz_USB
PCIF2
31
RW
2x drive
normal
0
Bit 7
31
9
Output Control
RW
RW
RW
RW
RW
RW
RW
Disable
Enable
1
0
0
0
1
1
1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FREE-RUN STOPPABLE
FREE-RUN STOPPABLE
FREE-RUN STOPPABLE
Disable
Disable
Disable
PCI FREE-RUN NING
CONTROL
8
7
PCIF1
PCIF0
9
8
7
PCICLK_F2
PCICLK_F1
PCICLK_F0
Output Control
Output Control
Output Control
Enable
Enable
Enable
I2C Table: Output Control Register
Byte 5 Pin #
Bit 7
Name
48MHZ_DOT
RESERVED
3V66_4/VCH
Select
Control Function
Output Control
RESERVED
Type
RW
`
0
1
Enable
-
PWD
1
0
32
-
Disable
-
Bit 6
29
Output Select
RW
3V66
VCH
0
Bit 5
29
27
26
23
22
3V66_4/VCH
3V66_3
Output Control
Output Control
Output Control
Output Control
Output Control
RW
RW
RW
RW
RW
Disable
Disable
Disable
Disable
Disable
Enable
Enable
Enable
Enable
Enable
1
1
1
1
1
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
3V66_2
3V66_1
3V66_0
0758A—02/06/07
12
Integrated
Circuit
ICS952623
Systems, Inc.
I2C Table: Output Control and Fix Frequency Register
Byte 6
Pin #
Name
Control Function
Type
0
1
PWD
1,2,7,8,9,12,13,14,
15,18,19,20,22,23,2
6,27,29,31,32,37,38
,40,41,43,44,46,47
Test Clock Mode
Test Clock Mode
-
Disable
Enable
0
Bit 7
-
RESERVED
RESERVED
-
-
-
-
-
0
0
Bit 6
Bit 5
FS_A and FS_B
Operation
40,41,43,44,46,47
Normal
Test Mode
SRC Frequency
Select
Down/Center
37,38
RESERVED
Spread Type
-
-
100MHz
Down
200MHz
Center
0
0
Bit 4
Bit 3
7,8,9,12,13,14,15,1
8,19,20,22,23,26,27
,29,31,32,37,38,40,
41,43,44,46,47
Spread
OFF
Spread
ON
Spread Spectrum Mode
0
Bit 2
2
1
REF1
REF0
Output Control
Output Control
RW
RW
Disable
Disable
Enable
Enable
1
1
Bit 1
Bit 0
I2C Table: Vendor & Revision ID Register
Byte 7
Bit 7
Pin #
Name
RID3
RID2
RID1
RID0
VID3
VID2
VID1
VID0
Control Function
Type
R
R
R
R
R
R
R
R
0
-
-
-
-
-
-
-
-
1
-
-
-
-
-
-
-
-
PWD
-
-
-
-
-
-
-
-
0
0
0
0
0
0
0
1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
REVISION ID
VENDOR ID
I2C Table: Byte Count Register
Byte 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
Name
Control Function
Type
0
1
PWD
-
-
-
-
-
-
-
-
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
RW
RW
RW
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
0
0
0
1
0
0
0
Writing to this register
will configure how
many bytes will be
read back, default is
08 = 8 bytes.
0758A—02/06/07
13
Integrated
Circuit
ICS952623
Systems, Inc.
I2C Table: Overclocking Output Control Register
Byte 9
Bit 7
Bit 6
Bit 5
Bit 4
Pin #
Name
Control Function
Reserved
Type
RW
RW
RW
RW
0
-
-
-
-
1
-
-
-
-
PWD
-
-
-
-
Reserved
Reserved
Reserved
Reserved
0
0
0
0
Reserved
Reserved
Reserved
1: over-clk
See over clocking per bit 1
and 2
00= +15%, 01 = +20%
10= +5%, 11= +10%
-
Over Clocking
R
0
Bit 3
0: normal mode
Over Clocking
Over Clocking
Reserved
-
-
-
Over Clocking
Over Clocking
Reserved
R
R
RW
0
0
0
Bit 2
Bit 1
Bit 0
-
-
I2C Table: VCO Control Select Bit Control Register
Byte 10
Bit 7
Pin #
Name
Control Function
Type
0
1
PWD
Enables prograaming
bytes 11-14
-
Programming ENABLE
RW
DISABLED
ENABLED
0
-
-
-
-
-
-
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RW
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
-
-
-
-
0
0
0
0
0
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
-
RESERVED
RESERVED
RW
-
-
0
Bit 0
I2C Table: VCO Frequency Control Register
Byte 11
Bit 7
Pin #
Name
N Div8
Control Function
N Divider Bit 8
Type
RW
0
-
1
-
PWD
X
-
-
-
-
-
-
-
-
M Div6
M Div5
M Div4
M Div3
M Div2
M Div1
M Div0
RW
RW
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
-
-
-
-
-
-
X
X
X
X
X
X
X
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The decimal
representation of M
Div (6:0) is equal to
reference divider
value. Default at
power up = latch-in or
Byte 0 Rom table.
0758A—02/06/07
14
Integrated
Circuit
ICS952623
Systems, Inc.
I2C Table: VCO Frequency Control Register
Byte 12
Bit 7
Pin #
Name
N Div7
N Div6
N Div5
N Div4
N Div3
N Div2
N Div1
N Div0
Control Function
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
-
-
-
-
-
-
-
-
1
-
-
-
-
-
-
-
-
PWD
X
X
X
X
X
X
X
X
-
-
-
-
-
-
-
-
The decimal
representation of N
Div (8:0) is equal to
VCO divider value.
Default at power up =
latch-in or Byte 0 Rom
table.
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
I2C Table: Spread Spectrum Control Register
Byte 13
Bit 7
Pin #
Name
SSP7
SSP6
SSP5
SSP4
SSP3
SSP2
SSP1
SSP0
Control Function
These Spread
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
-
-
-
-
-
-
-
-
1
-
-
-
-
-
-
-
-
PWD
X
X
X
X
X
X
X
X
-
-
-
-
-
-
-
-
Spectrum bits will
program the spread
pecentage. It is
recommended to use
ICS Spread % table
for spread
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
programming.
I2C Table: Spread Spectrum Control Register
Byte 14
Bit 7
Pin #
Name
Reserved
Reserved
SSP13
SSP12
SSP11
SSP10
SSP9
Control Function
Reserved
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
-
-
-
-
-
-
-
-
1
-
-
-
-
-
-
-
-
PWD
0
0
X
X
X
X
X
X
-
-
-
-
-
-
-
-
Reserved
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
It is recommended to
use ICS Spread %
table for spread
programming.
SSP8
0758A—02/06/07
15
Integrated
Circuit
ICS952623
Systems, Inc.
PCI Stop Functionality
The PCI_STOP# signal is on an active low input controlling PCI and SRC outputs. If PCIF (2:0) and SRC clocks can be set to
be free-running through I2C programming. Outputs set to be free-running will ignore both the PCI_STOP pin and the
PCI_STOP register bit.
PCI_STOP#
CPU
CPU #
SRC
SRC#
3V66
PCIF/PCI USB/DOT
REF
Note
1
0
Normal Normal Normal Normal 66MHz
33MHz
Low
48MHz
48MHz
14.318MHz
14.318MHz
Normal Normal Iref * 6
or Float
Low
66MHz
PCI_STOP# Assertion (transition from '1' to '0')
The clock samples the PCI_STOP# signal on a rising edge of PCIF clock. After detecting the PCI_STOP# assertion low, all
PCI[6:0] and stoppable PCIF[2:0] clocks will latch low on their next high to low transition. After the PCI clocks are latched low,
the SRC clock, (if set to stoppable) will latch high at Iref * 6 (or tristate if Byte 2 Bit 6 = 1) upon its next low to high transition and
the SRC# will latch low as shown below.
Tsu
PCI_STOP#
PCIF[2:0] 33MHz
PCI[6:0] 33MHz
SRC 100MHz
SRC# 100MHz
PCI_STOP# - De-assertion
The de-assertion of the PCI_Stop# signal is to be sampled on the rising edge of the PCIF free running clock domain. After
detecting PCI_Stop# de-assertion, all PCI[6:0], stoppable PCIF[2:0] and stoppable SRC clocks will resume in a glitch free
manner.
Tsu
Tdrive_SRC
PCI_STOP#
PCIF[2:0] 33MHz
PCI[6:0] 33MHz
SRC 100MHz
SRC# 100MHz
0758A—02/06/07
16
Integrated
Circuit
ICS952623
Systems, Inc.
CPU_STOP# Functionality
The CPU_STOP# signal is an active low input controlling the CPU outputs. This signal can be asserted asynchronously.
CPU_STOP#
CPU
CPU #
SRC
SRC#
3V66
PCIF/PCI USB/DOT
REF
Note
1
0
Normal
Normal Normal Normal 66MHz
33MHz
33MHz
48MHz
48MHz
14.318MHz
14.318MHz
Iref * 6 or
Float
Low
Normal Normal 66MHz
CPU_STOP# - Assertion (transition from '1' to '0')
Asserting CPU_STOP# pin stops all CPU outputs that are set to be stoppable after their next transition. When the I2C
CPU_STOP tri-state bit corresponding to the CPU output of interest is programmed to a '0', CPU output will stop CPU_True
= HIGH and CPU_Complement = LOW. When the I2C CPU_Stop tri-state bit corresponding to the CPU output of interest is
programmed to a '1', CPU outputs will be tri-stated.
CPU_STOP#
CPU
CPU#
CPU_STOP# - De-assertion (transition from '0' to '1')
With the de-assertion of CPU_Stop# all stopped CPU outputs will resume without a glitch. The maximum latency from the
de-assertion to active outputs is 2 - 6 CPU clock periods. If the control register tristate bit corresponding to the output of
interest is programmed to '1', then the stopped CPU outputs will be driven High within 10nS of CPU_Stop# de-assertion to
a voltage greater than 200mV.
CPU_Stop#
CPU
CPU#
CPU Internal
Tdrive_CPU_Stop, 10nS >200mV
0758A—02/06/07
17
Integrated
Circuit
ICS952623
Systems, Inc.
PD#, Power Down
PD# is an asynchronous active low input used to shut off all clocks cleanly prior to clock power.
When PD# is asserted low all clocks will be driven low before turning off the VCO. In PD# de-assertion all clocks will start
without glitches.
PWRDWN#
CPU
CPU #
SRC
SRC#
3V66
PCIF/PCI USB/DOT
REF
14.318MHz
Low
Note
1
0
Normal
Normal Normal Normal 66MHz
33MHz
Low
48MHz
Low
Iref * 2 or
Float
Float
Iref * 2
or Float
Float
Low
Notes:
1. Refer to tristate control of CPU and SRC clocks in section 7.7 for tristate timing and operation.
2. Refer to Control Registers in section 16 for CPU_Stop, SRC_Stop and PwrDwn SMBus tristate control addresses.
PD# Assertion
PD# should be sampled low by 2 consecutive CPU# rising edges before stopping clocks. All single ended clocks will be
held low on their next high to low transition.
All differential clocks will be held high on the next high to low transition of the complimentary clock. If the control register
determining to drive mode is set to 'tri-state', the differential pair will be stopped in tri-state mode, undriven.
When the drive mode but corresponding to the CPU or SRC clock of interest is set to '0' the true clock will be driven high at
2 x Iref and the complementary clock will be tristated. If the control register is programmed to '1' both clocks will be tristated.
PWRDWN#
CPU, 133MHz
CPU#, 133MHz
SRC, 100MHz
SRC#, 100MHz
3V66, 66MHz
USB, 48MHz
PCI, 33MHz
REF, 14.31818
0758A—02/06/07
18
Integrated
Circuit
ICS952623
Systems, Inc.
PD# De-assertion
The time from the de-assertion of PD# or until power supply ramps to get stable clocks will be less than 1.8ms. If the drive
mode control bit for PD# tristate is programmed to '1' the stopped differential pair must first be driven high to a minimum of
200mV in less than 300µs of PD# deassertion.
Tstable
<1.8mS
PWRDWN#
CPU, 133MHz
CPU#, 133MHz
SRC, 100MHz
SRC# 100MHz
3V66, 66MHz
USB, 48MHz
PCI, 33MHz
REF, 14.31818
Tdrive_PwrDwn#
<300µS, >200mV
3V66_4/VCH Pin Functionality
The 3V66_4/VCH pin can be configured to be a 66.66MHz modulated output or a non-spread 48MHz output. The default is
3V66 clock. The switching is controlled by Byte 5 Bit 5. If it is set to '1' this pin will output the 48MHz VCH clock. The output
will go low on the falling edge of 3V66 for a minimum of 7.49ns. Then the output will transition to 48MHz on the next rising
edge of DOT_48 clock.
3V66
3V66_4/VCH
DOT_48
7.49nS min
0758A—02/06/07
19
Integrated
Circuit
ICS952623
Systems, Inc.
Differential Clock Tristate
To minimize power consumption, CPU[2:0] clock outputs are individually configurable through SMBus to be driven or
tristated during PwrDwn# and CPU_Stop# mode and the SRC clock is configurable to be driven or tristated during
PCI_Stop# and PwrDwn# mode. Each differential clock (SRC, CPU[2:0]) output can be disabled by setting the
corresponding output's register OE bit to "0" (disable). Disabled outputs are to be tristated regardless of "CPU_Stop",
"SRC_Stop" and "PwrDwn" register bit settings.
Signal
Pin PD#
Pin
CPU_Stop
Pwrdwn
Non-Stoppable
Outputs
Stoppable
Outputs
CPU_Stop# Tristate Bit Tristate Bit
CPU[2:0}
CPU[2:0}
CPU[2:0}
CPU[2:0}
CPU[2:0}
1
1
1
0
0
1
0
X
X
X
X
0
Running
Running
Running
Running
Driven @ Iref x 6
Tristate
0
1
0
X
X
X
X
Driven @ Iref x 2 Driven @ Iref x 2
Tristate Tristate
1
Notes:
1. Each output has four corresponding control register bits, OE, PwrDwn, CPU_Stop and "Free Running"
2. Iref x 6 and Iref x 2 is the output current in the corresponding mode
3. See Control Registers section for bit address
Signal
Pin PD#
Pin
PCI_Stop#
PCI_Stop
Tristate Bit Tristate Bit
Pwrdwn
Non-Stoppable
Output
Stoppable
Output
SRC
SRC
SRC
SRC
SRC
1
1
1
0
0
1
0
X
X
X
X
0
Running
Running
Running
Running
Driven @ Iref x 6
Tristate
0
1
0
X
X
X
X
Driven @ Iref x 2 Driven @ Iref x 2
Tristate Tristate
1
Notes:
1. SRC output has four corresponding control register bits, OE, PwrDwn, SRC_Stop and "Free Running"
2. Iref x 6 and Iref x 2 is the output current in the corresponding mode
3. See Control Registers section for bit address
0758A—02/06/07
20
Integrated
Circuit
ICS952623
Systems, Inc.
CPU Clock Tristate Timing
The following diagrams illustrate CPU clock timing during CPU_Stop# and PwrDwn# modes with CPU_PwrDwn and
CPU_Stop tristate control bits set to driven or tristate in byte 2 of the control register.
CPU_Stop = Driven, CPU_Pwrdwn = Driven
1.8mS
CPU_Stop#
PD#
CPU (Free Running)
CPU# (Free Running)
CPU (Stoppable)
CPU# (Stoppable)
Notes:
1. When both bits (CPU_Stop & CPU_Pwrdown tristate bits) are low, the clock chip will never tristate CPU output clocks
(assuming clock's OE bit is set to "1")
CPU_Stop = Tristate, CPU_Pwrdwn = Driven
1.8mS
CPU_Stop#
PD#
CPU (Free Running)
CPU# (Free Running)
CPU (Stoppable)
CPU# (Stoppable)
Notes:
1. Tristate outputs are pulled low by output termination resistors as shown here.
0758A—02/06/07
21
Integrated
Circuit
ICS952623
Systems, Inc.
CPU_Stop = Driven, CPU_Pwrdwn = Tristate
1.8mS
CPU_Stop#
PWRDWN#
CPU (Free Running)
CPU# (Free Running)
CPU (Stoppable)
CPU# (Stoppable)
Notes:
1. When CPU_Pwrdwn is set to tristate and CPU_Stop is set to driven, the clock chip will tristate outputs only during the
assertion of PWRDWN#. Differential clock behavior during the assertion/de-assertion of CPU_Stop# will be unaffected.
2. In the case that CPU_Stop# is de-asserted during the 1.8mS PWRDWN# de-assertion resume delay, the clock chip can
sample the CPU_Stop# high with the internal rising edges of clock#. This will result in CPU clocks resuming immediately
after the 1.8mS windows expires. This applies to all control register bit changes as well.
3. Tristate outputs are pulled low by output termination resistors as shown here.
CPU_Stop = Tristate, CPU_Pwrdwn = Tristate
1.8mS
CPU_Stop#
PWRDWN#
CPU (Free Running)
CPU# (Free Running)
CPU (Stoppable)
CPU# (Stoppable)
Notes:
1. When CPU_Stop and CPU_Pwrdwn bits are set to tristate, the clock chip will tristate the outputs during the assertion of
CPU_Stop# and PWRDWN#.
2. Tristate outputs are pulled low by output termination resistors as shown here.
0758A—02/06/07
22
Integrated
Circuit
ICS952623
Systems, Inc.
SRC Clock Tristate Timing
The following diagrams illustrate SRC clock timing during PCI_Stop# and PwrDwn# modes with SRC_Pwrdwn and
SRC_Stop tristate control bits set to driven or tristate in byte 2 of the control register.
SRC_Stop = Driven, SRC_Pwrdwn = Driven
1.8mS
PCI_Stop#
PCI (Free Running)
PWRDWN#
CPU (Free Running)
CPU# (Free Running)
SRC (Stoppable)
SRC# (Stoppable)
1 PCI
clock max
Notes:
1. When both bits (SRC_Stop & SRC_Pwrdown tristate bits) are set to driven, the clock chip will never tristate the SRC output
clock (assuming clock's OE bit is set to "1")
SRC_Stop = Tristate, Pwrdwn = Tristate
1.8mS
PCI_Stop#
PCI (Free Running)
PWRDWN#
CPU (Free Running)
CPU# (Free Running)
SRC (Stoppable)
SRC# (Stoppable)
1 PCI
clock max
Notes:
1. When SRC_Stop and SRC_Pwrdwn bits are set to tristate, the clock chip will tristate outputs during the assertion of
PCI_Stop# and PWRDWN#.
2. Tristate outputs are pulled low by output termination resistors as shown here.
0758A—02/06/07
23
Integrated
Circuit
ICS952623
Systems, Inc.
PCI_STOP Asserted
SRC_Stop = Tristate, SRC_Pwrdwn = Tristate
1.8mS
PCI_Stop#
PCI (Free Running)
PWRDWN#
CPU (Free Running)
CPU# (Free Running)
SRC (Stoppable)
SRC# (Stoppable)
Notes:
1. When SRC_Pwrdwn and SRC_Stop are set to tristate, the clock chip will tristate outputs during the assertion of PCI_Stop#
and PWRDWN#.
2. In the case that PCI_Stop# is de-asserted during the 1.8mS PWRDWN# de-assertion resume delay, the clock chip can
sample the PCI_Stop# high with the internal rising edges of CPU clock#. This will result in SRC clocks resuming
immediately after the 1.8mS window expires. This applies to all control register bit changes as well.
3. Tristate outputs are pulled low by output termination resistors as shown here.
0758A—02/06/07
24
Integrated
Circuit
ICS952623
Systems, Inc.
Shared Pin Operation -
Input/Output Pins
Figure 1 shows a means of implementing this function
when a switch or 2 pin header is used. With no jumper is
installed the pin will be pulled high. With the jumper in
place the pin will be pulled low. If programmability is not
necessary, than only a single resistor is necessary. The
programming resistors should be located close to the series
termination resistor to minimize the current loop area. It is
more important to locate the series termination resistor
close to the driver than the programming resistor.
The I/O pins designated by (input/output) serve as dual
signal functions to the device. During initial power-up, they
act as input pins. The logic level (voltage) that is present on
these pins at this time is read and stored into a 5-bit internal
data latch. At the end of Power-On reset, (see AC
characteristics for timing values), the device changes the
mode of operations for these pins to an output function. In
this mode the pins produce the specified buffered clocks to
external loads.
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1) power
supplyortheGND(logic0)voltagepotential. A10Kilohm(10K)
resistor is used to provide both the solid CMOS programming
voltageneededduringthepower-upprogrammingperiodandto
provide an insignificant load on the output clock during the
subsequent operating period.
Via to
VDD
Programming
Header
2K W
Via to Gnd
Device
Pad
8.2K W
Clock trace to load
Series Term. Res.
Fig. 1
0758A—02/06/07
25
Integrated
Circuit
ICS952623
Systems, Inc.
300 mil SSOP
In Millimeters
COMMON DIMENSIONS
In Inches
COMMON DIMENSIONS
c
N
SYMBOL
MIN
2.41
0.20
0.20
0.13
MAX
2.80
0.40
0.34
0.25
MIN
.095
.008
.008
.005
SEE VARIATIONS
.395
.291
0.025 BASIC
.015
.020
SEE VARIATIONS
0°
MAX
.110
.016
.0135
.010
A
A1
b
c
D
E
E1
e
h
L
N
α
L
E1
E
INDEX
AREA
SEE VARIATIONS
10.03
7.40
0.635 BASIC
0.38
0.50
10.68
7.60
.420
.299
1
2
0.64
1.02
.025
.040
α
h x 45°
D
SEE VARIATIONS
0°
8°
8°
VARIATIONS
D mm.
D (inch)
A
N
MIN
18.31
MAX
18.55
MIN
.720
MAX
.730
56
A1
- C -
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
e
SEATING
PLANE
b
.10 (.004) C
Ordering Information
ICS952623yFLFT
Example:
ICS XXXXXX y FLF - T
Designation for tape and reel packaging
RoHS Compliant (Optional)
Package Type
F = SSOP
Revis ion Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
0758A—02/06/07
26
Integrated
Circuit
ICS952623
Systems, Inc.
56-Lead 6.10 mm. Body, 0.50 mm. Pitch TSSOP
c
N
(240 mil)
(20 mil)
In Millimeters
In Inches
SYMBOL
COMMON DIMENSIONS COMMON DIMENSIONS
L
MIN
--
0.05
0.80
0.17
0.09
MAX
1.20
0.15
1.05
0.27
0.20
MIN
--
.002
.032
.007
.0035
MAX
.047
.006
.041
.011
.008
A
A1
A2
b
E1
E
INDEX
AREA
c
D
E
SEE VARIATIONS
8.10 BASIC
SEE VARIATIONS
0.319 BASIC
1
22
a
E1
e
6.00
0.50 BASIC
6.20
.236
0.020 BASIC
.244
D
L
0.45
0.75
.018
.030
N
SEE VARIATIONS
SEE VARIATIONS
0°
--
8°
0.10
0°
--
8°
.004
α
aaa
A
A2
VARIATIONS
A1
D mm.
D (inch)
MIN
.547
- C -
N
MIN
13.90
MAX
14.10
MAX
.555
e
SEATING
PLANE
56
b
Reference Doc.: JEDEC Publication 95, MO-153
aaa
C
10 - 0 0 3 9
Ordering Information
ICS952623yGLFT
Example:
ICS XXXXXX y GLF - T
Designation for tape and reel packaging
RoHS Compliant (Optional)
Package Type
G = TSSOP
Revis ion Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
0758A—02/06/07
27
Integrated
Circuit
ICS952623
Systems, Inc.
Revision History
Rev.
Issue Date Description
1. Added LF Ordering Information.
2/6/2007 2. Going to Release.
Page #
A
26-27
0758A—02/06/07
28
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