954204GLNT [IDT]
Clock Generator, PDSO56;
| 型号： | 954204GLNT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, PDSO56 光电二极管 |
| 文件： | 总16页 (文件大小：199K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
ICS954204
Systems, Inc.
Programmable Timing Control Hub™ for Mobile P4™ Systems
Recommended Application:
CK410M Compliant Main Clock with Integrated LCD Spread
Spectrum Clock.
•
•
•
PCI outputs cycle-cycle jitter < 500ps
+/- 300ppm frequency accuracy on CPU & SRC clocks
+/- 100ppm frequency accuracy on USB clocks
Features/Benefits:
Output Features:
•
Supports tight ppm accuracy clocks for Serial-ATA and
SRC
•
•
2 - 0.7V current-mode differential CPU pairs
5 - 0.7V current-mode differential SRC pair for SATA and
PCI-E
•
Supports programmable spread percentage and
frequency
•
1 - 0.7V current-mode differential CPU/SRC selectable
pair
•
•
•
Uses external 14.318MHz crystal, external crystal load
caps are required for frequency tuning
•
•
•
•
•
•
4 - PCI (33MHz)
2 - PCICLK_F, (33MHz) free-running
1 - USB, 48MHz
1 - DOT, 96MHz, 0.7V current differential pair
1 - REF, 14.318MHz
1 - 0.7V current-mode differential LCD/SRC selectable
pair.
Supports undriven differential CPU, SRC pair in PD#
for power management.
CLKREQ pins to support SRC power management.
Key Specifications:
•
•
CPU outputs cycle-cycle jitter < 85ps
SRC outputs cycle-cycle jitter < 125ps
Pin Configuration
Functionality
CPU
MHz
SRC
MHz
PCI
MHz
REF
MHz
USB
MHz
DOT
MHz
VDDPCI 1
56 PCICLK2
FS_C FS_B FS_A
GND 2
PCICLK3 3
PCICLK4 4
PCICLK5 5
GND 6
55 PCI/SRC_STOP#
54 CPU_STOP#
53 FSLC/TEST_SEL
52 REFOUT
51 GND
50 X1
49 X2
48 VDDREF
47 SDATA
46 SCLK
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
266.67 100.00 33.33
133.33 100.00 33.33
200.00 100.00 33.33
166.67 100.00 33.33
333.33 100.00 33.33
100.00 100.00 33.33
400.00 100.00 33.33
200.00 100.00 33.33
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
48.00
48.00
48.00
48.00
48.00
48.00
48.00
48.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
VDDPCI 7
ITP_EN/PCICLK_F0 8
*SELSRC_LCDCLK#/PCICLK_F1 9
Vtt_PwrGd#/PD 10
VDD48 11
FSLA/USB_48MHz 12
45 GND
FS_C is a three-level input. Please see VIL_FS and VIH_FS specifications in the
Input/Supply/Common Output Parameters Table for correct values. Also refer
to the Test Clarification Table.
1.
2.
GND 13
DOTT_96MHz 14
DOTC_96MHz 15
44 CPUCLKT0
43 CPUCLKC0
42 VDDCPU
41 CPUCLKT1
40 CPUCLKC1
39 IREF
FSLB/TEST_MODE 16
FS_B and FS_A are low-threshold inputs. Please see the VIL_FS and VIH_FS
specifications in the Input/Supply/Common Output Parameters Table for
correct values.
LCDCLK_SST/SRCCLKT0 17
LCDCLK_SSC/SRCCLKC0 18
SRCCLKT1 19
38 GNDA
SRCCLKC1 20
37 VDDA
VDDSRC 21
SRCCLKT2 22
SRCCLKC2 23
36 CPUCLKT2_ITP/SRCCLKT7
35 CPUCLKC2_ITP/SRCCLKC7
34 VDDSRC
SRCCLKT3 24
33 CLKREQA#*
SRCCLKC3 25
32 CLKREQB#*
SRCCLKT4_SATA 26
SRCCLKC4_SATA 27
VDDSRC 28
31 SRCCLKT5
30 SRCCLKC5
29 GND
56-pin TSSOP
*100Kohm Pull-Up Resistor
0933D—03/16/05
Integrated
Circuit
ICS954204
Systems, Inc.
Pin Description
PIN # PIN NAME
PIN TYPE DESCRIPTION
1
VDDPCI
GND
PCICLK3
PCICLK4
PCICLK5
GND
PWR
PWR
OUT
OUT
OUT
PWR
PWR
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clock output.
PCI clock output.
PCI clock output.
Ground pin.
Power supply for PCI clocks, nominal 3.3V
Free running PCI clock not affected by PCI_STOP#.
ITP_EN: latched input to select pin functionality
1 = CPU_ITP pair
2
3
4
5
6
7
VDDPCI
8
ITP_EN/PCICLK_F0
I/O
I/O
IN
0 = SRC pair
Latched input select for LCD_ss/ SRCCLK output frequency:
0 = LCD,
1 = SRCCLK/ 3.3V free-running PCI clock output.
Vtt_PwrGd# is an active low input used to determine when latched inputs
are ready to be sampled. PD is an asynchronous active high input pin used
to put the device into a low power state. The internal clocks, PLLs and the
crystal oscillator are stopped.
9
*SELSRC_LCDCLK#/PCICLK_F1
Vtt_PwrGd#/PD
10
11
12
VDD48
PWR
I/O
Power pin for the 48MHz output.3.3V
3.3V tolerant input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values. / Fixed 48MHz USB clock
output. 3.3V.
FSLA/USB_48MHz
13
14
15
GND
DOTT_96MHz
DOTC_96MHz
PWR
OUT
OUT
Ground pin.
True clock of differential pair for 96.00MHz DOT clock.
Complement clock of differential pair for 96.00MHz DOT clock.
3.3V tolerant input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values. TEST_MODE is a real time
input to select between Hi-Z and REF/N divider mode while in test mode.
Refer to Test Clarification Table.
16
FSLB/TEST_MODE
IN
True clock of LCDCLK_SS output / True clock of SRCCLK differential pair.
Selected by SEL_LCDCLK#
Complementary clock of LCDCLK_SS output / Complementary clock of
SRCCLK differential pair. Selected by SEL_LCDCLK#
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
Supply for SRC clocks, 3.3V nominal
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
True clock of differential SRC/SATA pair.
Complement clock of differential SRC/SATA pair.
Supply for SRC clocks, 3.3V nominal
17
18
LCDCLK_SST/SRCCLKT0
LCDCLK_SSC/SRCCLKC0
OUT
OUT
19
20
21
22
23
24
25
26
27
28
SRCCLKT1
SRCCLKC1
VDDSRC
SRCCLKT2
SRCCLKC2
SRCCLKT3
SRCCLKC3
SRCCLKT4_SATA
SRCCLKC4_SATA
VDDSRC
OUT
OUT
PWR
OUT
OUT
OUT
OUT
OUT
OUT
PWR
0933D—03/16/05
2
Integrated
Circuit
ICS954204
Systems, Inc.
Pin Description (Continued)
PIN # PIN NAME
Type
Pin Description
29
30
31
GND
SRCCLKC5
SRCCLKT5
PWR
OUT
OUT
Ground pin.
Complement clock of differential SRC clock pair.
True clock of differential SRC clock pair.
Output enable for PCI Express (SRC) outputs. SMBus selects which outputs
are controlled.
32
CLKREQB#*
IN
0 = enabled, 1 = tri-stated
Output enable for PCI Express (SRC) outputs. SMBus selects which outputs
are controlled.
0 = enabled, 1 = tri-stated
33
34
35
CLKREQA#*
IN
VDDSRC
PWR
OUT
Supply for SRC clocks, 3.3V nominal
Complementary clock of CPU_ITP/SRC differential pair CPU_ITP/SRC
output. These are current mode outputs. External resistors are required for
voltage bias. Selected by ITP_EN input.
CPUCLKC2_ITP/SRCCLKC7
True clock of CPU_ITP/SRC differential pair CPU_ITP/SRC output. These
are current mode outputs. External resistors are required for voltage bias.
Selected by ITP_EN input.
36
CPUCLKT2_ITP/SRCCLKT7
OUT
37
38
VDDA
GNDA
PWR
PWR
3.3V power for the PLL core.
Ground pin for the PLL core.
This pin establishes the reference current for the differential current-mode
output pairs. This pin requires a fixed precision resistor tied to ground in
order to establish the appropriate current. 475 ohms is the standard value.
39
40
IREF
IN
Complementary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
CPUCLKC1
OUT
True clock of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
41
42
CPUCLKT1
VDDCPU
OUT
PWR
Complementary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
43
CPUCLKC0
OUT
True clock of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
Ground pin.
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 5V tolerant.
Ref, XTAL power supply, nominal 3.3V
Crystal output, Nominally 14.318MHz
Crystal input, Nominally 14.318MHz.
Ground pin.
44
CPUCLKT0
OUT
45
46
47
48
49
50
51
52
GND
PWR
IN
I/O
PWR
OUT
IN
PWR
OUT
SCLK
SDATA
VDDREF
X2
X1
GND
REFOUT
Reference Clock output
3.3V tolerant input for CPU frequency selection. Low voltage threshold
inputs, see input electrical characteristics for Vil_FS and Vih_FS values.
TEST_Sel: 3-level latched input to enable test mode.
Refer to Test Clarification Table
53
FSLC/TEST_SEL
IN
54
CPU_STOP#
IN
Stops all CPUCLK, except those set to be free running clocks
Stops all PCICLKs and SRCCLKs besides the free-running clocks at logic 0
level, when input low
55
56
PCI/SRC_STOP#
PCICLK2
IN
OUT
PCI clock output.
*Pins 32 and 33 have pull-ups.
0933D—03/16/05
3
Integrated
Circuit
ICS954204
Systems, Inc.
General Description
ICS954204 is a CK410M Compliant clock synthesizer. ICS954204 provides a single-chip solution for mobile systems built
with Intel P4-M processors and Intel mobile chipsets. ICS954204 is driven with a 14.318MHz crystal and generates CPU
outputs up to 400MHz. It provides the tight ppm accuracy required by Serial ATA and PCI-Express.
Block Diagram
REFOUT
USB_48MHz
X1
XTAL
OSC.
FIXED PLL
DIVIDER
X2
DOT_96MHz
PCICLK(5:2)
PCICLK_F(1:0)
SRCCLK(5:1)
CPUCLK2_ITP/SRCCLK7
CPUCLK(1:0)
PROG.
SPREAD
MAIN PLL
PCI/SRC_STOP#
CPU_STOP#
LCDCLKSS/SRCCLK0
FSL(C:A)
ITP_EN
CONTROL
LOGIC
TEST_MODE
VTT_PWRGD#/PD
CLKREQ#A/B
SDATA
SCLK
SelSRC/LCDCLK#
IREF
0933D—03/16/05
4
Integrated
Circuit
ICS954204
Systems, Inc.
General SMBus serial interface information for the ICS954204
How to Write:
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address D2(H)
• ICS clock will acknowledge
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2(H)
• ICS clock will acknowledge
• Controller (host) sends the begining byte location = N
• ICS clock will acknowledge
• Controller (host) sends the begining byte
location = N
• ICS clock will acknowledge
• Controller (host) sends the data byte count = X
• ICS clock will acknowledge
• Controller (host) starts sending Byte N through
Byte N + X -1
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address D3(H)
• ICS clock will acknowledge
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
• ICS clock will send the data byte count = X
• ICS clock sends Byte N + X -1
• ICS clock sends Byte 0 through byte X
• Controller (host) will need to acknowledge each byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Write Operation
Index Block Read Operation
Controller (Host)
ICS (Slave/Receiver)
Controller (Host)
ICS (Slave/Receiver)
starT bit
T
T
starT bit
Slave Address D2(H)
Slave Address D2(H)
WR
WR
WRite
WRite
ACK
ACK
ACK
ACK
ACK
ACK
Beginning Byte = N
Data Byte Count = X
Beginning Byte N
Beginning Byte = N
RT
Repeat starT
Slave Address D3(H)
RD
ReaD
ACK
Data Byte Count = X
Beginning Byte N
ACK
ACK
Byte N + X - 1
ACK
P
stoP bit
Byte N + X - 1
N
P
Not acknowledge
stoP bit
0933D—03/16/05
5
Integrated
Circuit
ICS954204
Systems, Inc.
Absolute Max
Symbol Parameter
Min
GND - 0.5
Max
Units
VDD + 0.5V
VDD_A
VDD_In
3.3V Core Supply Voltage
V
VDD + 0.5V
3.3V Logic Input Supply Voltage
V
°C
°C
°C
Ts
Tambient
Tcase
Storage Temperature
Ambient Operating Temp
Case Temperature
-65
0
150
70
115
Input ESD protection
human body model
ESD prot
2000
V
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
SYMBOL
CONDITIONS
3.3 V +/-5%
MIN
2
TYP
MAX
DD + 0.3
UNITS
NOTES
VIH
VIL
IIH
V
V
V
uA
1
1
1
V
SS - 0.3
3.3 V +/-5%
VIN = VDD
0.8
5
-5
VIN = 0 V; Inputs with no pull-up
IIL1
IIL2
-5
uA
uA
1
1
resistors
VIN = 0 V; Inputs with pull-up
Input Low Current
-200
resistors
Low Threshold Input High
Voltage
VIH_FS
V
DD + 0.3
0.35
3.3 V +/-5%
0.7
V
V
1
1
Low Threshold Input Low
Voltage
V
SS - 0.3
3.3 V +/-5%
IDD3.3OP
IDD3.3PD
Full Active, CL = Full load;
all diff pairs driven
all differential pairs tri-stated
VDD = 3.3 V
Operating Supply Current
275
64
5
400
70
12
mA
mA
mA
MHz
nH
pF
pF
pF
Powerdown Current
Input Frequency3
Pin Inductance1
Fi
Lpin
CIN
COUT
CINX
14.31818
3
1
1
1
1
7
5
6
5
Logic Inputs
Output pin capacitance
X1 & X2 pins
Input Capacitance1
From VDD Power-Up or de-
Clk Stabilization1,2
Modulation Frequency
Tdrive_SRC
TSTAB
1.3
1.8
33
10
ms
kHz
ns
1,2
1
assertion of PD# to 1st clock
Triangular Modulation
SRC output enable after
PCI_STOP de-assertion
Differential output enable after
PD# de-assertion
30
1
Tdrive_PD
300
us
1
Tfall_PD
Trise_PD
PD# fall time of
PD# rise time of
5
5
ns
ns
1
2
CPU output enable after
CPU_STOP de-assertion
CPU_STOP fall time of
CPU_STOP rise time of
Tdrive_CPU_STOP
10
ns
1
Tfall_CPU_STOP
Trise_CPU_STOP#
SMBus Voltage
Low-level Output Voltage
Current sinking
SCLK/SDATA
SCLK/SDATA
Clock/Data Fall Time
5
5
5.5
0.4
ns
ns
V
V
mA
ns
1
2
1
1
1
VDD
VOL
IPULLUP
TRI2C
2.7
4
SDATA, SCLK @ IPULLUP
VOL = 0.4 V
(Max VIL - 0.15) to
(Min VIH + 0.15) to
(Max VIL - 0.15)
1000
300
1,3
TFI2C
ns
1,3
1Guaranteed by design, not 100% tested in production.
2See timing diagrams for timing requirements.
3 Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet
0933D—03/16/05
6
Integrated
Circuit
ICS954204
Systems, Inc.
Electrical Characteristics - CPU 0.7V Current Mode Differential Pair
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9Ω, ΙREF = 475Ω
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
850
UNITS
NOTES
1
Current Source Output
Impedance
VO = Vx
Zo
3000
Ω
Statistical measurement on single
ended signal using oscilloscope
math function.
Voltage High
Voltage Low
VHigh
VLow
660
750
0
1,3
1,3
mV
-150
150
Measurement on single ended
signal using absolute value.
Max Voltage
Min Voltage
Crossing Voltage (abs)
Vovs
Vuds
Vcross(abs)
790
0
390
1150
1
1
1
mV
mV
mV
-300
250
550
140
Variation of crossing over all
edges
see Tperiod min-max values
400MHz non-spread
400MHz spread
Crossing Voltage (var)
Long Accuracy
d-Vcross
ppm
50
1
-300
300
ppm
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
1,2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1
2.4993
2.4993
2.9991
2.9991
3.7489
3.7489
4.9985
4.9985
5.9982
5.9982
7.4978
7.4978
9.9970
9.9970
2.5008
2.5133
3.0009
3.016
3.7511
3.77
333.33MHz non-spread
333.33MHz spread
266.66MHz non-spread
266.66MHz spread
200MHz non-spread
200MHz spread
166.66MHz non-spread
166.66MHz spread
133.33MHz non-spread
133.33MHz spread
100.00MHz non-spread
100.00MHz spread
400MHz non-spread
400MHz spread
333.33MHz non-spread
333.33MHz spread
266.66MHz non-spread
266.66MHz spread
200MHz non-spread
200MHz spread
166.66MHz non-spread
166.66MHz spread
133.33MHz non-spread
133.33MHz spread
100.00MHz non-spread
100.00MHz spread
VOL = 0.175V, VOH = 0.525V
5.0015
5.0266
6.0018
6.0320
7.5023
5.4000
10.0030
10.0533
2.5750
2.5983
3.0859
3.1010
3.8361
3.8550
5.0865
5.1116
6.0868
6.1170
7.5873
7.6250
10.0880
10.1383
700
Tperiod
Average period
2.4143
2.9141
3.6639
4.9135
5.9132
7.4128
9.9120
Tabs
Absolute min/max period
tr
tf
d-tr
d-tf
Rise Time
Fall Time
Rise Time Variation
Fall Time Variation
175
175
310
305
20
VOH = 0.525V VOL = 0.175V
700
125
125
ps
ps
ps
1
1
1
15
Measurement from differential
wavefrom
dt3
Duty Cycle
Skew
45
50
55
%
1
CPU(1:0), VT = 50%
CPU2_ITP, VT = 50%
Differential waveform
measurement, CPU(1:0)
Differential waveform
measurement, CPU2_ITP
20
90
100
150
ps
ps
1
1
tsk3
tjcyc-cyc
tjcyc-cyc
Jitter, Cycle to cycle
Jitter, Cycle to cycle
35
45
85
ps
ps
1
1
125
1Guaranteed by design and characterization, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
3IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω.
0933D—03/16/05
7
Integrated
Circuit
ICS954204
Systems, Inc.
Electrical Characteristics - SRC 0.7V Current Mode Differential Pair
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9Ω, ΙREF = 475Ω
PARAMETER
Current Source Output
Impedance
SYMBOL
Zo1
CONDITIONS
MIN
TYP
MAX
UNITS
Notes
1
VO = Vx
3000
Ω
Statistical measurement on single
ended signal using oscilloscope
Measurement on single ended
signal using absolute value.
Voltage High
Voltage Low
Max Voltage
Min Voltage
VHigh
VLow
Vovs
660
-150
750
0
790
0
850
150
1150
1,3
1,3
1
1
1
mV
mV
mV
mV
Vuds
Vcross(abs)
-300
250
Crossing Voltage (abs)
350
550
140
Variation of crossing over all
edges
see Tperiod min-max values
100.00MHz non-spread
100.00MHz spread
100.00MHz non-spread
100.00MHz spread
Crossing Voltage (var)
Long Accuracy
d-Vcross
ppm
12
1
-300
300
10.0030
10.0533
10.1280
10.1783
700
700
125
125
ppm
ns
ns
ns
ns
ps
ps
ps
ps
1,2
2
2
1,2
1,2
1
Tperiod
Average period
9.9970
Tabs
Absolute min/max period
9.8720
tr
tf
d-tr
d-tf
VOL = 0.175V, VOH = 0.525V
VOH = 0.525V, VOL = 0.175V
Rise Time
Fall Time
Rise Time Variation
Fall Time Variation
175
175
308
310
30
1
1
30
1
1
1
1
Measurement from differential
wavefrom
VT = 50%
Measurement from differential
wavefrom
dt3
tsk3
Duty Cycle
Skew
45
50
100
40
55
%
250
125
ps
ps
tjcyc-cyc
Jitter, Cycle to cycle
1Guaranteed by design and characterization, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
3IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω.
Electrical Characteristics - LCD_SS 0.7V Current Mode Differential Pair
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9Ω, ΙREF = 475Ω
PARAMETER
Current Source Output
Impedance
SYMBOL
Zo1
CONDITIONS
MIN
TYP
MAX
UNITS
Notes
1
VO = Vx
3000
Ω
Statistical measurement on single
ended signal using oscilloscope
Measurement on single ended
signal using absolute value.
Voltage High
Voltage Low
Max Voltage
Min Voltage
VHigh
VLow
Vovs
660
-150
750
0
790
0
850
150
1150
1,2
1,2
1
1
1
mV
mV
mV
mV
Vuds
Vcross(abs)
-300
250
Crossing Voltage (abs)
350
550
140
Variation of crossing over all
edges
Crossing Voltage (var)
d-Vcross
12
1
tr
tf
d-tr
d-tf
VOL = 0.175V, VOH = 0.525V
VOH = 0.525V, VOL = 0.175V
Rise Time
Fall Time
Rise Time Variation
Fall Time Variation
175
175
308
310
30
700
700
125
125
ps
ps
ps
ps
1
1
1
1
30
Measurement from differential
wavefrom
dt3
tsk3
Duty Cycle
Skew
45
50
100
40
55
%
ps
ps
1
1
1
VT = 50%
250
125
Measurement from differential
wavefrom
tjcyc-cyc
Jitter, Cycle to cycle
1Guaranteed by design and characterization, not 100% tested in production.
2IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω.
0933D—03/16/05
8
Integrated
Circuit
ICS954204
Systems, Inc.
Electrical Characteristics - PCICLK/PCICLK_F
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
Long Accuracy
SYMBOL
ppm
CONDITIONS
see Tperiod min-max values
33.33MHz output non-spread
33.33MHz output spread
33.33MHz output non-spread
33.33MHz output spread
IOH = -1 mA
MIN
-300
TYP
MAX
300
30.0090
30.1598
30.5090
30.6598
UNITS
Notes
1,2
2
ppm
ns
ns
ns
ns
V
V
mA
mA
mA
mA
V/ns
V/ns
ns
ns
%
ps
ps
Tperiod
Clock period
29.9910
2
1,2
1,2
1
1
1
1
1
1
1
1
1
1
1
1
1
Tabs
Absolute min/max period
29.4910
2.4
VOH
VOL
Output High Voltage
Output Low Voltage
IOL = 1 mA
V OH = 1.0 V
0.55
-33
-33
30
IOH
IOL
Output High Current
Output Low Current
V
OH = 3.135 V
VOL = 1.95 V
OL = 0.4 V
V
38
4
4
2
2
55
500
500
Edge Rate
Edge Rate
Rise Time
Fall Time
Duty Cycle
Skew
Rising edge rate
Falling edge rate
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1
1
0.5
0.5
45
1.37
1.6
tr1
tf1
dt1
50
50
95
tsk1
VT = 1.5 V
tjcyc-cyc
VT = 1.5 V
Jitter
1Guaranteed by design and characterization, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
Electrical Characteristics - 48MHz, USB
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
Long Accuracy
Clock period
SYMBOL
ppm
Tperiod
CONDITIONS
see Tperiod min-max values
48.00000 MHz output
MIN
-100
20.83125
TYP
MAX
100
20.83542
UNITS
ppm
ns
Notes
1,2
2
Tabs
VOH
VOL
Absolute min/max period
Output High Voltage
Output Low Voltage
48.00000 MHz output
IOH = -1 mA
20.4813
2.4
21.1854
0.55
ns
V
V
1,2
1
1
IOL = 1 mA
VOH = 1.0 V
VOH = 3.135 V
VOL = 1.95 V
VOL = 0.4 V
Rising edge rate
-29
29
mA
mA
mA
mA
V/ns
V/ns
ns
1
1
1
1
1
1
1
1
IOH
IOL
Output High Current
Output Low Current
-23
27
2
2
2
2
Edge Rate
Edge Rate
Rise Time
Fall Time
1
1
1
1
1.8
1.6
1.43
1.33
Falling edge rate
tr1
tf1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
ns
dt1
VT = 1.5 V
VT = 1.5 V
Duty Cycle
45
48
55
%
1
1
tjcyc-cyc
Jitter, Cycle to cycle
150
350
ps
1Guaranteed by design and characterization, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
0933D—03/16/05
9
Integrated
Circuit
ICS954204
Systems, Inc.
Electrical Characteristics - DOT, 96MHz 0.7V Current Mode Differential Pair
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9Ω, ΙREF = 475Ω
PARAMETER
Current Source Output
Impedance
SYMBOL
Zo1
CONDITIONS
MIN
TYP
MAX
UNITS
Notes
1
VO = Vx
3000
Ω
Statistical measurement on single
ended signal using oscilloscope
Measurement on single ended
signal using absolute value.
Voltage High
Voltage Low
Max Voltage
Min Voltage
VHigh
VLow
Vovs
660
-150
790
0
810
0
850
150
1150
1,3
1,3
1
1
1
mV
mV
mV
mV
Vuds
Vcross(abs)
-300
250
Crossing Voltage (abs)
400
550
140
Variation of crossing over all
edges
Crossing Voltage (var)
d-Vcross
10
1
see Tperiod min-max values
Long Accuracy
Average period
ppm
Tperiod
Tabs
tr
tf
d-tr
d-tf
-100
10.4135
10.1635
175
100
10.4198
10.6698
700
700
125
ppm
ns
1,2
2
96.00MHz
Absolute min/max period
Rise Time
Fall Time
Rise Time Variation
Fall Time Variation
96.00MHz
VOL = 0.175V, VOH = 0.525V
VOH = 0.525V, VOL = 0.175V
ns
ps
ps
ps
1,2
1
1
1
1
250
240
15
175
30
125
ps
Measurement from differential
wavefrom
Measurement from differential
dt3
Duty Cycle
45
50
90
55
%
1
1
tjcyc-cyc
Jitter, Cycle to cycle
250
ps
wavefrom
1Guaranteed by design and characterization, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
3IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω.
Electrical Characteristics - REF-14.318MHz
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
Long Accuracy
Clock period
Output High Voltage
Output Low Voltage
SYMBOL
ppm
Tperiod
VOH
VOL
CONDITIONS
see Tperiod min-max values
14.318MHz output nominal
IOH = -1 mA
MIN
-300
69.8270
2.4
-33
TYP
MAX
300
69.8550
UNITS
ppm
ns
V
V
Notes
1
1
1
1
IOL = 1 mA
VOH = 1.0 V
0.4
-33
IOH
IOL
Output High Current
Output Low Current
VOH = 3.135 V
mA
1
VOL = 1.95 V
VOL = 0.4 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
30
mA
mA
ns
ns
%
1
1
1
1,2
1,2
1
38
2
2
55
1000
tr1
tf1
dt1
Rise Time
Fall Time
Duty Cycle
Jitter
0.5
0.5
45
1
1
53
750
tjcyc-cyc
VT = 1.5 V
ps
1Guaranteed by design and characterization, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
0933D—03/16/05
10
Integrated
Circuit
ICS954204
Systems, Inc.
SMBus Table: Output Enable Control Register
Byte 0
Pin #
Name
Control Function
Type
0
1
PWD
CPUCLK2_ITP/SRCCLK7
Enable
35, 36
Bit 7
Output Enable
RW
Disable (HiZ)
Enable
1
-
Reserved
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
30, 31
26, 27
24, 25
22, 23
19, 20
17, 18
SRCCLK5 Enable
SRCCLK4/SATA Enable
SRCCLK3 Enable
SRCCLK2 Enable
SRCCLK1 Enable
SRCCLK0 Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
RW
RW
RW
RW
RW
RW
Disable (HiZ)
Disable (HiZ)
Disable (HiZ)
Disable (HiZ)
Disable (HiZ)
Disable (HiZ)
Enable
Enable
Enable
Enable
Enable
Enable
SMBus Table: PLL1 Spread and Output Enable Control Register
Byte 1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Pin #
8
14,15
12
52
Name
PCI_F0 Enable
DOT_96MHz Enable
USB_48MHz Enable
REFOUT Enable
Control Function
Output Enable
Output Enable
Output Enable
Output Enable
Type
RW
RW
RW
RW
0
1
PWD
Disable
Disable (HiZ)
Disable
Enable
Enable
Enable
Enable
1
1
1
1
-
Disable
-
Reserved
41, 40
44, 43
CPU_1 Enable
CPU_0 Enable
Output Enable
Output Enable
RW
RW
Disable (HiZ)
Disable (HiZ)
Enable
Enable
1
1
Spread Spectrum Mode
(CPU, SRC, PCIF, PCI)
-
Bit 0
Spread Control for PLL1
RW
SPREAD OFF SPREAD ON
0
SMBus Table: Output Enable Control Register
Byte 2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
5
4
3
56
Name
Control Function
Output Enable
Output Enable
Output Enable
Output Enable
Reserved
Type
RW
RW
RW
RW
0
1
PWD
PCICLK5
PCICLK4
PCICLK3
PCICLK2
Disable
Disable
Disable
Disable
Enable
Enable
Enable
Enable
1
1
1
1
1
1
1
1
Reserved
Reserved
9
PCI_F1 Enable
Output Enable
RW
Disable
Enable
SMBus Table: SRC Free-Running Control Register
Byte 3
Bit 7
Bit 6
Pin #
35, 36
-
30, 31
26, 27
Name
SRCCLK7
Control Function
Free-Running Control
Reserved
Type
RW
0
1
PWD
Free-Running
Stoppable
0
0
0
0
Bit 5
SRCCLK5
SRCCLK4/SATA
SRCCLK3
RW
RW
RW
RW
RW
Free-Running
Free-Running
Free-Running
Free-Running
Free-Running
Stoppable
Stoppable
Stoppable
Stoppable
Stoppable
Bit 4
24, 25
22, 23
19, 20
17, 18
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
Free-Running Control, not
affected by PCI/SRC_STOP#
SRCCLK2
SRCCLK1
SRCCLK0
RW
Free-Running
Stoppable
0933D—03/16/05
11
Integrated
Circuit
ICS954204
Systems, Inc.
SMBus Table: DOT PD Mode and Output Free-Running Control Register
Byte 4
Bit 7
Pin #
Name
Control Function
Reserved
Type
0
1
PWD
0
DOT_96MHz Power Down
Mode
14, 15
Driven in PD
Reserved
Free-Running Control, not
affected by
RW
Driven
Hi-Z
0
0
Bit 6
Bit 5
Bit 4
9
PCICLK_F1
RW
Free-Running
Stoppable
0
8
PCICLK_F0
CPUCLK_2
CPUCLK_1
RW
RW
RW
Free-Running
Free-Running
Free-Running
Stoppable
Stoppable
Stoppable
0
1
1
Bit 3
Bit 2
Bit 1
Bit 0
PCI/SRC_STOP#
35, 36
40, 41
43, 44
Free-Running Control, not
affected by CPU_STOP#
CPUCLK_0
RW
Free-Running
Stoppable
1
SMBus Table: Output Mode Control Register
Byte 5
Pin #
Name
Control Function
Type
0
1
PWD
SRC(7:0)
PCI/SRC_STOP# Drive
Mode
17-20, 22-27,
30, 31, 35, 36
Driven in PCI/SRC_STOP#
RW
Driven
Hi-Z
0
Bit 7
CPUCLK2_ITP
CPU_STOP# Drive Mode
35, 36
40, 41
43, 44
Driven in CPU_STOP#
Driven in CPU_STOP#
Driven in CPU_STOP#
RW
RW
RW
Driven
Driven
Driven
Hi-Z
Hi-Z
Hi-Z
0
0
0
Bit 6
Bit 5
Bit 4
CPUCLK_1 CPU_STOP#
Drive Mode
CPUCLK_0 CPU_STOP#
Drive Mode
17-20, 22-27,
30, 31, 35, 36
SRC(7:0), 96MHz_SS
PD Drive Mode
Driven in PD
Driven in PD
RW
RW
Driven
Driven
Hi-Z
Hi-Z
0
0
Bit 3
CPUCLK2_ITP PD Drive
Mode
35, 36
Bit 2
Bit 1
Bit 0
40, 41
43, 44
CPUCLK_1 PD Drive Mode
CPUCLK_0 PD Drive Mode
Driven in PD
Driven in PD
RW
RW
Driven
Driven
Hi-Z
Hi-Z
0
0
SMBus Table: Test Mode, FS Readback, and PCI Stop# Control Register
Byte 6
Pin #
Name
Test Mode Selection
(Active only when B6b6 =
1)
Control Function
Type
0
1
PWD
-
Test Mode Selection
RW
Hi-Z
REF/N
0
Bit 7
Normal
Operation
Test Mode
per B6b7
-
Test Clock Mode Entry
Test Mode
RW
0
Bit 6
Reserved
Strength Prog
-
1
Bit 5
Bit 4
52
-
REFOUT STRENGTH
PCI/SRC_STOP#
RW
RW
1X
2X
Outputs
Stopped
Outputs
Active
Stop all PCI and SRC clocks
1
Bit 3
53
16
12
FS_C
FS_B
FS_A
Readback
Readback
Readback
RW
RW
RW
-
-
-
-
-
-
LATCHED
LATCHED
LATCHED
Bit 2
Bit 1
Bit 0
0933D—03/16/05
12
Integrated
Circuit
ICS954204
Systems, Inc.
SMBus Table: Vendor & Revision ID Register
Byte 7
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
Name
RID3
RID2
RID1
RID0
VID3
VID2
VID1
Control Function
Type
R
R
R
R
R
R
R
0
-
-
-
-
-
-
-
1
-
-
-
-
-
-
-
PWD
-
-
-
-
-
-
-
-
x
x
x
x
0
0
0
REVISION ID
VENDOR ID
VID0
R
-
-
1
SMBus Table: Clock Request Control Register
Byte 8
Bit 7
Pin #
-
Name
Control
Type
0
1
PWD
-
Reserved
32
CLKREQB# Control
SRCCLK5 is controlled
RW
Not Controlled
Controlled
1
Bit 6
32
32
-
CLKREQB# Control
CLKREQB# Control
SRCCLK3 is controlled
SRCCLK1 is controlled
Reserved
RW
RW
Not Controlled
Not Controlled
Controlled
Controlled
0
0
-
Bit 5
Bit 4
Bit 3
33
33
33
CLKREQA# Control
CLKREQA# Control
CLKREQA# Control
SRCCLK4 is controlled
SRCCLK2 is controlled
SRCCLK0 is controlled
RW
RW
RW
Not Controlled
Not Controlled
Not Controlled
Controlled
Controlled
Controlled
1
0
0
Bit 2
Bit 1
Bit 0
SMBus Table: LCDCLK_SS Control Register
Byte 9
Bit 7
Bit 6
Bit 5
Bit 4
Pin #
Name
Control
Bit S3
Bit S2
Bit S1
Bit S0
Type
RW
RW
RW
RW
0
1
PWD
LCDCLK_SS3
LCDCLK_SS2
LCDCLK_SS1
LCDCLK_SS0
0
1
1
1
See LCDCLK_SS Frequency
Select Table 2
17,18
Select
LCDCLK_SS/SRCCLK0
9
*SEL SRC_LCDCLK#
R
LCDCLK
SRCCLK0
-
Bit 3
Bit 2
LCDCLK_SS/SRCCLK0
Enable
17, 18
Output Enable
RW
RW
Disable (HiZ)
OFF
Enable
ON
1
LCDCLK_SS Spread
Enable
17, 18
-
Enable SS
Reserved
1
0
Bit 1
Bit 0
Table 2: LCDCLK_SS Frequency Select
Byte9/
Pin 17/18
MHz
S3
S2
S1
S0
Spread % Spread Type
bit1
0
X
0
0
0
0
0
0
0
0
1
X
0
0
0
0
1
1
1
1
0
X
0
0
1
1
0
0
1
1
0
X
0
1
0
1
0
1
0
1
0
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
-
0.8
1
-
1
1
1
1
1
1
1
1
Down
Down
Down
Down
Down
Down
Down
Down
Center
1.25
1.5
1.75
2
2.5
3
1
+/-0.3
1
1
1
1
1
1
0
0
0
0
1
1
1
0
1
100.00
100.00
100.00
+/-0.4
+/-0.5
+/-0.6
Center
Center
Center
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
100.00
100.00
100.00
100.00
+/-0.8
+/-1.0
+/-1.25
+/-1.5
Center
Center
Center
Center
0933D—03/16/05
13
Integrated
Circuit
ICS954204
Systems, Inc.
Table 3. Power-Up CLKREQ# Timing1
Symbol
Parameter
Power Valid to CLKREQ# Output Active
(Fig. 1)
Min
Max
Units
TPVCRL
100
µs
SRC Clock Stablilzation Time from assertion
TSRCSTBL
800
µs
of CLKREQ# (Fig. 1)
1This timing is valid only after system clocks are stable.
Power Stable to Device
VPCIEXDEV
TPVCRL
TSRCSTBL
CLKREQ#
SRCCLK
Figure 1. Power-Up CLKREQ# Timing
Table 4. CLKREQ# Control Timing
Symbol
Parameter
Min
Max
Units
CLKREQ# De-asserted High to SRCCLK
TCRHoff
0
µs
Parked (Fig. 2)
CLKREQ# Asserted LOW to SRCCLK
Active (Fig. 2)
TCRHon
0.4
µs
CLKREQ#
SRCCLK
Figure 2. CLKREQ# Control Timing
CLKREQ# - Assertion (transition from logic“1”to logic“0”)
The impact of asserting the CLKREQ# pin is that the SRCCLK output will become active per the timing found in
Table 4. The clock will become active in a glitch free manner, providing a full cycle at the time it becomes active.
CLKREQ# - De-Assertion (transition from logic“0”to logic“1”)
The impact of asserting the CLKREQ# pin is that the SRCCLK output will become inactive setliing in the Tristate
condition per the timing found in Table 4. The clock will become inactive in a glitch free manner.
0933D—03/16/05
14
Integrated
Circuit
ICS954204
Systems, Inc.
Table 5: PCI_STOP# Functionality
PCI_STOP#
CPU
CPU#
Normal
Normal
SRC
SRC#
Normal
Low
PCIF/PCI
33MHz
Low
DOT
DOT#
Normal
Normal
USB
REF
0
1
Normal
Normal
Normal
Iref*6 or Float
Normal
Normal
48MHz
48MHz
14.318MHz
14.318MHz
Table 6: PD Functionality
PD
CPU
CPU#
Normal
Float
SRC
SRC#
Normal
Float
PCIF/PCI
33MHz
Low
DOT
DOT#
Low
USB
48MHz
Low
REF
14.318MHz
Low
0
Normal
Iref*2 or Float
Normal
Iref*2 or Float
Normal
Iref*2 or Float
1
Float
Table 7: Tristate CPU Clock Control Truth Table
CPU_STOP
Tristate BIT
NON-STOP
OUTPUTS
PD
CPU_STOP#
PD Tristate BIT
Signal
STOPPABLE OUTPUTS
10
0
54
1
B5b[6, 5, 4]
B5b[2,1,0]
CPU[2:0]
CPU[2:0]
CPU[2:0]
CPU[2:0]
X
0
X
X
X
1
Running
Running
Running
Running
Driven @ IREF X6
Tristate
0
0
0
0
1
Driven @ IREF X2
Tristate
Driven @ IREF X2
1
X
X
CPU[2:0]
1
X
X
0
Tristate
Table 8: Tristate SRC Clock Control Truth Table
PCI/SRC_STOP
Tristate BIT
NON-STOP
OUTPUTS
PD
PCI/SRC_STOP#
PD Tristate BIT
Signal
STOPPABLE OUTPUTS
10
0
55
1
B5b7
B5b3
SRC
SRC
SRC
SRC
SRC
X
0
X
X
X
1
Running
Running
Running
Driven @ IREF X6
Tristate
0
0
0
0
1
Running
Driven @ IREF X2
Driven @ IREF X2
1
X
X
X
X
1
0
Tristate
Tristate
Table 9: Tristate DOT Clock Control Truth Table
PD
10
0
PD Tristate BIT
Signal
STOPPABLE OUTPUTS
B4b6
DOT_96
DOT_96
DOT_96
X
1
0
Running
Driven @ IREF X2
Tristate
1
1
Table10: CLKREQ# Clock Control Truth Table
CLKREQA#
CLKREQB#
PD
PCI/SRC_STOP#
Signal
SELECTED OUTPUTS
10
0
55
1
33, 32
SRC
SRC
SRC
SRC
SRC
0
1
0
1
X
Running
Tristate
0
1
0
0
Tristate
0
0
Stopped per B5b7
Stopped per B5b3
1
X
0933D—03/16/05
15
Integrated
Circuit
ICS954204
Systems, Inc.
c
56-Lead 6.10 mm. Body, 0.50 mm. Pitch TSSOP
N
(240 mil)
(20 mil)
In Millimeters
COMMON DIMENSIONS COMMON DIMENSIONS
In Inches
L
SYMBOL
MIN
--
0.05
0.80
0.17
0.09
MAX
1.20
0.15
1.05
0.27
0.20
MIN
--
.002
.032
.007
.0035
MAX
.047
.006
.041
.011
.008
E1
E
A
A1
A2
b
INDEX
AREA
c
1
2
D
E
SEE VARIATIONS
8.10 BASIC
SEE VARIATIONS
0.319 BASIC
a
D
E1
e
6.00
0.50 BASIC
6.20
.236
0.020 BASIC
.244
L
0.45
0.75
.018
.030
N
α
SEE VARIATIONS
SEE VARIATIONS
A
A2
0°
--
8°
0.10
0°
--
8°
.004
A1
aaa
- C -
VARIATIONS
e
SEATING
PLANE
D mm.
D (inch)
b
N
MIN
13.90
MAX
14.10
MIN
.547
MAX
.555
aaa
C
56
Reference Doc.: JEDEC Publication 95, MO-153
10-0039
Ordering Information
ICS954204yGLFT
Example:
ICS XXXX y G Lx T
Designation for tape and reel packaging
Lead Option(optional)
LF = Lead Free
LN = Lead Free Annealed
Package Type
G = TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
0933D—03/16/05
16
相关型号：
954204YGLFT
Processor Specific Clock Generator, 400MHz, CMOS, PDSO56, 0.240 INCH, 0.020 INCH PITCH, LEAD FREE, MO-153, TSSOP-56
IDT
954204YGLNT
Processor Specific Clock Generator, 400MHz, CMOS, PDSO56, 0.240 INCH, 0.020 INCH PITCH, LEAD FREE, MO-153, TSSOP-56
IDT
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