9DB1904BKLFT中文资料_数据手册_规格书

Datasheet

19OutputDifferentialBufferforPCIeGen2andQPI

9DB1904B

Description

Features/Benefits

The 9DB1904 is electrically compatible to the Intel DB1900GS

Differential Buffer Specification.This buffer provides 19 output clocks

for PCI-Express Gen2 or Intel QPI 6.4GT/s applications. A differential

clock from a CK410B+ main clock generator, such as the

ICS932S421 drives the 9DB1904. The 9DB1904 can provide

outputs up to 400MHz in Bypass Mode.

•

Power up default is all outputs in 1:1 mode/No SMBus

programming

•

Spread spectrum compatible/EMI reductions

Supports output frequencies up to 400 MHz in bypass

mode/flexible fanout buffer

•

8 Selectable SMBus addresses/no SMBus

segmentationrequired

SMBus address determines PLL or Bypass mode/pin

savings

DedicatedVDDA and CKPWRGD_PD# pins/easy board

design

Recommended Application

19 Output Differential Buffer for PCIe Gen2 and QPI

Key Specifications

•

DIF output cycle-to-cycle jitter < 50ps

DIF output-to-output skew < 150ps across all outputs

Functionality at Power Up (PLL Mode)

Power Down Functionality

INPUTS

CKPWRGD_ CLK_IN/

OUTPUTS

CLK_IN

DIF_(18:0)

MHz

CLK_IN

100M_133M#

MHz

PLL State

PD#

1

0

CLK_IN#

Running

X

DIF/DIF#

Running

Hi-Z

1

0

100MHz

133MHz

ON

OFF

Pin Configuration

72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55

IREF

GNDA

VDDA

1

2

3

4

5

6

7

8

9

54 OE14#

53 DIF_13#

52 DIF_13

51 OE13#

50 DIF_12#

49 DIF_12

48 OE12#

47 VDD

HIGH_BW#

100M_133M#_LV

DIF_0

DIF_0#

DIF_1

DIF_1#

GND 10

VDD 11

DIF_2 12

DIF_2# 13

DIF_3 14

DIF_3# 15

DIF_4 16

46 GND

9DB1904BKLF

45 DIF_11#

44 DIF_11

43 OE11#

42 DIF_10#

41 DIF_10

40 OE10#

39 DIF_9#

38 DIF_9

DIF_4# 17

OE_01234# 18

37 OE9#

19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

IDT^®19 Output Differential Buffer for PCIe Gen2 and QPI

1607C —04/19/11

1

9DB1904B

19 Output Differential Buffer for PCIe Gen2 and QPI

Pin Description

PIN #

PIN NAME

PIN TYPE

DESCRIPTION

This pin establishes the reference for the differential current-mode output

pairs. It requires a fixed precision resistor to ground. 475ohm is the standard

value for 100ohm differential impedance. Other impedances require different

values. See data sheet.

1

IREF

OUT

2

3

GNDA

VDDA

PWR

Ground pin for the PLL core.

3.3V power for the PLL core.

3.3V input for selecting PLL Band Width

0 = High, 1= Low

Low Threshold Input to select operating frequency.

See Functionality Table for Definition

0.7V differential true clock output

0.7V differential Complementary clock output

0.7V differential true clock output

0.7V differential Complementary clock output

Ground pin.

Power supply, nominal 3.3V

0.7V differential true clock output

0.7V differential Complementary clock output

0.7V differential true clock output

0.7V differential Complementary clock output

0.7V differential true clock output

0.7V differential Complementary clock output

Active low input for enabling DIF pairs 0, 1, 2, 3 and 4.

1 =disable outputs, 0 = enable outputs

Clock pin of SMBUS circuitry, 5V tolerant

Data pin of SMBUS circuitry, 5V tolerant

Active low input for enabling DIF pair 5.

1 =disable outputs, 0 = enable outputs

0.7V differential true clock output

0.7V differential Complementary clock output

Active low input for enabling DIF pair 6.

1 =disable outputs, 0 = enable outputs

0.7V differential true clock output

4

5

HIGH_BW#

IN

100M_133M#_LV

6

7

8

DIF_0

DIF_0#

DIF_1

DIF_1#

GND

OUT

PWR

OUT

9

10

11

12

13

14

15

16

17

VDD

DIF_2

DIF_2#

DIF_3

DIF_3#

DIF_4

DIF_4#

18

OE_01234#

IN

19

20

SMBCLK

SMBDAT

IN

I/O

21

OE5#

IN

22

23

DIF_5

DIF_5#

OUT

24

OE6#

IN

25

26

27

28

DIF_6

DIF_6#

VDD

OUT

PWR

0.7V differential Complementary clock output

Power supply, nominal 3.3V

Ground pin.

GND

Active low input for enabling DIF pair 7.

1 =disable outputs, 0 = enable outputs

0.7V differential true clock output

0.7V differential Complementary clock output

Active low input for enabling DIF pair 8.

1 =disable outputs, 0 = enable outputs

0.7V differential true clock output

0.7V differential Complementary clock output

SMBus address bit 0 (LSB)

SMBus address bit 1

29

OE7#

IN

30

31

DIF_7

DIF_7#

OUT

32

OE8#

IN

33

34

35

36

DIF_8

OUT

IN

DIF_8#

SMB_A0

SMB_A1

IN

IDT^®19 Output Differential Buffer for PCIe Gen2 and QPI

1607C—04/19/11

2

9DB1904B

19 Output Differential Buffer for PCIe Gen2 and QPI

Pin Description (continued)

PIN #

PIN NAME

PIN TYPE

DESCRIPTION

Active low input for enabling DIF pair 9.

1 =disable outputs, 0 = enable outputs

0.7V differential true clock output

0.7V differential Complementary clock output

Active low input for enabling DIF pair 10.

1 =disable outputs, 0 = enable outputs

0.7V differential true clock output

0.7V differential Complementary clock output

Active low input for enabling DIF pair 11.

1 =disable outputs, 0 = enable outputs

0.7V differential true clock output

37

OE9#

IN

38

39

DIF_9

DIF_9#

OUT

40

OE10#

IN

41

42

DIF_10

DIF_10#

OUT

43

OE11#

IN

44

45

46

47

DIF_11

DIF_11#

GND

OUT

PWR

0.7V differential Complementary clock output

Ground pin.

Power supply, nominal 3.3V

VDD

Active low input for enabling DIF pair 12.

1 =disable outputs, 0 = enable outputs

0.7V differential true clock output

0.7V differential Complementary clock output

Active low input for enabling DIF pair 13.

1 =disable outputs, 0 = enable outputs

0.7V differential true clock output

0.7V differential Complementary clock output

Active low input for enabling DIF pair 14.

1 =disable outputs, 0 = enable outputs

0.7V differential true clock output

0.7V differential Complementary clock output

3.3V Input notifies device to sample latched inputs and start up on first high

assertion, or exit Power Down Mode on subsequent assertions. Low enters

Power Down Mode.

48

OE12#

IN

49

50

DIF_12

DIF_12#

OUT

51

OE13#

IN

52

53

DIF_13

DIF_13#

OUT

54

OE14#

IN

55

56

DIF_14

DIF_14#

OUT

57

CKPWRGD_PD#

IN

58

59

DIF_15

DIF_15#

OUT

0.7V differential true clock output

0.7V differential Complementary clock output

Active low input for enabling DIF pairs 15 and 16.

1 =disable outputs, 0 = enable outputs

0.7V differential true clock output

0.7V differential Complementary clock output

Power supply, nominal 3.3V

Ground pin.

0.7V differential true clock output

0.7V differential Complementary clock output

0.7V differential true clock output

0.7V differential Complementary clock output

Active low input for enabling DIF pairs 17 and 18.

1 =disable outputs, 0 = enable outputs

True Input for differential reference clock.

Complementary Input for differential reference clock.

SMBus address bit 2. When Low, the part operates as a fanout buffer with the

PLL bypassed. When High, the part operates as a zero-delay buffer (ZDB) with

the PLL operating.

60

OE15_16#

IN

61

62

63

64

65

66

67

68

DIF_ 16

DIF_16#

VDD

OUT

PWR

OUT

GND

DIF_17

DIF_17#

DIF_18

DIF_18#

69

OE17_18#

IN

70

71

CLK_IN

CLK_IN#

IN

72

SMB_A2_PLLBYP#

IN

0 = fanout mode (PLL bypassed), 1 = ZDB mode (PLL used)

IDT^®19 Output Differential Buffer for PCIe Gen2 and QPI

1607C—04/19/11

3

9DB1904B

19 Output Differential Buffer for PCIe Gen2 and QPI

Functional Block Diagram

OE(17_18)#

OE(15_16)#

13

OE(14:5)#,

OE_01234#

PLL

(SS Compatible)

CLK_IN

CLK_IN#

19

DIF(18:0)

HIGH_BW#

100M_133M#_LV

CKPWRGD_PD#

SMB_A0

SMB_A1

Logic

SMB_A2_PLLBYP#

SMBDAT

SMBCLK

IREF

Power Groups

Pin Number

Description

VDD

GND

3

2

PLL, Analog

DIF clocks

11,27,47,63 10,28,46,64

9DB1904 Frequency Selects for PLL Mode

Byte 9,

bit 2

100M_133M#_LV

Byte9,

bit 1

FSB

Byte 9,

bit 0

FSA

CLK_IN

MHz

DIF Outputs

MHz

Notes

1

2

1

0

1

100.00

133.33

100.00

133.33

Notes:FS_A_410 = 1

1. Powerup Default for 100M_133M# = 1

2. Powerup Default for 100M_133M# = 0

IDT^®19 Output Differential Buffer for PCIe Gen2 and QPI

1607C—04/19/11

4

9DB1904B

19 Output Differential Buffer for PCIe Gen2 and QPI

Electrical Characteristics - Absolute Maximum Ratings

PARAMETER

SYMBOL

CONDITIONS

UNITS NOTES

MIN

TYP

MAX

4.6

3.3V Core Supply Voltage

3.3V Logic Supply Voltage

Input Low Voltage

VDDA

VDD

V_IL

V

1,2

1

GND-0.5

Input High Voltage

V_IH

Except for SMBus interface

SMBus clock and data pins

V_DD+0.5V

5.5V

V

^°C

°C

V

1

V_IHSMB

1

Storage Temperature

Junction Temperature

Input ESD protection

Ts

Tj

ESD prot

-65

150

125

Human Body Model

2000

¹Guaranteed by design and characterization, not 100% tested in production.

²Operation under these conditions is neither implied nor guaranteed.

Electrical Characteristics - Clock Input Parameters

TA = T_COM;Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions

PARAMETER

SYMBOL

CONDITIONS

MIN

600

TYP

800

MAX

1150

UNITS NOTES

Differential inputs

(single-ended measurement)

Differential inputs

Input High Voltage - DIF_IN

V_IHDIF

mV

1

Input Low Voltage - DIF_IN

V_ILDIF

V_COM

V

_SS- 300

300

0

300

(single-ended measurement)

Input Common Mode

Voltage - DIF_IN

Common Mode Input Voltage

1000

Input Amplitude - DIF_IN

Input Slew Rate - DIF_IN

Input Leakage Current

V_SWING

dv/dt

I_IN

Peak to Peak value

Measured differentially

V_IN= V_{DD ,}V_IN= GND

300

0.4

-5

1450

8

5

mV

V/ns

uA

1

1,2

1

Input Duty Cycle

d_tin

Measurement from differential wavefrom

Differential Measurement

45

0

55

125

%

1, 3

1

Input Jitter - Cycle to Cycle

J_DIFIn

ps

¹Guaranteed by design and characterization, not 100% tested in production.

²Slew rate measured through +/-75mV window centered around differential zero

³Input duty cycle will directly impact output duty cycle in bypass mode. It has no impact in PLL mode.

Electrical Characteristics - Current Consumption

TA = T_COM;Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS NOTES

I_DD3.3OP

I_DD3.3AOP

I_DD3.3PD

I_DD3.3APD

VDD, All outputs active @100MHz

mA

1

425

35

20

450

45

25

Operating Supply Current

VDDA, All outputs active @100MHz

VDD

Powerdown Current

VDDA

12

15

1

Ω

Guaranteed by design and characterization, not 100% tested in production. Zo = 100

IDT^®19 Output Differential Buffer for PCIe Gen2 and QPI

1607C—04/19/11

5

9DB1904B

19 Output Differential Buffer for PCIe Gen2 and QPI

Electrical Characteristics - Input/Supply/Common Parameters

TA = T_COM;Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions

PARAMETER

SYMBOL

CONDITIONS

MIN

0

TYP

MAX

70

UNITS NOTES

Ambient Operating

Temperature

T_COM

Commmercial range

°C

V

1

Single-ended inputs, except SMBus, low

threshold and tri-level inputs

Single-ended inputs, except SMBus, low

threshold and tri-level inputs

Input High Voltage

Input Low Voltage

V_IH

V_IL

2

V

_DD+ 0.3

0.8

GND - 0.3

0.7

V

Low Threshold Input-

High Voltage

Low Threshold Input-

Low Voltage

V_{IH_FS}

3.3 V +/-5%, Applies to 100M_133M#_LV pin

V_DD+ 0.3

V

V_{IL_FS}

I_IN

V_SS- 0.3

-5

0.35

5

V

1

Single-ended inputs, V_IN= GND, V_IN= VDD

Single-ended inputs

uA

Input Current

V

_IN= 0 V; Inputs with internal pull-up resistors

I_INP

-200

200

uA

1

V

_IN= VDD; Inputs with internal pull-down resistors

F_ibyp

F_ipll

V_DD= 3.3 V, Bypass mode

V_DD= 3.3 V, 100MHz PLL mode

V_DD= 3.3 V, 133.33MHz PLL mode

33

90

400

110

147

7

MHz

nH

2

Input Frequency

Pin Inductance

Capacitance

100.00

133.33

F_ipll

120

2

L_pin

1

C_IN

Logic Inputs, except DIF_IN

DIF_IN differential clock inputs

1.5

5

pF

1

C_{INDIF_IN}

2.7

pF

1,4

C_OUT

Output pin capacitance

6

pF

1

From V_DDPower-Up and after input clock

stabilization or de-assertion of PD# to 1st clock

Clk Stabilization

T_STAB

1.8

ms

1,2

Input SS Modulation

Frequency

Allowable Frequency

(Triangular Modulation)

f_MODIN

30

4

33

kHz

1

DIF start after OE# assertion

DIF stop after OE# deassertion

DIF output enable after

OE# Latency

Tdrive_PD#

t_LATOE#

t_DRVPD

12

clocks

us

1,3

300

PD# de-assertion

Tfall

t_F

Fall time of control inputs

5

ns

V

1,2

1

Trise

t_R

Rise time of control inputs

SMBus Input Low Voltage

SMBus Input High Voltage

V_ILSMB

V_IHSMB

0.8

2.1

V_DDSMB

0.4

V

1

SMBus Output Low Voltage V_OLSMB

@ I_PULLUP

@ V_OL

V

1

SMBus Sink Current

Nominal Bus Voltage

SCLK/SDATA Rise Time

I_PULLUP

V_DDSMB

t_RSMB

4

mA

V

1

3V to 5V +/- 10%

2.7

5.5

1000

300

1

(Max VIL - 0.15) to (Min VIH + 0.15)

(Min VIH + 0.15) to (Max VIL - 0.15)

ns

1

SCLK/SDATA Fall Time

SMBus Operating

Frequency

t_FSMB

1

f_MAXSMB

Maximum SMBus operating frequency

100

kHz

1,5

¹Guaranteed by design and characterization, not 100% tested in production.

²Control input must be monotonic from 20% to 80% of input swing.

³Time from deassertion until outputs are >200 mV

⁴DIF_IN input

⁵The differential input clock must be running for the SMBus to be active

IDT^®19 Output Differential Buffer for PCIe Gen2 and QPI

1607C—04/19/11

6

9DB1904B

19 Output Differential Buffer for PCIe Gen2 and QPI

Electrical Characteristics - DIF 0.7V Current Mode Differential Outputs

TA = T_COM;Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions

PARAMETER

SYMBOL

Trf

CONDITIONS

MIN

1

TYP MAX UNITS NOTES

V/ns

%

Slew rate

Slew rate matching

Scope averaging on

Slew rate matching, Scope averaging on

2

12.6

4

20

1, 2, 3

1, 2, 4

Δ

Trf

Statistical measurement on single-ended signal

using oscilloscope math function. (Scope

averaging on)

Voltage High

Voltage Low

VHigh

VLow

660

797

39

850

1

mV

-150

150

Max Voltage

Min Voltage

Vswing

Crossing Voltage (abs)

Crossing Voltage (var)

Vmax

Vmin

Vswing

Measurement on single ended signal using

absolute value. (Scope averaging off)

Scope averaging off

857

7

1510

378

57

1150

1

1, 2

1, 5

1, 6

mV

-300

300

250

mV

Vcross_abs

Scope averaging off

550

140

Δ

-Vcross

1

Ω

Guaranteed by design and characterization, not 100% tested in production. IREF = VDD/(3xR_R). For R_R= 475 (1%), I_REF= 2.32mA.

Ω Ω

_OH= 6 x I_REFand V_OH= 0.7V @ Z_O=50 (100 differential impedance).

I

²Measured from differential waveform

³Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around

differential 0V.

⁴Matching applies to rising edge rate of Clock / falling edge rate of Clock#. It is measured in a +/-75mV window centered on the

average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the

oscilloscope uses for the edge rate calculations.

⁵Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising

edge (i.e. Clock rising and Clock# falling).

⁶The total variation of all Vcross measurements in any particular system. Note that this is a subset of V_cross_min/max (V_cross

absolute) allowed. The intent is to limit Vcross induced modulation by setting V_cross_delta to be smaller than V_cross absolute.

9DBxxx Differential Test Loads

Rs

Differential Zo

2pF

Rp

Rs

HSCL Output

Buffer

Differential Output Termination Table

Ω

Rs ( )

Ω

Rp ( )

DIF Zo ( ) Iref ( )

100

85

475

412

33

27

50

43.2

IDT^®19 Output Differential Buffer for PCIe Gen2 and QPI

1607C—04/19/11

7

9DB1904B

19 Output Differential Buffer for PCIe Gen2 and QPI

Electrical Characteristics - Output Duty Cycle, Jitter, Skew and PLL Characterisitics

TA = T_COM;Supply Voltage VDD = 3.3 V +/-5%

PARAMETER

PLL Bandwidth

SYMBOL

BW

CONDITIONS

MIN

TYP

MAX

UNITS NOTES

-3dB point in High BW Mode

-3dB point in Low BW Mode

Peak Pass band Gain

2

0.7

3

1

1.4

4

1.4

2

MHz

dB

1

PLL Jitter Peaking

Duty Cycle

t_JPEAK

t_DC

Measured differentially, PLL Mode

Measured differentially, Bypass Mode

@100MHz

45

-2

49.5

55

%

1,2

Duty Cycle Distortion

t_DCD

t_pdBYP

t_pdPLL

1

2

%

1,2,5

Bypass Mode, nominal value @ 25°C, 3.3V,

V_T= 50%

PLL Mode, nominal value @ 25°C, 3.3V,

V_T= 50%

2500

100

3700

300

4500

500

ps

1,2,4

1,2,3

Skew, Input to Output

Input-to-Output Skew Variation in Bypass

mode

(over specified voltage / temperature operating

ranges)

1,2,4,6,7,

8,9,13

Δ

DIF_IN, DIF [x:0]

t_{pd_BYP}

|500|

|600|

ps

Input-to-Output Skew Variation in PLL mode

t_{pd_PLL}(over specified voltage / temperature operating

ranges)

1,2,3,6,7,

8,9,13

Δ

|250|

|350|

ps

DIF[X:0]

t_JPH

t_SSTERROR

t_sk3

Differential Phase Jitter (RMS Value)

Differential Spread Spectrum Tracking Error

(peak to peak)

2

10

80

ps

1,7,10

1,7,12

40

Skew, Output to Output

Jitter, Cycle to cycle

V_T= 50%

PLL mode

Additive Jitter in Bypass Mode

100

40

25

150

50

ps

1

1,2

t_jcyc-cyc

¹Guaranteed by design and characterization, not 100% tested in production. C_LOAD= 2pF

²Measured from differential cross-point to differential cross-point

³PLL mode Input-to-Output skew is measured at the first output edge following the corresponding input.

⁴All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created by it.

⁵Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.

⁶VT = 50% of Vout

⁷This parameter is deterministic for a given device

⁸Measured with scope averaging on to find mean value.

⁹Long-term variation from nominal of input-to-output skew over temperature and voltage for a single device.

¹⁰This parameter is measured at the outputs of two separate 9DB1904 devices driven by a single main clock. The 9DB1904's must

be set to high bandwidth. Differential phase jitter is the accumulation of the phase jitter not shared by the outputs (eg. not including

the affects of spread spectrum). Target ranges of consideration are agents with BW of 1-22MHz and 11-33MHz.

¹¹t is the period of the input clock

¹²Differential spread spectrum tracking error is the difference in spread spectrum tracking between two 9DB1904 devices This

parameter is measured at the outputs of two separate 9DB1904 devices driven by a single main clock in Spread Spectrum mode.

The 9DB1904's must be set to high bandwidth. The spread spectrum characteristics are: maximum of 0.5%, 30-33KHz modulation

frequency, linear profile.

¹³This parameter is an absolute value. It is not a double-sided figure.

IDT^®19 Output Differential Buffer for PCIe Gen2 and QPI

1607C—04/19/11

8

9DB1904B

19 Output Differential Buffer for PCIe Gen2 and QPI

Electrical Characteristics - Phase Jitter Parameters

TA = T_COM;Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions

PARAMETER

SYMBOL

t_jphPCIeG1

CONDITIONS

PCIe Gen 1

PCIe Gen 2 Lo Band

MIN

TYP

35

MAX

86

UNITS

ps (p-p)

ps

(rms)

ps

(rms)

ps

(rms)

Notes

1,2,3

1.2

2.5

3

1,2

10kHz < f < 1.5MHz

t_jphPCIeG2

Phase Jitter, PLL Mode

PCIe Gen 2 High Band

1.5MHz < f < Nyquist (50MHz)

QPI & SMI

3.1

t_{jphQPI_SMI}

t_jphPCIeG1

0.30

3

0.5

10

1,5

(100MHz or 133MHz, 4.8Gb/s, 6.4Gb/s 12UI)

PCIe Gen 1

ps (p-p)

1,2,3

1,2,6

PCIe Gen 2 Lo Band

10kHz < f < 1.5MHz

PCIe Gen 2 High Band

ps

(rms)

ps

(rms)

ps

0.01

0.3

AdditivePhase Jitter,

t_jphPCIeG2

Bypass mode

0.8

1.3

0.3

1,2,6

1,5,6

1.5MHz < f < Nyquist (50MHz)

QPI & SMI

(100MHz or 133MHz, 4.8Gb/s, 6.4Gb/s 12UI)

t_{jphQPI_SMI}

0.12

(rms)

¹Applies to all outputs.

²See http://www.pcisig.com for complete specs

³Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.

⁴Subject to final radification by PCI SIG.

⁵Calculated from Intel-supplied Clock Jitter Tool v 1.6.3

⁶For RMS figures, additive jitter is calculated by solving the following equation: (Additive jitter)^2 = (total jittter)^2 - (input jitter)^2

Clock Periods - Differential Outputs with Spread Spectrum Disabled

Measurement Window

1 Clock

1us

-SSC

0.1s

- ppm

0.1s

+ ppm

Long-Term Short-Term

Average

Max

1us

+SSC

1 Clock

Center

Freq.

MHz

SSC OFF

-c2c jitter

AbsPer

Min

0 ppm

Period

Nominal

+c2c jitter Units Notes

AbsPer

Max

Short-Term Long-Term

Average

Min

Average

Min

Average

Max

100.00

133.33

9.94900

7.44925

9.99900

7.49925

10.00000

7.50000

10.00100

7.50075

10.05100

7.55075

ns

1,2

DIF

Clock Periods - Differential Outputs with Spread Spectrum Enabled

Measurement Window

1 Clock

1us

-SSC

0.1s

- ppm

0.1s

+ ppm

Long-Term Short-Term

Average

Max

1us

+SSC

1 Clock

Center

Freq.

MHz

SSC ON

-c2c jitter

AbsPer

Min

0 ppm

Period

Nominal

+c2c jitter Units Notes

AbsPer

Max

Short-Term Long-Term

Average

Min

Average

Min

Average

Max

99.75

133.00

9.94906

7.44930

9.99906

7.49930

10.02406

7.51805

10.02506

7.51880

10.02607

7.51955

10.05107

7.53830

10.10107

7.58830

ns

1,2

DIF

¹Guaranteed by design and characterization, not 100% tested in production.

²All Long Term Accuracy specifications are guaranteed with the assumption that the input clock complies with CK410B+/CK420BQ

accuracy requirements. The 9DB1904 itself does not contribute to ppm error.

IDT^®19 Output Differential Buffer for PCIe Gen2 and QPI

1607C—04/19/11

9

9DB1904B

19 Output Differential Buffer for PCIe Gen2 and QPI

DIF Reference Clock

Common Recommendations for Differential Routing

L1 length, route as non-coupled 50ohm trace

L2 length, route as non-coupled 50ohm trace

L3 length, route as non-coupled 50ohm trace

Dimension or Value

0.5 max

0.2 max

33

Unit Figure

inch

ohm

1

Rs

Rt

49.9

Down Device Differential Routing

L4 length, route as coupled microstrip 100ohm differential trace 2 min to 16 max

inch

1

L4 length, route as coupled stripline 100ohm differential trace

1.8 min to 14.4 max

Differential Routing to PCI Express Connector

L4 length, route as coupled microstrip 100ohm differential trace 0.25 to 14 max

inch

2

L4 length, route as coupled stripline 100ohm differential trace

0.225 min to 12.6 max

Figure 1: Down Device Routing

L2

L1

Rs

L4

L4'

L2'

L1'

Rt

HCSL Output Buffer

PCI Express

Down Device

REF_CLK Input

L3' L3

Figure 2: PCI Express Connector Routing

L2

L1

Rs

L4

L4'

L2'

L1'

Rs

Rt

HCSL Output Buffer

PCI Express

Add-in Board

REF_CLK Input

L3' L3

IDT^®19 Output Differential Buffer for PCIe Gen2 and QPI

1607C—04/19/11

10

9DB1904B

19 Output Differential Buffer for PCIe Gen2 and QPI

Alternative Termination for LVDS and other Common Differential Signals (figure 3)

Vdiff

0.45v

0.58

0.80

0.60

Vp-p

0.22v

0.28

0.40

0.3

Vcm

1.08

0.6

1.2

R1

33

R2

R3

R4

Note

150

78.7

174

100

137

none

140

100

ICS874003i-02 input compatible

Standard LVDS

R1a = R1b = R1

R2a = R2b = R2

Figure 3

L2

L1

R3

R4

R1a

L4

L4'

L2'

L1'

R1b

R2a

R2b

HCSL Output Buffer

Down Device

REF_CLK Input

L3'

L3

Cable Connected AC Coupled Application (figure 4)

Component

R5a, R5b

R6a, R6b

Cc

Value

8.2K 5%

1K 5%

Note

0.1 µF

Vcm

0.350 volts

Figure 4

3.3 Volts

R5a

R5b

R6b

Cc

L4

L4'

R6a

PCIe Device

REF_CLK Input

IDT^®19 Output Differential Buffer for PCIe Gen2 and QPI

1607C—04/19/11

11

9DB1904B

19 Output Differential Buffer for PCIe Gen2 and QPI

9DB1904 SMBus Address Mapping

when using CK410/CK410B, 9FG1200, and

9DB403/803

SMB_A(2:0) = 000

SMB Adr: D0

9FG1201

SMB Adr: D0

OR

9DB1904

(DB1200G)

SMB_A(2:0) = 001

SMB Adr: D2

SMB_A(2:0) = 001

SMB Adr: D2

9FG1201

SMB Adr: D2

932S421

OR

CK410B

9DB1904

(DB1200G)

SMB_A(2:0) = 010

SMB Adr: D4

SMB_A(2:0) = 010

SMB Adr: D4

9FG1201

9DB1904

(DB1200G)

SMB_A(2:0) = 011

SMB Adr: D6

SMB_A(2:0) = 011

SMB Adr: D6

9FG1201

9DB1904

(DB1200G)

SMB_A(2:0) = 100

SMB Adr: D8

SMB_A(2:0) = 100

SMB Adr: D8

9FG1201

9DB1904

(DB1200G)

SMB_A(2:0) = 101

SMB Adr: DA

SMB_A(2:0) = 101

SMB Adr: DA

9FG1201

9DB1904

(DB1200G)

SMB_A(2:0) = 110

SMB Adr: DC

SMB_A(2:0) = 110

SMB Adr: DC

9FG1201

SMB Adr: DC

9DB403/803

(DB400/800)

OR

9DB1904

(DB1200G)

SMB_A(2:0) = 111

SMB Adr: DE

SMB_A(2:0) = 111

SMB Adr: DE

9FG1201

9DB1904

(DB1200G)

IDT^®19 Output Differential Buffer for PCIe Gen2 and QPI

1607C—04/19/11

12

9DB1904B

19 Output Differential Buffer for PCIe Gen2 and QPI

General SMBus serial interface information for the 9DB1904B

How to Write:

How to Read:

• Controller (host) will send start bit.

• Controller (host) sends the write address D4_(h)

• IDT clock will acknowledge

• Controller (host) sends a start bit.

• Controller (host) sends the write address D4_(h)

• IDT clock will acknowledge

• Controller (host) sends the begining byte location = N

• IDT clock will acknowledge

• Controller (host) sends the begining byte

location = N

• Controller (host) sends the data byte count = X

• IDT clock will acknowledge

• Controller (host) starts sending Byte N through

Byte N + X -1

• IDT clock will acknowledge

• Controller (host) will send a separate start bit.

• Controller (host) sends the read address D5_(h)

• IDT clock will acknowledge

• IDT clock will acknowledge each byte one at a time

• Controller (host) sends a Stop bit

• IDT clock will send the data byte count = X

• IDT clock sends Byte N + X -1

• IDT clock sends Byte 0 through byte X (if X_(h)

was written to byte 8).

• Controller (host) will need to acknowledge each byte

• Controllor (host) will send a not acknowledge bit

• Controller (host) will send a stop bit

Index Block Read Operation

Index Block Write Operation

Controller (Host)

IDT (Slave/Receiver)

Controller (Host)

IDT (Slave/Receiver)

T

starT bit

T

Slave Address D4_(h)*

WR

WRite

WR

WRite

Beginning Byte = N

Data Byte Count = X

Beginning Byte N

ACK

Beginning Byte = N

RT

Repeat starT

Slave Address D5_(h)*

RD

ReaD

ACK

Data Byte Count = X

Beginning Byte N

ACK

Byte N + X - 1

ACK

P

stoP bit

Byte N + X - 1

N

P

Not acknowledge

stoP bit

IDT^®19 Output Differential Buffer for PCIe Gen2 and QPI

1607C—04/19/11

13

9DB1904B

19 Output Differential Buffer for PCIe Gen2 and QPI

SMBusTable: Reserved Register

Byte 0

Bit 7

Pin #

-

Name

Control Function

Reserved

Type

R

0

1

PWD

1

0

1

-

Reserved

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SMBusTable: Output Control Register

Byte 1

Bit 7

Pin #

Name

DIF_7

DIF_6

DIF_5

DIF_4

DIF_3

DIF_2

DIF_1

DIF_0

Control Function

Type

RW

0

1

PWD

Output Control

Hi-Z

Enable

1

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SMBusTable: Output and PLL BW Control Register

Byte 2

Bit 7

Pin #

see note

Name

Control Function

PLL_BW# adjust

BYPASS# test mode / PLL

Type

RW

0

High BW

Bypass

Hi-Z

1

PWD

Low BW

PLL

1

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

DIF_13

Output Control

Enable

DIF_12

DIF_11

DIF_10

DIF_9

Hi-Z

DIF_8

Hi-Z

Note: Bit 7 is wired OR to the HIGH_BW# input, any 0 selects High BW

Note: Bit 6 is wired OR to the SMB_A2_PLLBYP# input, any 0 selects Fanout Bypass mode

SMBusTable: Output Enable Readback Register

Byte 3 Pin # Name Control Function

Readback - OE9# Input

Type

R

0

1

PWD

X

Readback

Bit 7

Readback - OE8# Input

Readback - OE7# Input

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Readback - OE6# Input

Readback - OE5# Input

Readback - OE_01234# Input

Readback - HIGH_BW# In

Readback - SMB_A2_PLLBYP# In

8

72

IDT^®19 Output Differential Buffer for PCIe Gen2 and QPI

1607C—04/19/11

14

9DB1904B

19 Output Differential Buffer for PCIe Gen2 and QPI

SMBusTable: Output Enable Readback Register

Byte 4

Bit 7

Pin #

69

60

Name

Control Function

Type

R

0

1

PWD

X

0

X

Readback - OE17_18# Input

Readback - OE15_16# Input

Reserved

Readback - OE14# Input

Readback - OE13# Input

Readback - OE12# Input

Readback - OE11# Input

Readback - OE10# Input

Readback

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

54

51

48

43

40

R

Readback

SMBusTable: Vendor & Revision ID Register

Byte 5

Bit 7

Pin #

-

Name

RID3

RID2

RID1

RID0

VID3

VID2

VID1

VID0

Control Function

Type

R

0

-

1

-

PWD

0

1

0

1

-

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

REVISION ID

VENDOR ID

SMBusTable: DEVICE ID (194 Decimal or C2 Hex)

Byte 6 Pin # Name Control Function

Device ID 7 (MSB)

Type

RW

0

1

PWD

-

Reserved

1

0

1

0

Bit 7

-

Device ID 6

Device ID 5

Device ID 4

Device ID 3

Device ID 2

Device ID 1

Device ID 0

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SMBusTable: Byte Count Register

Byte 7

Bit 7

Pin #

-

Name

BC7

BC6

BC5

BC4

BC3

BC2

BC1

BC0

Control Function

Type

RW

0

-

1

-

PWD

0

1

-

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Writing to this register

configures how many

bytes will be read back.

IDT^®19 Output Differential Buffer for PCIe Gen2 and QPI

1607C—04/19/11

15

9DB1904B

19 Output Differential Buffer for PCIe Gen2 and QPI

SMBusTable: Control Pin Readback Register

Byte 8

Pin #

Name

Control Function

Type

R

0

1

PWD

5

Readback -100M_133M#_LV

Readback

Latch

Bit 7

RESERVED

Output Control

X

1

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

DIF_18

DIF_17

DIF_16

DIF_15

DIF_14

RW

Hi-Z

Enable

SMBusTable: PLL Operating Set Point Register

Byte 9 Pin # Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Control Function

RESERVED

Type

0

1

PWD

0

-

Frequency Select 100M_133M#

RW

Latch

Bit 2

See ICS9DB1904 1:1

-

Frequency Select B

Frequency Select A

RW

0

1

Bit 1

Bit 0

PLL Programming Table

IDT^®19 Output Differential Buffer for PCIe Gen2 and QPI

1607C—04/19/11

16

9DB1904B

19 Output Differential Buffer for PCIe Gen2 and QPI

(Ref. )

Seating Plane

(N_D- 1)x

e

&

N_E

N_D

(Ref. )

Even

A1

Index Area

L

A3

E2

N

e

(Typ.)

2

If N &

N_E

D

Anvil

Singulation

are Even

1

2

1

(N - 1)x

e

E

OR

E

(Ref. )

E2

2

Sawn

Singulation

Top View

D

b

e

Thermal

Base

(Ref.)

D2

A

N &

N_E

Odd

D

2

D2

Chamfer 4x

0.6 x 0.6 max

OPTIONAL

C

0.08

THERMALLY ENHANCED, VERY THIN, FINE PITCH

QUAD FLAT / NO LEAD PLASTIC PACKAGE

DIMENSIONS

ICS 72L

SYMBOL

MIN.

0.8

0

MAX.

1.0

0.05

SYMBOL

TOLERANCE

A

A1

N

N_D

72

18

A3

b

e

0.25 Reference

0.18 0.3

0.50 BASIC

N_E

18

D x E BASIC

D2 MIN. / MAX.

E2 MIN. / MAX.

L MIN. / MAX.

10.00 x 10.00

5.75 / 6.15

0.30/ 0.50

Ordering Information

Part / Order Number Shipping Packaging

Package

72-pin MLF

Temperature

0 to +70° C

9DB1904BKLF

9DB1904BKLFT

Tubes

Tape and Reel

"LF" suffix to the part number are the Pb-Free configuration, RoHS compliant.

"B" is the device revision designator (will not correlate with the datasheet revision).

IDT^®19 Output Differential Buffer for PCIe Gen2 and QPI

1607C—04/19/11

17

9DB1904B

19 Output Differential Buffer for PCIe Gen2 and QPI

Revision History

Rev. Issue Date Description

Page #

0.1

0.2

7/1/2009 Initial release

7/8/2009 Updated revision ID in Byte 5

-

13

Updated electrical characteristics tables.

A

B

C

9/21/2010 Added Test loads and terminations

Corrected minor typo's, move to release.

1. Updated electrical char tables

9/23/2010 2. Updated test loads and termination figures

3. Added Period PPM tables

Various

1. Updated electrical tabels with Typ. Values

4/19/2011 2. Updated Differential Clock Period PPM tables

Innovate with IDT and accelerate your future networks. Contact:

www.IDT.com

For Sales

For Tech Support

800-345-7015

408-284-6578

408-284-8200

pcclockhelp@idt.com

Fax: 408-284-2775

Corporate Headquarters

Asia Pacific and Japan

Europe

Integrated Device Technology, Inc.

6024 Silver Creek Valley Road

San Jose, CA 95138

IDT Singapore Pte. Ltd.

1 Kallang Sector #07-01/06

KolamAyer Industrial Park

Singapore 349276

IDT Europe Limited

321 Kingston Road

Leatherhead, Surrey

KT22 7TU

United States

800 345 7015

+408 284 8200 (outside U.S.)

Phone: 65-6-744-3356

Fax: 65-6-744-1764

England

Phone: 44-1372-363339

Fax: 44-1372-378851

©

Integrated Device Technology, Inc. Accelerated Thinking is service mark of Integrated Device Technology, Inc. All other brands, product names and marks are

a

or may be trademarks or registered trademarks used to identify products or services of their respective owners.

Printed in USA

18

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	VFQFPN
包装说明：	HVQCCN, LCC72,.39SQ,20	针数：	72
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.45
系列：	9DB	输入调节：	DIFFERENTIAL
JESD-30 代码：	S-PQCC-N72	JESD-609代码：	e3
长度：	10 mm	逻辑集成电路类型：	PLL BASED CLOCK DRIVER
湿度敏感等级：	3	功能数量：	1
反相输出次数：		端子数量：	72
实输出次数：	19	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	HVQCCN	封装等效代码：	LCC72,.39SQ,20
封装形状：	SQUARE	封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：	260	电源：	3.3 V
认证状态：	Not Qualified	Same Edge Skew-Max（tskwd）：	0.15 ns
座面最大高度：	1 mm	子类别：	Clock Drivers
最大供电电压 (Vsup)：	3.465 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
温度等级：	COMMERCIAL	端子面层：	Matte Tin (Sn) - annealed
端子形式：	NO LEAD	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	10 mm	Base Number Matches：	1

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9DB1904BKLFT

9DB1904BKLFT 概述

9DB1904BKLFT 规格参数

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