9DBL08 [IDT]
8-output 3.3V PCIe Zero-Delay Buffer;
| 型号： | 9DBL08 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 8-output 3.3V PCIe Zero-Delay Buffer PC |
| 文件： | 总19页 (文件大小：354K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
8-output 3.3V PCIe Zero-Delay Buffer
9DBL08
DATASHEET
Description
Features/Benefits
The 9DBL08 devices are 3.3V members of IDT's
Full-Featured PCIe family. The 9DBL08 supports PCIe
Gen1-4 Common Clocked (CC) and PCIe Separate
Reference Independent Spread (SRIS) systems. It offers a
choice of integrated output terminations providing direct
connection to 85Ω or 100Ω transmission lines. The
9DBL08P1 can be factory programmed with a user-defined
power up default SMBus configuration.
• Direct connection to 100 (0841) or 85 (0851)
transmission lines; saves 32 resistors compared to
standard PCIe devices
• 211mW typical power consumption (PLL mode@3.3V);
eliminates thermal concerns
• VDDIO allows 35% power savings at optional 1.05V;
maximum power savings
• SMBus-selectable features allows optimization to customer
requirements:
Recommended Application
PCIe Gen1-4 clock distribution for Riser Cards, Storage,
Networking, JBOD, Communications, Access Points
• control input polarity
• control input pull up/downs
• slew rate for each output
• differential output amplitude
• output impedance for each output
• 50, 100, 125MHz operating frequency
Output Features
• 8 – 1-200 MHz Low-Power (LP) HCSL DIF pairs
• 9DBL0841 default ZOUT = 100
• 9DBL0851 default ZOUT = 85
• 9DBL08P1 factory programmable defaults
• Easy AC-coupling to other logic families, see IDT
application note AN-891
• Customer defined SMBus power up default can be
programmed into P1 device; allows exact optimization to
customer requirements
• OE# pins; support DIF power management
• HCSL-compatible differential input; can be driven by
common clock sources
Key Specifications
• PCIe Gen1-2-3-4 CC compliant in ZDB mode
• PCIe Gen2 SRIS compliant in ZDB mode
• Supports PCIe Gen2-3 SRIS in fan-out mode
• DIF cycle-to-cycle jitter <50ps
• DIF output-to-output skew < 50ps
• Bypass mode additive phase jitter is 0 ps typical rms for
PCIe
• Spread Spectrum tolerant; allows reduction of EMI
• Pin/SMBus selectable PLL bandwidth and PLL Bypass;
minimize phase jitter for each application
• Outputs blocked until PLL is locked; clean system start-up
• Device contains default configuration; SMBus interface not
required for device operation
• Three selectable SMBus addresses; multiple devices can
easily share an SMBus segment
• Bypass mode additive phase jitter 160fs rms typ. @
156.25M (1.5M to 10M)
• Space saving 48-pin 6x6mm VFQFPN; minimal board
space
Block Diagram
Note: Resistors default to internal on 41/51 devices. P1 devices have programmable default impedances on an output-by-output basis.
9DBL08 REVISION D 08/16/16
1
©2016 Integrated Device Technology, Inc.
9DBL08 DATASHEET
Pin Configuration
48 47 46 45 44 43 42 41 40 39 38 37
vSADR_tri 1
36 DIF5#
35 DIF5
^vHIBW_BYPM_LOBW# 2
FB_DNC 3
34 vOE4#
33 DIF4#
32 DIF4
FB_DNC# 4
VDDR3.3 5
CLK_IN 6
31 VDDIO
30 VDDA3.3
29 GNDA
28 vOE3#
27 DIF3#
26 DIF3
9DBL0841/51/P1
CLK_IN# 7
epad is GND
GNDR 8
GNDDIG 9
SCLK_3.3 10
SDATA_3.3 11
VDDDIG3.3 12
25 vOE2#
13 14 15 16 17 18 19 20 21 22 23 24
48-pin VFQFPN, 6x6 mm, 0.4mm pitch
^v prefix indicates internal 120KOhm pull up AND pull down resistor (biased to VDD/2)
v
^
prefix indicates internal 120KOhm pull down resistor
prefix indicates internal 120KOhm pull up resistor
SMBus Address Selection Table
+
Read/Write bit
SADR
Address
1101011
1101100
1101101
x
x
x
0
M
1
State of SADR on first application of
CKPWRGD_PD#
Note: If not using CKPWRGD (CKPWRGD tied to VDD3.3), all 3.3V VDD need to
transition from 2.1V to 3.135V in <300usec.
Power Management Table
DIFx
SMBus
OEx bit
CKPWRGD_PD#
CLK_IN
OEx# Pin
PLL
True O/P Comp. O/P
Low1
Low1
Low1
Low1
0
1
1
1
X
X
0
1
1
X
X
0
Off
On2
On2
On2
Running
Running
Running
Running
Low1
Running
Low1
1
1. The output state is set by B11[1:0] (Low/Low default)
2. If Bypass mode is selected, the PLL will be off, and outputs will be running.
Power Connections
PLL Operating Mode
Pin Number
Description
Byte1 [7:6] Byte1 [4:3]
VDD
VDDIO
GND
HiBW_BypM_LoBW#
MODE
PLL Lo BW
Bypass
Readback
Control
00
Input
receiver
analog
Digital Power
0
M
1
00
01
11
5
8
9
01
PLL Hi BW
11
12
20,31,38
30
13,21,31,
39,47
22, 29,40,49 DIF outputs
29 PLL Analog
8-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER
2
REVISION D 08/16/16
9DBL08 DATASHEET
Pin Descriptions
PIN #
PIN NAME
TYPE
LATCHED
IN
DESCRIPTION
1
vSADR_tri
Tri-level latch to select SMBus Address. See SMBus Address Selection Table.
Trilevel input to select High BW, Bypass or Low BW mode. This pin is biased
to VDD/2 (Bypass mode) with internal pull up/pull down resistors. See PLL
Operating Mode Table for Details.
LATCHED
IN
2
^vHIBW_BYPM_LOBW#
True clock of differential feedback. The feedback output and feedback input are
connected internally on this pin. Do not connect anything to this pin.
3
4
5
FB_DNC
FB_DNC#
VDDR3.3
DNC
DNC
PWR
Complement clock of differential feedback. The feedback output and feedback
input are connected internally on this pin. Do not connect anything to this pin.
3.3V power for differential input clock (receiver). This VDD should be treated as
an Analog power rail and filtered appropriately.
True Input for differential reference clock.
Complementary Input for differential reference clock.
Analog Ground pin for the differential input (receiver)
Ground pin for digital circuitry
Clock pin of SMBus circuitry, 3.3V tolerant.
Data pin for SMBus circuitry, 3.3V tolerant.
3.3V digital power (dirty power)
6
7
8
9
CLK_IN
CLK_IN#
GNDR
IN
IN
GND
GND
IN
I/O
PWR
PWR
GNDDIG
10 SCLK_3.3
11 SDATA_3.3
12 VDDDIG3.3
13 VDDIO
Power supply for differential outputs
Active low input for enabling output 0. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
Active low input for enabling output 1. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
Power supply, nominal 3.3V
Power supply for differential outputs
14 vOE0#
IN
15 DIF0
16 DIF0#
OUT
OUT
17 vOE1#
IN
18 DIF1
OUT
OUT
PWR
PWR
GND
OUT
OUT
19 DIF1#
20 VDD3.3
21 VDDIO
22 GND
23 DIF2
24 DIF2#
Ground pin.
Differential true clock output
Differential Complementary clock output
Active low input for enabling output 2. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
Active low input for enabling output 3. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Ground pin for the PLL core.
25 vOE2#
IN
26 DIF3
27 DIF3#
OUT
OUT
28 vOE3#
IN
29 GNDA
30 VDDA3.3
31 VDDIO
32 DIF4
GND
PWR
PWR
OUT
OUT
3.3V power for the PLL core.
Power supply for differential outputs
Differential true clock output
33 DIF4#
Differential Complementary clock output
Active low input for enabling output 4. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
Active low input for enabling output 5. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Power supply, nominal 3.3V
34 vOE4#
IN
35 DIF5
36 DIF5#
OUT
OUT
37 vOE5#
IN
38 VDD3.3
39 VDDIO
PWR
PWR
Power supply for differential outputs
REVISION D 08/16/16
3
8-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER
9DBL08 DATASHEET
Pin Descriptions (cont.)
PIN #
40 GND
41 DIF6
PIN NAME
TYPE
GND
OUT
OUT
DESCRIPTION
Ground pin.
Differential true clock output
42 DIF6#
Differential Complementary clock output
Active low input for enabling output 6. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
43 vOE6#
IN
44 DIF7
45 DIF7#
OUT
OUT
Differential true clock output
Differential Complementary clock output
Active low input for enabling output 7. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Power supply for differential outputs
46 vOE7#
47 VDDIO
IN
PWR
Input notifies device to sample latched inputs and start up on first high
assertion. Low enters Power Down Mode, subsequent high assertions exit
Power Down Mode. This pin has internal pull-up resistor.
Connect to Ground.
48 ^CKPWRGD_PD#
49 EPAD
IN
GND
Test Loads
Terminations
Low-Power push-pull HCSL Output test load
(integrated terminations)
Device
Zo (Ω)
100
100
100
85
Rs (Ω)
None needed
7.5
9DBL0841
9DBL0851
9DBL08P1
9DBL0841
9DBL0851
9DBL08P1
Prog.
L inches
N/A
Differential Zo
85
85
None needed
Prog.
2pF
2pF
Alternate Terminations
The 9DBL family can easily drive LVPECL, LVDS, and CML logic. See “AN-891 Driving LVPECL, LVDS, and CML Logic with
IDT's "Universal" Low-Power HCSL Outputs” for details.
8-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER
4
REVISION D 08/16/16
9DBL08 DATASHEET
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9DBL08. These ratings, which are standard values
for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended
operating temperature range.
PARAMETER
SYMBOL
CONDITIONS
UNITS NOTES
MIN
-0.5
TYP
MAX
4.6
VDD+0.5
Supply Voltage
Input Voltage
VDDx
VIN
V
V
1,2
1,3
Input High Voltage, SMBus
VIHSMB
Ts
Tj
SMBus clock and data pins
Human Body Model
3.9
150
125
V
1
1
1
1
Storage Temperature
Junction Temperature
Input ESD protection
-65
°C
°C
V
ESD prot
2500
1Guaranteed by design and characterization, not 100% tested in production.
2 Operation under these conditions is neither implied nor guaranteed.
3 Not to exceed 4.6V.
Electrical Characteristics–SMBus Parameters
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
SMBus Input Low Voltage
SMBus Input High Voltage
VILSMB
VIHSMB
VDDSMB = 3.3V
VDDSMB = 3.3V
@ IPULLUP
0.8
3.6
0.4
V
V
2.1
SMBus Output Low Voltage VOLSMB
V
SMBus Sink Current
Nominal Bus Voltage
SCLK/SDATA Rise Time
IPULLUP
VDDSMB
tRSMB
@ VOL
4
mA
V
2.7
3.6
1000
300
(Max VIL - 0.15) to (Min VIH + 0.15)
(Min VIH + 0.15) to (Max VIL - 0.15)
ns
ns
1
1
SCLK/SDATA Fall Time
SMBus Operating
Frequency
tFSMB
fSMB
SMBus operating frequency
500
kHz
2,3
1 Guaranteed by design and characterization, not 100% tested in production.
2. The device must be powered up for the SMBus to function.
3.
The differential input clock must be running for the SMBus to be active
Electrical Characteristics–Clock Input Parameters
TA = TAMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
900
UNITS NOTES
Input Crossover Voltage -
DIF_IN
VCROSS
Cross Over Voltage
150
mV
1
Input Swing - DIF_IN
Input Slew Rate - DIF_IN
VSWING
dv/dt
IIN
Differential value
Measured differentially
300
0.4
-5
mV
V/ns
uA
1
1,2
8
5
Input Leakage Current
Input Duty Cycle
VIN = VDD , VIN = GND
dtin
Measurement from differential wavefrom
45
0
55
125
%
1
1
Input Jitter - Cycle to Cycle
JDIFIn
Differential Measurement
ps
1 Guaranteed by design and characterization, not 100% tested in production.
2Slew rate measured through +/-75mV window centered around differential zero
REVISION D 08/16/16
5
8-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER
9DBL08 DATASHEET
Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating
Conditions
TA = TAMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
Supply Voltage
Output Supply Voltage
Ambient Operating
Temperature
VDDx
VDDIO
Supply voltage for core and analog
Supply voltage for Low Power HCSL Outputs
3.135
0.95
3.3
1.05-3.3
3.465
3.465
V
V
TAMB
Industrial range
-40
25
85
°C
Input High Voltage
VIH
0.75 VDDx
VDDx + 0.3
V
Single-ended inputs, except SMBus
Input Low Voltage
Input High Voltage
Input Mid Voltage
Input Low Voltage
VIL
VIHtri
VIMtri
VILtri
IIN
-0.3
0.25 VDDx
VDD + 0.3
V
V
0.75 VDDx
Single-ended tri-level inputs ('_tri' suffix)
0.4 VDDx 0.5 VDDx 0.6 VDDx
V
-0.3
-5
0.25 VDDx
5
V
Single-ended inputs, VIN = GND, VIN = VDD
Single-ended inputs
IN = 0 V; Inputs with internal pull-up resistors
IN = VDD; Inputs with internal pull-down resistors
Bypass mode
uA
Input Current
V
IINP
-50
50
uA
V
1
200
140
65
175
7
MHz
MHz
MHz
MHz
nH
2
2
2
2
1
1
1
1
100MHz PLL mode
60
30
75
100.00
50.00
Input Frequency
FIN
50MHz PLL mode
125MHz PLL mode
125.00
Pin Inductance
Capacitance
Lpin
CIN
Logic Inputs, except DIF_IN
DIF_IN differential clock inputs
Output pin capacitance
1.5
1.5
5
pF
CINDIF_IN
COUT
2.7
6
pF
pF
From VDD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
Clk Stabilization
TSTAB
1
ms
1,2
Input SS Modulation
Frequency PCIe
Allowable Frequency for PCIe Applications
(Triangular Modulation)
fMODINPCIe
30
33
kHz
Input SS Modulation
Frequency non-PCIe
Allowable Frequency for non-PCIe Applications
(Triangular Modulation)
fMODIN
tLATOE#
tDRVPD
0
1
66
3
kHz
clocks
us
DIF start after OE# assertion
DIF stop after OE# deassertion
DIF output enable after
OE# Latency
Tdrive_PD#
1,3
1,3
300
PD# de-assertion
Tfall
tF
Fall time of single-ended control inputs
5
5
ns
ns
2
2
Trise
tR
Rise time of single-ended control inputs
1Guaranteed by design and characterization, not 100% tested in production.
2Control input must be monotonic from 20% to 80% of input swing.
3Time from deassertion until outputs are >200 mV
8-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER
6
REVISION D 08/16/16
9DBL08 DATASHEET
Electrical Characteristics–DIF Low-Power HCSL Outputs
TA = TAMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP MAX UNITS NOTES
V/ns
V/ns
%
dV/dt
dV/dt
dV/dt
Δ
Scope averaging on, fast setting
Scope averaging on, slow setting
Slew rate matching
2
1.2
2.8
1.9
7
4
3.1
20
1,2,3
1,2,3
1,2,4
Slew rate
Slew rate matching
Voltage High
Statistical measurement on single-ended signal
using oscilloscope math function. (Scope
averaging on)
VHIGH
660
768
-11
850
7
7
mV
Voltage Low
VLOW
-150
150
Max Voltage
Min Voltage
Crossing Voltage (abs)
Vmax
Vmin
Vcross_abs
Measurement on single ended signal using
absolute value. (Scope averaging off)
Scope averaging off
811
-49
357
14
1150
7
7
1,5
1,6
mV
-300
250
550
140
mV
mV
Crossing Voltage (var)
-Vcross
Scope averaging off
Δ
1Guaranteed by design and characterization, not 100% tested in production.
2 Measured from differential waveform
3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on
the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations.
5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising
edge (i.e. Clock rising and Clock# falling).
6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross
absolute) allowed. The intent is to limit Vcross induced modulation by setting -Vcross to be smaller than Vcross absolute.
Δ
7 At default SMBus settings.
Electrical Characteristics–Current Consumption
TA = TAMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
IDDA
CONDITIONS
MIN
TYP
7
MAX
10
UNITS NOTES
VDDA, PLL Mode, @100MHz
VDDx, All outputs active @100MHz
mA
mA
mA
Operating Supply Current
IDD
22
32
IDDIO
IDDAPD
IDDPD
VDDIO, All outputs active @100MHz
VDDA, CKPWRGD_PD#=0
VDDx, CKPWRGD_PD#=0
35
0.6
45
1
mA
mA
mA
2
2
2
Powerdown Current
4.9
7
IDDIOPD
VDDIO, CKPWRGD_PD#=0
0.04
0.10
1 Guaranteed by design and characterization, not 100% tested in production.
2 Input clock stopped.
REVISION D 08/16/16
7
8-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER
9DBL08 DATASHEET
Electrical Characteristics–Output Duty Cycle, Jitter, Skew and PLL Characteristics
TA = TAMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
-3dB point in High BW Mode (100MHz)
-3dB point in Low BW Mode (100MHz)
Peak Pass band Gain (100MHz)
2
1
3.3
1.5
0.8
4
2
2
MHz
MHz
dB
1,5
1,5
1
PLL Bandwidth
BW
PLL Jitter Peaking
Duty Cycle
tJPEAK
tDC
Measured differentially, PLL Mode
Measured differentially, Bypass Mode
Bypass Mode, VT = 50%
45
-1
50
0.0
3406
8
55
1
%
%
1
Duty Cycle Distortion
tDCD
1,3
1
tpdBYP
tpdPLL
tsk3
2500
-100
4500
100
ps
ps
Skew, Input to Output
PLL Mode VT = 50%
1,4
Skew, Output to Output
Jitter, Cycle to cycle
VT = 50%
PLL mode
Additive Jitter in Bypass Mode
21
15
0.1
55
50
1
ps
ps
ps
1,4
1,2
1,2
tjcyc-cyc
1 Guaranteed by design and characterization, not 100% tested in production.
2 Measured from differential waveform
3 Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.
4 All outputs at default slew rate
5 The MIN/TYP/MAX values of each BW setting track each other, i.e., Low BW MAX will never occur with Hi BW MIN.
Electrical Characteristics–Filtered Phase Jitter Parameters - PCIe Common Clocked
(CC) Architectures
TAMB = over the specified operating range. Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
INDUSTRY
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
23
MAX
32
UNITS Notes
ps (p-p) 1,2,3,5
LIMIT
86
tjphPCIeG1-CC
PCIe Gen 1
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
ps
0.6
1.7
0.8
3
1,2,5
(rms)
(PLL BW of 5-16MHz or 8-5MHz, CDR = 5MHz)
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
(PLL BW of 5-16MHz or 8-5MHz, CDR = 5MHz)
PCIe Gen 3
(PLL BW of 2-4MHz or 2-5MHz, CDR = 10MHz)
PCIe Gen 4
(PLL BW of 2-4MHz or 2-5MHz, CDR = 10MHz)
tjphPCIeG2-CC
Phase Jitter,
PLL Mode
ps
2.1
3.1
1,2,5
(rms)
ps
0.48
0.48
0.01
1
tjphPCIeG3-CC
tjphPCIeG4-CC
tjphPCIeG1-CC
0.4
0.4
0.0
1,2,5
(rms)
ps
(rms)
0.5
1,2,5
ps
PCIe Gen 1
1,2,5
(p-p)
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
(PLL BW of 5-16MHz or 8-5MHz, CDR = 5MHz)
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
(PLL BW of 5-16MHz or 8-5MHz, CDR = 5MHz)
PCIe Gen 3
(PLL BW of 2-4MHz or 2-5MHz, CDR = 10MHz)
PCIe Gen 4
ps
0.0
0.0
0.01
0.01
1,2,4,5
(rms)
tjphPCIeG2-CC
Additive Phase Jitter,
n/a
ps
Bypass mode
1,2,4,5
(rms)
ps
tjphPCIeG3-CC
tjphPCIeG4-CC
0.0
0.0
0.01
0.01
1,2,4,5
(rms)
ps
1,2,4,5
(rms)
(PLL BW of 2-4MHz or 2-5MHz, CDR = 10MHz)
1 Applies to all outputs.
2 Based on PCIe Base Specification Rev4.0 version 0.7draft. See http://www.pcisig.com for latest specifications.
3 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.
4 For RMS values additive jitter is calculated by solving the following equation for b [a^2+b^2=c^2] where a is rms input jitter and c is rms total jitter.
5 Driven by 9FGL0841 or equivalent
8-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER
8
REVISION D 08/16/16
9DBL08 DATASHEET
Electrical Characteristics–Filtered Phase Jitter Parameters - PCIe Separate
Reference Independent Spread (SRIS) Architectures5
TAMB = over the specified operating range. Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
INDUSTRY
LIMIT
PARAMETER
SYMBOL
tjphPCIeG2-SRIS
tjphPCIeG3-SRIS
tjphPCIeG2-SRIS
tjphPCIeG3-SRIS
CONDITIONS
MIN
TYP
1.2
n/a
0.0
0.0
MAX
1.5
UNITS Notes
PCIe Gen 2
(PLL BW of 16MHz , CDR = 5MHz)
PCIe Gen 3
ps
1,2
2
(rms)
Phase Jitter, PLL Mode
ps
(rms)
0.5
1,2,6
(PLL BW of 2-4MHz or 2-5MHz, CDR = 10MHz)
PCIe Gen 2
(PLL BW of 16MHz , CDR = 5MHz)
PCIe Gen 3
(PLL BW of 2-4MHz or 2-5MHz, CDR = 10MHz)
ps
0.01
1,2,4
(rms)
Additive Phase Jitter,
Bypass mode
n/a
ps
0.01
1,2,4,6
(rms)
1 Applies to all outputs.
2 Based on PCIe Base Specification Rev3.1a. These filters are different than Common Clock filters. See http://www.pcisig.com for latest specifications.
3 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.
4 For RMS values, additive jitter is calculated by solving the following equation for b [a^2+b^2=c^2] where a is rms input jitter and c is rms total jitter.
5 As of PCIe Base Specification Rev4.0 draft 0.7, SRIS is not currently defined for Gen1 or Gen4.
6 This device does not support PCIe Gen3 SRIS in PLL mode. It supports PCIe Gen3 SRIS in bypass mode.
Electrical Characteristics–Unfiltered Phase Jitter Parameters
TA = TAMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
INDUSTRY
PARAMETER
SYMBOL
tjph156M
CONDITIONS
MIN
TYP
159
MAX
LIMIT
N/A
UNITS Notes
156.25MHz, 1.5MHz to 10MHz, -20dB/decade
rollover < 1.5MHz, -40db/decade rolloff > 10MHz
fs
1,2,3
(rms)
Additive Phase Jitter,
Fanout Mode
156.25MHz, 12kHz to 20MHz, -20dB/decade
rollover <12kHz, -40db/decade rolloff > 20MHz
fs
tjph156M12k-20
363
N/A
1,2,3
(rms)
1Guaranteed by design and characterization, not 100% tested in production.
2
DRiven by Rohde&Schartz SMA100
3 For RMS figures, additive jitter is calculated by solving the following equation: Additive jitter = SQRT[(total jitter)^2 - (input jitter)^2]
REVISION D 08/16/16
9
8-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER
9DBL08 DATASHEET
General SMBus Serial Interface Information
How to Write
How to Read
• Controller (host) sends a start bit
• Controller (host) sends the write address
• IDT clock will acknowledge
• Controller (host) will send a start bit
• Controller (host) sends the write address
• IDT clock will acknowledge
• Controller (host) sends the beginning byte location = N
• IDT clock will acknowledge
• Controller (host) sends the beginning byte location = N
• IDT clock will acknowledge
• Controller (host) sends the byte count = X
• IDT clock will acknowledge
• Controller (host) will send a separate start bit
• Controller (host) sends the read address
• IDT clock will acknowledge
• Controller (host) starts sending Byte N through Byte
N+X-1
• IDT clock will send the data byte count = X
• IDT clock sends Byte N+X-1
• IDT clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
• IDT clock sends Byte 0 through Byte X (if X was
(H)
written to Byte 8)
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Write Operation
Index Block Read Operation
Controller (Host)
starT bit
Slave Address
IDT (Slave/Receiver)
Controller (Host)
starT bit
IDT (Slave/Receiver)
T
T
Slave Address
WR
WRite
WR
WRite
ACK
ACK
ACK
ACK
ACK
ACK
Beginning Byte = N
Data Byte Count = X
Beginning Byte N
Beginning Byte = N
RT
Repeat starT
Slave Address
ReaD
RD
ACK
O
O
O
O
O
O
Data Byte Count=X
Beginning Byte N
ACK
ACK
Byte N + X - 1
ACK
O
O
O
P
stoP bit
O
O
O
Note: SMBus Address is Latched on SADR pin.
Unless otherwise indicated, default values are for the
xx31, xx41, and xx51. P1 devices are fully factory
programmable.
Byte N + X - 1
N
P
Not acknowledge
stoP bit
8-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER
10
REVISION D 08/16/16
9DBL08 DATASHEET
SMBus Table: Output Enable Register 1
Byte 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Control Function
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
Default
DIF OE7
DIF OE6
DIF OE5
DIF OE4
DIF OE3
DIF OE2
DIF OE1
DIF OE0
Pin Control
Pin Control
Pin Control
Pin Control
Pin Control
Pin Control
Pin Control
Pin Control
1
1
1
1
1
1
1
1
See B11[1:0]
1. A low on these bits will overide the OE# pin and force the differential output to the state indicated by B11[1:0] (Low/Low default)
SMBus Table: PLL Operating Mode and Output Amplitude Control Register
Byte 1
Bit 7
Bit 6
Name
PLLMODERB1
PLLMODERB0
Control Function
PLL Mode Readback Bit 1
PLL Mode Readback Bit 0
Type
R
R
0
1
Default
Latch
Latch
See PLL Operating Mode Table
Values in B1[7:6]
set PLL Mode
Values in B1[4:3]
set PLL Mode
PLLMODE_SWCNTRL
Enable SW control of PLL Mode RW
0
Bit 5
RW1
RW1
PLLMODE1
PLLMODE0
PLL Mode Control Bit 1
0
0
1
1
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
See PLL Operating Mode Table
PLL Mode Control Bit 0
Reserved
RW
Controls Output Amplitude
RW
AMPLITUDE 1
AMPLITUDE 0
00 = 0.6V
10 = 0.75V
01= 0.68V
11 = 0.85V
1. B1[5] must be set to a 1 for these bits to have any effect on the part.
SMBus Table: DIF Slew Rate Control Register
Byte 2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Control Function
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
Default
SLEWRATESEL DIF7
SLEWRATESEL DIF6
SLEWRATESEL DIF5
SLEWRATESEL DIF4
SLEWRATESEL DIF3
SLEWRATESEL DIF2
SLEWRATESEL DIF1
SLEWRATESEL DIF0
Adjust Slew Rate of DIF7
Adjust Slew Rate of DIF6
Adjust Slew Rate of DIF5
Adjust Slew Rate of DIF4
Adjust Slew Rate of DIF3
Adjust Slew Rate of DIF2
Adjust Slew Rate of DIF1
Adjust Slew Rate of DIF0
Slow Setting
Slow Setting
Slow Setting
Slow Setting
Slow Setting
Slow Setting
Slow Setting
Slow Setting
Fast Setting
Fast Setting
Fast Setting
Fast Setting
Fast Setting
Fast Setting
Fast Setting
Fast Setting
1
1
1
1
1
1
1
1
Note: See "Low-Power HCSL Outputs" table for slew rates.
SMBus Table: Frequency Select Control Register
Byte 3
Bit 7
Bit 6
Name
Control Function
Reserved
Reserved
Enable SW selection of
frequency
Type
0
1
Default
1
1
SW frequency
change disabled
SW frequency
change enabled
FREQ_SEL_EN
RW
0
Bit 5
RW1
RW1
00 = 100M, 10 = 125M
01 = 50M, 11= Reserved
FSEL1
FSEL0
Freq. Select Bit 1
0
Bit 4
Freq. Select Bit 0
Reserved
Reserved
Adjust Slew Rate of FB
0
1
1
1
Bit 3
Bit 2
Bit 1
Bit 0
SLEWRATESEL FB
RW
Slow Setting
Fast Setting
1. B3[5] must be set to a 1 for these bits to have any effect on the part.
Byte 4 is Reserved
REVISION D 08/16/16
11
8-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER
9DBL08 DATASHEET
SMBus Table: Revision and Vendor ID Register
Byte 5
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
RID3
RID2
RID1
RID0
VID3
VID2
VID1
VID0
Control Function
Type
R
R
R
R
R
R
R
R
0
1
Default
0
0
0
1
0
0
0
1
Revision ID
B rev = 0001
0001 = IDT
VENDOR ID
SMBus Table: Device Type/Device ID
Byte 6
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Control Function
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
Default
Device Type1
Device Type0
Device ID5
Device ID4
Device ID3
Device ID2
Device ID1
Device ID0
00 = FGx, 01 = DBx ZDB/FOB,
10 = DMx, 11= DBx FOB
0
1
0
0
1
0
0
0
Device Type
Device ID
001000 binary or 08 hex
SMBus Table: Byte Count Register
Byte 7
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Control Function
Type
0
1
Default
Reserved
Reserved
Reserved
0
0
0
0
1
0
0
0
BC4
BC3
BC2
BC1
BC0
RW
RW Writing to this register will configure how
RW many bytes will be read back, default is
RW
RW
Byte Count Programming
= 8 bytes.
Bytes 8 and 9 are Reserved
SMBus Table: PD_Restore
Byte 10
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Control Function
Type
0
1
Default
Reserved
1
1
0
0
0
0
0
0
Power-Down (PD) Restore
Restore Default Config. In PD
Reserved
RW Clear Config in PD Keep Config in PD
Reserved
Reserved
Reserved
Reserved
Reserved
8-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER
12
REVISION D 08/16/16
9DBL08 DATASHEET
SMBus Table: Impedance Control
Byte 11
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
FB_imp[1]
FB_imp[0]
Control Function
Type
RW
RW
0
1
Default
00=33 DIF Zout 10=100 DIF Zout
01=85 DIF Zout
ꢀ
ꢀ
ꢀ
Feedback Zout
see Note
11 = Reserved
Reserved
Reserved
Reserved
0
0
0
0
0
0
Reserved
STP[1]
STP[0]
True/Complement DIF Output
Disable State
RW
RW
00 = Low/Low
01 = HiZ/HiZ
10 = High/Low
11 = Low/High
Note: xx41 = 10, xx51 = 01, P1 = factory programmable.
SMBus Table: Impedance Control
Byte 12
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Control Function
DIF3 Zout
DIF3 Zout
DIF2 Zout
DIF2 Zout
DIF1 Zout
DIF1 Zout
DIF0 Zout
DIF0 Zout
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
Default
DIF3_imp[1]
DIF3_imp[0]
DIF2_imp[1]
DIF2_imp[0]
DIF1_imp[1]
DIF1_imp[0]
DIF0_imp[1]
DIF0_imp[0]
00=33 DIF Zout 10=100 DIF Zout
01=85 DIF Zout
00=33 DIF Zout 10=100 DIF Zout
01=85 DIF Zout
00=33 DIF Zout 10=100 DIF Zout
01=85 DIF Zout
00=33 DIF Zout 10=100 DIF Zout
01=85 DIF Zout
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
11 = Reserved
ꢀ
11 = Reserved
see Note
ꢀ
11 = Reserved
ꢀ
11 = Reserved
Note: xx41 = 10, xx51 = 01, P1 = factory programmable.
SMBus Table: Impedance Control
Byte 13
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Control Function
DIF7 Zout
DIF7 Zout
DIF6 Zout
DIF6 Zout
DIF5 Zout
DIF5 Zout
DIF4 Zout
DIF4 Zout
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
Default
DIF7_imp[1]
DIF7_imp[0]
DIF6_imp[1]
DIF6_imp[0]
DIF5_imp[1]
DIF5_imp[0]
DIF4_imp[1]
DIF4_imp[0]
00=33 DIF Zout 10=100 DIF Zout
01=85 DIF Zout
00=33 DIF Zout 10=100 DIF Zout
01=85 DIF Zout
00=33 DIF Zout 10=100 DIF Zout
01=85 DIF Zout
00=33 DIF Zout 10=100 DIF Zout
01=85 DIF Zout
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
11 = Reserved
ꢀ
11 = Reserved
see Note
ꢀ
11 = Reserved
ꢀ
11 = Reserved
Note: xx41 = 10, xx51 = 01, P1 = factory programmable.
SMBus Table: Pull-up Pull-down Control
Byte 14
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Control Function
OE3 Pull-up(PuP)/
Pull-down(Pdwn) control
OE2 Pull-up(PuP)/
Pull-down(Pdwn) control
OE1 Pull-up(PuP)/
Pull-down(Pdwn) control
OE0 Pull-up(PuP)/
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
Default
OE3_pu/pd[1]
OE3_pu/pd[0]
OE2_pu/pd[1]
OE2_pu/pd[0]
OE1_pu/pd[1]
OE1_pu/pd[0]
OE0_pu/pd[1]
OE0_pu/pd[0]
00=None
01=Pdwn
00=None
01=Pdwn
00=None
01=Pdwn
00=None
01=Pdwn
10=Pup
11 = Pup+Pdwn
10=Pup
11 = Pup+Pdwn
10=Pup
11 = Pup+Pdwn
10=Pup
0
1
0
1
0
1
0
1
Pull-down(Pdwn) control
11 = Pup+Pdwn
Note: These values are for xx41 and xx51. P1 is factory programmable.
REVISION D 08/16/16
13
8-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER
9DBL08 DATASHEET
Byte 15
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Control Function
OE7 Pull-up(PuP)/
Pull-down(Pdwn) control
OE6 Pull-up(PuP)/
Pull-down(Pdwn) control
OE5 Pull-up(PuP)/
Pull-down(Pdwn) control
OE4 Pull-up(PuP)/
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
Default
OE7_pu/pd[1]
OE7_pu/pd0]
OE6_pu/pd[1]
OE6_pu/pd[0]
OE5_pu/pd[1]
OE5_pu/pd[0]
OE4_pu/pd[1]
OE4_pu/pd[0]
00=None
01=Pdwn
00=None
01=Pdwn
00=None
01=Pdwn
00=None
01=Pdwn
10=Pup
11 = Pup+Pdwn
10=Pup
11 = Pup+Pdwn
10=Pup
11 = Pup+Pdwn
10=Pup
0
1
0
1
0
1
0
1
Pull-down(Pdwn) control
11 = Pup+Pdwn
Note: These values are for xx41 and xx51. P1 is factory programmable.
SMBus Table: Pull-up Pull-down Control
Byte 16
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Control Function
Reserved
Type
0
1
Default
0
0
0
0
0
0
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
CKPWRGD_PD_pu/pd[1]
CKPWRGD_PD_pu/pd[0]
CKPWRGD_PD Pull-up(PuP)/ RW
00=None
01=Pdwn
10=Pup
11 = Pup+Pdwn
Pull-down(Pdwn) control
RW
Note: These values are for xx41 and xx51. P1 is factory programmable.
Bytes 17 is Reserved and and reads back 0h00.
SMBus Table: Polarity Control
Byte 18
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Control Function
Sets OE7 polarity
Sets OE6 polarity
Sets OE5 polarity
Sets OE4 polarity
Sets OE3 polarity
Sets OE2 polarity
Sets OE1 polarity
Sets OE0 polarity
Type
0
1
Default
OE7_polarity
OE6_polarity
OE5_polarity
OE4_polarity
OE3_polarity
OE2_polarity
OE1_polarity
OE0_polarity
RW Enabled when Low Enabled when High
RW Enabled when Low Enabled when High
RW Enabled when Low Enabled when High
RW Enabled when Low Enabled when High
RW Enabled when Low Enabled when High
RW Enabled when Low Enabled when High
RW Enabled when Low Enabled when High
RW Enabled when Low Enabled when High
0
0
0
0
0
0
0
0
SMBus Table: Polarity Control
Byte 19
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Name
Control Function
Type
0
1
Default
Reserved
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Determines
CKPWRGD_PD polarity
Power Down when Power Down when
Low High
CKPWRGD_PD
RW
0
Bit 0
8-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER
14
REVISION D 08/16/16
9DBL08 DATASHEET
Marking Diagrams
ICS
DBL0841BI
YYWW
COO
ICS
DBL0851BI
YYWW
COO
ICS
B8P1000I
YYWW
COO
LOT
LOT
LOT
Notes:
1. “LOT” is the lot sequence number.
2. “COO” denotes country of origin.
3. YYWW is the last two digits of the year and week that the part was assembled.
4. Line 2: truncated part number
5. “L” denotes RoHS compliant package.
6. “I” denotes industrial temperature range device.
Thermal Characteristics
TYP
VALUE
33
PARAMETER
SYMBOL
CONDITIONS
PKG
UNITS NOTES
C/W
°
C/W
°
C/W
°
C/W
°
C/W
°
C/W
°
Junction to Case
Junction to Base
1
1
1
1
1
1
θJC
θJb
2.1
37
30
27
26
Junction to Air, still air
θJA0
θ
Thermal Resistance
NDG48
Junction to Air, 1 m/s air flow
Junction to Air, 3 m/s air flow
Junction to Air, 5 m/s air flow
θJA1
θJA3
θJA5
1ePad soldered to board
REVISION D 08/16/16
15
8-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER
9DBL08 DATASHEET
Package Outline and Dimensions (NDG48). Use Option 1.
8-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER
16
REVISION D 08/16/16
9DBL08 DATASHEET
Package Outline and Dimensions (NDG48), cont. Use Option 1 EPAD
REVISION D 08/16/16
17
8-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER
9DBL08 DATASHEET
Ordering Information
Part / Order Number
9DBL0841BKILF
9DBL0841BKILFT
9DBL0851BKILF
9DBL0851BKILFT
Notes
Shipping Packaging
Trays
Package
Temperature
48-pin VFQFPN -40 to +85° C
48-pin VFQFPN -40 to +85° C
48-pin VFQFPN -40 to +85° C
48-pin VFQFPN -40 to +85° C
100Ω
Tape and Reel
Trays
Tape and Reel
85Ω
Factory configurable.
Contact IDT for
addtional information.
9DBL08P1BxxxKILF
9DBL08P1BxxxKILFT
Trays
48-pin VFQFPN -40 to +85° C
48-pin VFQFPN -40 to +85° C
Tape and Reel
“LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.
“B” is the device revision designator (will not correlate with the datasheet revision).
“xxx” is a unique factory assigned number to identify a particular default configuration.
Revision History
Rev. Initiator Issue Date Description
Page #
1. Add PCIe G1-4 Common Clock and PCIe SRIS to electrical tables
2. Update Electrical Tables to final
3. Changed '1' value in Byte 0 to indicate "Pin Control"
4. Stylistic update to block diagram
5. Minor updates to SMBus registers 0 and 1 for Readability
6. Front page text update for family consistency.
7. Removed '000' code from ordering information, updated table.
8. Updated SMBus Byte 1[1:0] description
A
B
RDW
RDW
5/312016
6/14/2016
Various
9. Update SMBUS Byte 11[1:0] description
1. Electrical Table and SMBus Updates/Corrections
2. SMBus operating frequency is now set to 500KHz max.
3. Removed duplicate Absolute Maximum Table.
4. Release to final.
Various
1.Max SMbus freq changed from 400kHz to 500kHz.
2. Page 13. Byte 11[7:6] are now renamed..
C
D
RDW
RDW
6/21/2016 3. Page 14. Byte 16 - Bits 3 and 2 are now reserved. References to
9DBL09xx devices in footnote removed.
4. Page 14. Byte 19 - Bit 1 is reserved
8/16/2016 Corrected typo in part number under Output Features.
5,13,14
1
8-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER
18
REVISION D 08/16/16
Corporate Headquarters
6024 Silver Creek Valley Road
San Jose, CA 95138 USA
www.IDT.com
Sales
Tech Support
www.idt.com/go/support
1-800-345-7015 or 408-284-8200
Fax: 408-284-2775
www.IDT.com/go/sales
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in
this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined
in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether
express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This
document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.
IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably
expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Product specification subject to change without notice. Other trademarks and service marks used herein, including protected
names, logos and designs, are the property of IDT or their respective third party owners.
Copyright ©2016 Integrated Device Technology, Inc.. All rights reserved.
相关型号：
9DBL411BGILF
Four Output Low Power Differential Fanout Buffer for PCI Express Gen1, Gen2, and QPI
IDT
9DBL411BGILFT
Four Output Low Power Differential Fanout Buffer for PCI Express Gen1, Gen2, and QPI
IDT
©2020 ICPDF网 联系我们和版权申明