9FGU0441AKLFT [IDT]
4 O/P 1.5V PCIe Gen1-2-3 Clock Generator;型号: | 9FGU0441AKLFT |
厂家: | INTEGRATED DEVICE TECHNOLOGY |
描述: | 4 O/P 1.5V PCIe Gen1-2-3 Clock Generator PC |
文件: | 总15页 (文件大小:202K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
4 O/P 1.5V PCIe Gen1-2-3 Clock Generator
w/Zo=100ohms
9FGU0441
DATASHEET
Description
Features/Benefits
The 9FGU0441 is a member of IDT's 1.5V Ultra-Low-Power
PCIe clock family with integrated output terminations
providing Zo=100Ω. The device has 4 output enables for
clock management, 2 different spread spectrum levels in
addition to spread off and 2 selectable SMBus addresses.
• Direct connection to 100ohm transmission lines; saves 16
resistors compared to standard PCIe devices
• 39mW typical power consumption; reduced thermal
concerns
• OE# pins; support DIF power management
• Programmable Slew rate for each output; allows tuning for
various line lengths
Recommended Application
• Programmable output amplitude; allows tuning for various
application environments
1.5V PCIe Gen1-2-3 clock generator
• DIF outputs blocked until PLL is locked; clean system
Output Features
• 4 - 100MHz Low-Power (LP) HCSL DIF pairs
w/Zo=100ohms
start-up
• Selectable 0%, -0.25% or -0.5% spread on DIF outputs;
reduces EMI
• 1 - 1.5V LVCMOS REF output w/Wake-On-LAN (WOL)
support
• External 25MHz crystal; supports tight ppm with 0 ppm
synthesis error
• Configuration can be accomplished with strapping pins;
SMBus interface not required for device control
Key Specifications
• Selectable SMBus addresses; multiple devices can easily
• DIF cycle-to-cycle jitter <50ps
share an SMBus segment
• DIF output-to-output skew <50ps
• DIF phase jitter is PCIe Gen1-2-3 compliant
• REF phase jitter is < 3.0ps RMS
• 3.3V tolerant SMBus interface works with legacy controllers
• Space saving 32-pin 5x5 mm VFQFPN; minimal board
space
Block Diagram
XIN/CLKIN_25
REF1.5
OSC
X2
vOE(3:0)#
DIF3
SS Capable PLL
DIF2
DIF1
vSADR
vSS_EN_tri
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
CONTROL
LOGIC
DIF0
9FGU0441 OCTOBER 18, 2016
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©2016 Integrated Device Technology, Inc.
9FGU0441 DATASHEET
Pin Configuration
32 31 30 29 28 27 26 25
GNDXTAL 1
XIN/CLKIN_25 2
X2 3
vOE2#
DIF2#
DIF2
24
23
22
21
20
19
18
VDDXTAL1.5 4
VDDREF1.5 5
vSADR/REF1.5 6
VDDA1.5
GNDA
DIF1#
DIF1
9FGU0441
GNDREF
GNDDIG
7
8
17 vOE1#
9 10 11 12 13 14 15 16
32-pin VFQFPN, 5x5 mm, 0.5mm pitch
^ prefix indicates internal 120KOhm pull up resistor
v prefix indicates internal 120KOhm pull down resistor
SMBus Address Selection Table
+
Read/Write Bit
SADR
0
1
Address
1101000
1101010
x
x
State of SADR on first application
of CKPWRGD_PD#
Power Management Table
SMBus
CKPWRGD_PD#
OE bit
DIFx
True O/P
Low
REF
OEx#
Comp. O/P
Low
Hi-Z1
Running
Low
0
1
1
X
1
0
X
0
1
Running
Low
Running
Low
1. REF is Hi-Z until the 1st assertion of CKPWRGD_PD# high. After this, when
CKPWRG_PD# is low, REF is Low.
Power Connections
Pin Number
Description
VDD
4
5
GND
1
7
XTAL Analog
REF Output
Digital Power
DIF outputs
PLL Analog
9
8, 30
15, 26
20
16, 25
21
4 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR W/ZO=100OHMS
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OCTOBER 18, 2016
9FGU0441 DATASHEET
Pin Descriptions
Pin# Pin Name
Type
GND
IN
Pin Description
GND for XTAL
1
2
GNDXTAL
XIN/CLKIN_25
Crystal input or Reference Clock input. Nominally 25MHz.
3
4
5
X2
OUT
PWR
PWR
LATCHED
I/O
Crystal output.
Power supply for XTAL, nominal 1.5V
VDD for REF output. nominal 1.5V.
VDDXTAL1.5
VDDREF1.5
6
vSADR/REF1.5
Latch to select SMBus Address/1.5V LVCMOS copy of X1/REFIN pin
7
8
9
10
11
GNDREF
GNDDIG
VDDDIG1.5
SCLK_3.3
SDATA_3.3
GND
GND
PWR
IN
Ground pin for the REF outputs.
Ground pin for digital circuitry
1.5V digital power (dirty power)
Clock pin of SMBus circuitry, 3.3V tolerant.
Data pin for SMBus circuitry, 3.3V tolerant.
Active low input for enabling DIF pair 0. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
I/O
12
vOE0#
IN
13
14
15
16
DIF0
DIF0#
GND
OUT
OUT
GND
PWR
Differential true clock output
Differential Complementary clock output
Ground pin.
Power supply for outputs, nominally 1.5V.
Active low input for enabling DIF pair 1. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
VDDO1.5
17
vOE1#
IN
18
19
20
21
22
23
DIF1
OUT
OUT
GND
PWR
OUT
OUT
Differential true clock output
Differential Complementary clock output
Ground pin for the PLL core.
1.5V power for the PLL core.
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 2. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
DIF1#
GNDA
VDDA1.5
DIF2
DIF2#
24
vOE2#
IN
25
26
27
28
VDDO1.5
GND
DIF3
PWR
GND
OUT
OUT
Power supply for outputs, nominally 1.5V.
Ground pin.
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 3. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
DIF3#
29
30
vOE3#
GND
IN
GND
Ground pin.
Input notifies device to sample latched inputs and start up on first high assertion.
Low enters Power Down Mode, subsequent high assertions exit Power Down
Mode. This pin has internal pull-up resistor.
Latched select input to select spread spectrum amount at initial power up :
1 = -0.5% spread, M = -0.25%, 0 = Spread Off
31
32
^CKPWRGD_PD#
vSS_EN_tri
IN
LATCHED IN
OCTOBER 18, 2016
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4 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR W/ZO=100OHMS
9FGU0441 DATASHEET
Test Loads
Low-Power HCSL Differential Output Test Load
5 inches
Rs
Zo=100ohm
2pF
2pF
Rs
Device
REF Output Test Load
Zo = 50 ohms
33
5pF
REF Output
Alternate Terminations
3.3V
Driving LVDS
R7a
R7b
R8b
Cc
Rs
Rs
Zo
Cc
R8a
LVDS Clock
input
Device
Driving LVDS inputs
Value
Receiver has Receiver does not
Component
R7a, R7b
R8a, R8b
Cc
termination
10K ohm
5.6K ohm
0.1 uF
have termination Note
140 ohm
75 ohm
0.1 uF
Vcm
1.2 volts
1.2 volts
4 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR W/ZO=100OHMS
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OCTOBER 18, 2016
9FGU0441 DATASHEET
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9FGU0441. These ratings, which are standard
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the
recommended operating temperature range.
PARAMETER
SYMBOL
CONDITIONS
UNITS NOTES
MIN
-0.5
-0.5
TYP
MAX
2
VDD+0.5V
Supply Voltage
Input Voltage
VDDxx
VIN
Applies to all VDD pins
V
V
1,2
1,3
Input High Voltage, SMBus
VIHSMB
Ts
Tj
SMBus clock and data pins
3.3V
150
125
V
1
1
1
1
Storage Temperature
Junction Temperature
Input ESD protection
-65
°C
°C
V
ESD prot
Human Body Model
2000
1Guaranteed by design and characterization, not 100% tested in production.
2 Operation under these conditions is neither implied nor guaranteed.
3 Not to exceed 2.5V.
Electrical Characteristics–Current Consumption
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
IDDAOP
CONDITIONS
MIN TYP MAX UNITS NOTES
VDDA, All outputs active @100MHz
6.2
9
mA
Operating Supply Current
All VDD, except VDDA and VDDIO, All outputs
active @100MHz
IDDOP
21
27
mA
IDDAPD
VDDA, DIF outputs off, REF output running
0.4
4.5
1
mA
mA
2
2
Wake-on-LAN Current
(CKPWRGD_PD# = '0'
Byte 3, bit 5 = '1')
All VDD, except VDDA and VDDIO,
DIF outputs off, REF output running
IDDPD
6.5
Powerdown Current
(CKPWRGD_PD# = '0'
Byte 3, bit 5 = '0')
IDDAPD
IDDPD
VDDA, all outputs off
0.4
0.4
1
1
mA
mA
All VDD, except VDDA and VDDIO, all outputs off
1 Guaranteed by design and characterization, not 100% tested in production.
2 This is the current required to have the REF output running in Wake-on-LAN mode (Byte 3, bit 5 = 1)
Electrical Characteristics–DIF Output Duty Cycle, Jitter, and Skew Characteristics
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS NOTES
Duty Cycle
tDC
tsk3
Measured differentially, PLL Mode
Averaging on, VT = 50%
45
50
32
16
55
50
50
%
ps
ps
1,2
1
Skew, Output to Output
Jitter, Cycle to cycle
tjcyc-cyc
1,2
1Guaranteed by design and characterization, not 100% tested in production.
2 Measured from differential waveform
OCTOBER 18, 2016
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4 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR W/ZO=100OHMS
9FGU0441 DATASHEET
Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating
Conditions
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
Supply Voltage
SYMBOL
VDDxx
CONDITIONS
MIN
TYP
1.5
MAX
UNITS NOTES
V
Supply voltage for core, analog and single-ended
LVCMOS outputs
1.425
1.575
Ambient Operating
Temperature
Comercial range
0
25
25
70
85
°C
°C
V
TAMB
Industrial range
-40
Input High Voltage
Input Mid Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
VIH
VIM
VIL
VIH
VIL
IIN
Single-ended inputs, except SMBus
Single-ended tri-level inputs ('_tri' suffix)
Single-ended inputs, except SMBus
0.75 VDD
0.4 VDD
-0.3
VDD + 0.3
0.5 VDD 0.6 VDD
0.25 VDD
V
V
Single-ended outputs, except SMBus. IOH = -2mA VDD-0.45
Single-ended outputs, except SMBus. IOL = -2mA
V
0.45
5
V
Single-ended inputs, VIN = GND, VIN = VDD
Single-ended inputs
IN = 0 V; Inputs with internal pull-up resistors
IN = VDD; Inputs with internal pull-down resistors
XTAL, or X1 input
-5
-200
23
uA
Input Current
V
IINP
200
uA
V
Input Frequency
Pin Inductance
Fin
Lpin
25
27
7
MHz
nH
pF
pF
1
1
1
CIN
Logic Inputs, except DIF_IN
Output pin capacitance
1.5
5
Capacitance
COUT
6
From VDD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
Triangular Modulation
Clk Stabilization
TSTAB
1.8
ms
1,2
SS Modulation Frequency
OE# Latency
fMOD
30
1
31.6
33
3
kHz
1
DIF start after OE# assertion
DIF stop after OE# deassertion
DIF output enable after
tLATOE#
clocks
1,3
Tdrive_PD#
tDRVPD
300
us
1,3
PD# de-assertion
Tfall
tF
Fall time of single-ended control inputs
5
ns
ns
V
2
2
Trise
tR
Rise time of single-ended control inputs
5
SMBus Input Low Voltage
SMBus Input High Voltage
VILSMB
VIHSMB
0.6
3.3
0.4
VDDSMB = 3.3V, see note 4 for VDDSMB < 3.3V
2.1
V
4
SMBus Output Low Voltage VOLSMB
@ IPULLUP
@ VOL
V
SMBus Sink Current
Nominal Bus Voltage
SCLK/SDATA Rise Time
IPULLUP
VDDSMB
tRSMB
4
mA
V
1.425
3.3
1000
300
(Max VIL - 0.15) to (Min VIH + 0.15)
(Min VIH + 0.15) to (Max VIL - 0.15)
ns
ns
1
1
SCLK/SDATA Fall Time
SMBus Operating
Frequency
tFSMB
fMAXSMB
Maximum SMBus operating frequency
400
kHz
1
1 Guaranteed by design and characterization, not 100% tested in production.
2 Control input must be monotonic from 20% to 80% of input swing.
3 Time from deassertion until outputs are >200 mV
4 For VDDSMB < 3.3V, VIHSMB >= 0.8xVDDSMB
4 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR W/ZO=100OHMS
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OCTOBER 18, 2016
9FGU0441 DATASHEET
Electrical Characteristics–DIF Low-Power HCSL Outputs
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP MAX UNITS NOTES
V/ns
V/ns
%
Scope averaging on fast setting
Scope averaging on slow setting
Slew rate matching, Scope averaging on
1.2
0.8
2.4
1.7
9
3.6
2.5
20
1,2,3
1,2,3
1,2,4
Slew rate
Trf
Slew rate matching
Voltage High
ΔTrf
Statistical measurement on single-ended signal
using oscilloscope math function. (Scope
averaging on)
VHIGH
600
750
26
850
7
7
mV
Voltage Low
VLOW
-150
150
Max Voltage
Min Voltage
Vswing
Crossing Voltage (abs)
Vmax
Vmin
Vswing
Measurement on single ended signal using
absolute value. (Scope averaging off)
763
22
1448
390
11
1150
7
7
mV
-300
300
250
Scope averaging off
Scope averaging off
Scope averaging off
mV
mV
mV
1,2,7
1,5,7
1,6,7
Vcross_abs
550
140
Crossing Voltage (var)
Δ-Vcross
1Guaranteed by design and characterization, not 100% tested in production.
2 Measured from differential waveform
3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on
the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations.
5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising
edge (i.e. Clock rising and Clock# falling).
6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross
absolute) allowed. The intent is to limit Vcross induced modulation by setting Δ-Vcross to be smaller than Vcross absolute.
7 At default SMBus amplitude settings.
Electrical Characteristics–DIF Output Phase Jitter Parameters
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
IND.
LIMIT
86
PARAMETER
SYMBOL
tjphPCIeG1
CONDITIONS
MIN TYP MAX
UNITS Notes
ps (p-p) 1,2,3,5
PCIe Gen 1
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
27.7
1.0
40
ps
1.3
3
3.1
1
1,2,3,5
(rms)
tjphPCIeG2
PCIe Gen 2 High Band
ps
2.2
0.6
1.9
0.4
1,2,3,5
(rms)
1.5MHz < f < Nyquist (50MHz)
PCIe Gen 3 Common Clock Architecture
(PLL BW of 2-4 or 2-5MHz, CDR = 10MHz)
Phase Jitter, PLL Mode
ps
tjphPCIeG3
1,2,3,5
(rms)
tjphPCIeG3SRn
PCIe Gen 3 Separate Reference No Spread (SRnS)
(PLL BW of 2-4 or 2-5MHz, CDR = 10MHz)
ps
0.6
0.7
0.4
1,2,3,5
(rms)
S
1 Guaranteed by design and characterization, not 100% tested in production.
2 See http://www.pcisig.com for complete specs
3 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.
4 Calculated from Intel-supplied Clock Jitter Tool
5 Applies to all differential outputs
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4 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR W/ZO=100OHMS
9FGU0441 DATASHEET
Electrical Characteristics–REF
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
Long Accuracy
SYMBOL
ppm
CONDITIONS
see Tperiod min-max values
MIN
TYP
0
MAX
UNITS Notes
ppm
1,2
Clock period
Rise/Fall Slew Rate
Rise/Fall Slew Rate
Rise/Fall Slew Rate
Rise/Fall Slew Rate
Duty Cycle
Tperiod
trf1
25 MHz output
40
0.7
1.0
1.3
1.4
47.1
2.0
ns
2
Byte 3 = 1F, 20% to 80% of VDDREF
Byte 3 = 5F, 20% to 80% of VDDREF
Byte 3 = 9F, 20% to 80% of VDDREF
Byte 3 = DF, 20% to 80% of VDDREF
VT = VDD/2 V
0.3
0.5
0.77
0.84
45
1.1
1.6
1.9
2.0
55
V/ns
V/ns
V/ns
V/ns
%
1
trf1
1,3
1
trf1
trf1
1
dt1X
dtcd
1,4
1,5
Duty Cycle Distortion
VT = VDD/2 V, when driven by XIN/CLKIN_25 pin
0
4
%
Jitter, cycle to cycle
Noise floor
tjcyc-cyc
tjdBc1k
VT = VDD/2 V
1kHz offset
51.2
-126
-139
250
-105
-110
ps
1,4
1,4
1,4
dBc
Noise floor
tjdBc10k
10kHz offset to Nyquist
dBc
ps
(rms)
Jitter, phase
tjphREF
12kHz to 5MHz
1.11
3
1,4
1Guaranteed by design and characterization, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is trimmed to 25.00 MHz
3 Default SMBus Value
4 When driven by a crystal.
5 X2 should be floating.
Clock Periods–Differential Outputs with Spread Spectrum Disabled
Measurement Window
1 Clock
1us
-SSC
0.1s
- ppm
0.1s
0.1s
+ ppm
Long-Term Short-Term
Average
Max
1us
+SSC
1 Clock
Center
Freq.
MHz
SSC OFF
-c2c jitter
AbsPer
Min
0 ppm
Period
Nominal
+c2c jitter Units Notes
AbsPer
Max
Short-Term Long-Term
Average
Min
Average
Min
Average
Max
DIF
100.00
9.94900
9.99900
10.00000
10.00100
10.05100
ns
1,2
Clock Periods–Differential Outputs with -0.5% Spread Spectrum Enabled
Measurement Window
1 Clock
1us
-SSC
0.1s
- ppm
0.1s
0.1s
+ ppm
Long-Term Short-Term
Average
Max
1us
+SSC
1 Clock
Center
Freq.
MHz
SSC ON
-c2c jitter
AbsPer
Min
0 ppm
Period
Nominal
+c2c jitter Units Notes
AbsPer
Max
Short-Term Long-Term
Average
Min
Average
Min
Average
Max
DIF
99.75
9.94906
9.99906
10.02406
10.02506
10.02607
10.05107
10.10107
ns
1,2
1Guaranteed by design and characterization, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is trimmed to 25.00 MHz
4 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR W/ZO=100OHMS
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OCTOBER 18, 2016
9FGU0441 DATASHEET
General SMBus Serial Interface Information
How to Write
How to Read
• Controller (host) sends a start bit
• Controller (host) sends the write address
• IDT clock will acknowledge
• Controller (host) will send a start bit
• Controller (host) sends the write address
• IDT clock will acknowledge
• Controller (host) sends the beginning byte location = N
• IDT clock will acknowledge
• Controller (host) sends the beginning byte location = N
• IDT clock will acknowledge
• Controller (host) sends the byte count = X
• IDT clock will acknowledge
• Controller (host) starts sending Byte N through Byte
N+X-1
• Controller (host) will send a separate start bit
• Controller (host) sends the read address
• IDT clock will acknowledge
• IDT clock will send the data byte count = X
• IDT clock sends Byte N+X-1
• IDT clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
• IDT clock sends Byte 0 through Byte X (if X was
written to Byte 8)
(H)
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Write Operation
Index Block Read Operation
Controller (Host)
IDT (Slave/Receiver)
Controller (Host)
starT bit
IDT (Slave/Receiver)
T
starT bit
T
Slave Address
Slave Address
WRite
WR
WRite
WR
ACK
ACK
ACK
ACK
ACK
ACK
Beginning Byte = N
Data Byte Count = X
Beginning Byte N
Beginning Byte = N
RT
Repeat starT
Slave Address
ReaD
RD
ACK
O
O
O
O
O
O
Data Byte Count=X
Beginning Byte N
ACK
ACK
Byte N + X - 1
ACK
O
O
O
P
stoP bit
O
O
O
Note: Read/Write address is determined by SADR latch.
Byte N + X - 1
N
P
Not acknowledge
stoP bit
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4 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR W/ZO=100OHMS
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SMBus Table: Output Enable Register
Byte 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Control Function
Reserved
Type
0
1
Default
1
1
1
1
1
1
1
1
Reserved
Reserved
Reserved
DIF OE3
DIF OE3
DIF OE2
DIF OE1
Output Enable
RW
RW
RW
RW
Low/Low
Low/Low
Low/Low
Low/Low
Enabled
Enabled
Enabled
Enabled
Output Enable
Output Enable
Output Enable
SMBus Table: SS Readback and Vhigh Control Register
Byte 1
Bit 7
Bit 6
Name
SSENRB1
SSENRB1
Control Function
SS Enable Readback Bit1
SS Enable Readback Bit0
Type
R
R
0
1
Default
Latch
Latch
00' for SS_EN_tri = 0, '01' for SS_EN_tri
= 'M', '11 for SS_EN_tri = '1'
Values in B1[4:3]
SS control locked
SSEN_SWCNTRL
Enable SW control of SS
RW
0
Bit 5
control SS amount.
RW1
RW1
SSENSW1
SSENSW0
SS Enable Software Ctl Bit1
SS Enable Software Ctl Bit0
Reserved
00' = SS Off, '01' = -0.25% SS,
'10' = Reserved, '11'= -0.5% SS
0
Bit 4
0
1
1
0
Bit 3
Bit 2
Bit 1
Bit 0
AMPLITUDE 1
AMPLITUDE 0
RW
RW
00 = 0.55V
10= 0.7V
01 = 0.65V
11 = 0.8V
Controls Output Amplitude
1. B1[5] must be set to a 1 for these bits to have any effect on the part.
SMBus Table: DIF Slew Rate Control Register
Byte 2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Control Function
Reserved
Type
0
1
Default
1
1
1
1
1
1
1
1
Reserved
Reserved
Reserved
SLEWRATESEL DIF3
SLEWRATESEL DIF2
SLEWRATESEL DIF1
SLEWRATESEL DIF0
Adjust Slew Rate of DIF3
Adjust Slew Rate of DIF2
Adjust Slew Rate of DIF3
Adjust Slew Rate of DIF1
RW
RW
RW
RW
Slow Setting
Slow Setting
Slow Setting
Slow Setting
Fast Setting
Fast Setting
Fast Setting
Fast Setting
SMBus Table: REF Control Register
Byte 3
Bit 7
Bit 6
Name
Control Function
Type
RW
RW
0
1
Default
00 = Slowest
10 = Fast
01 = Slow
11 = Faster
0
1
REF
Slew Rate Control
REF does not run in REF runs in Power
REF Power Down Function
REF OE
Wake-on-Lan Enable for REF
REF Output Enable
RW
RW
0
Bit 5
Power Down
Low
Down
Enabled
1
1
1
1
1
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
Reserved
Byte 4 is reserved and reads back 'hFF'.
4 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR W/ZO=100OHMS
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9FGU0441 DATASHEET
SMBus Table: Revision and Vendor ID Register
Byte 5
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
RID3
RID2
RID1
RID0
VID3
VID2
VID1
VID0
Control Function
Type
R
R
R
R
R
R
R
R
0
1
Default
0
0
0
0
0
0
0
1
Revision ID
A rev = 0000
0001 = IDT
VENDOR ID
SMBus Table: Device Type/Device ID
Byte 6
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Control Function
Type
R
R
R
R
R
R
R
R
0
1
Default
Device Type1
Device Type0
Device ID5
Device ID4
Device ID3
Device ID2
Device ID1
Device ID0
00 = FGx, 01 = DBx ZDB/FOB,
10 = DMx, 11= DBx FOB
0
0
0
0
0
1
0
0
Device Type
Device ID
000100 binary or 04 hex
SMBus Table: Byte Count Register
Byte 7
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Control Function
Type
0
1
Default
Reserved
Reserved
Reserved
0
0
0
0
1
0
0
0
BC4
BC3
BC2
BC1
BC0
RW
RW Writing to this register will configure how
RW many bytes will be read back, default is
RW
RW
Byte Count Programming
= 8 bytes.
Recommended Crystal Characteristics (3225 package)
PARAMETER
VALUE
UNITS
NOTES
Frequency
Resonance Mode
25
MHz
-
1
1
1
Fundamental
Frequency Tolerance @ 25°C
Frequency Stability, ref @ 25°C Over
Operating Temperature Range
Temperature Range (commerical)
Temperature Range (industrial)
Equivalent Series Resistance (ESR)
Shunt Capacitance (CO)
20
±
PPM Max
20
±
PPM Max
1
C
°
C
°
0~70
-40~85
50
1
2
1
1
Ω
Max
7
pF Max
Load Capacitance (CL)
Drive Level
8
0.3
±5
pF Max
mW Max
PPM Max
1
1
1
Aging per year
Notes:
1. FOX 603-25-150.
2. For I-temp, FOX 603-25-261.
OCTOBER 18, 2016
11
4 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR W/ZO=100OHMS
9FGU0441 DATASHEET
Thermal Characteristics
PARAMETER
SYMBOL
CONDITIONS
Junction to Case
PKG
TYP.
42
UNITS
NOTES
C/W
°
C/W
°
C/W
°
C/W
°
C/W
°
C/W
°
1
1
1
1
1
1
θJC
θJb
θJA0
θJA1
θJA3
θJA5
Junction to Base
2.4
39
Junction to Air, still air
Junction to Air, 1 m/s air flow
Junction to Air, 3 m/s air flow
Junction to Air, 5 m/s air flow
Thermal Resistance
NLG32
33
28
27
1ePad soldered to board
Marking Diagrams
ICS
GU0441AL
YYWW
COO
ICS
U0441AIL
YYWW
COO
LOT
LOT
Notes:
1. “LOT” is the lot number.
2. “COO” denotes the country of origin.
3. “YYWW” is the last two digits of the year and week that the part was assembled.
4. Line 2: truncated part number.
5. “L” denotes RoHS compliant package.
6. “I” denotes industrial temperature grade.
4 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR W/ZO=100OHMS
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OCTOBER 18, 2016
9FGU0441 DATASHEET
Package Outline and Package Dimensions (NLG32)
(Ref)
ND & NE
Even
Seating Plane
(ND-1)x
(Ref)
e
A1
Index Area
(Typ)
If ND & NE
are Even
L
A3
e
2
N
1
2
N
Anvil
Singulation
1
2
(NE-1)x
(Ref)
e
-- or --
E2
E
E2
2
Sawn
Singulation
Top View
b
A
C
(Ref)
ND & NE
Odd
e
Thermal Base
D
D2
2
C
D2
0.08
Millimeters
Symbol
Min
0.8
0
Max
1.0
A
A1
0.05
A3
0.20 Reference
0.18 0.3
0.50 BASIC
5.00 x 5.00
b
e
D x E BASIC
D2 MIN./MAX.
E2 MIN./MAX.
L MIN./MAX.
N
3.00
3.30
3.30
0.50
3.00
0.30
32
8
ND
NE
8
Ordering Information
Part / Order Number Shipping Packaging
Package
Temperature
0 to +70° C
0 to +70° C
-40 to +85° C
-40 to +85° C
9FGU0441AKLF
9FGU0441AKLFT
9FGU0441AKILF
9FGU0441AKILFT
Trays
Tape and Reel
Trays
32-pin VFQFPN
32-pin VFQFPN
32-pin VFQFPN
32-pin VFQFPN
Tape and Reel
“LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.
“A” is the device revision designator (will not correlate with the datasheet revision).
OCTOBER 18, 2016
13
4 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR W/ZO=100OHMS
9FGU0441 DATASHEET
Revision History
Rev.
Issue Date Intiator Description
Page #
1. Updated electrical tables with latest versions for release.
2. Updated SMBus nomenclature for consistency with the family.
3. Removed references to Suspend Mode. This is replaced by Power
Down with Wake-on-LAN Modes in the current consumption table.
4. Updated GenDes tab for front page consistency.
5. All Electrical tables updated with characterization data.
6. Updated doc with latest template.
A
9/24/2014
RDW
Various
7. Move to final.
B
10/18/2016
RDW Removed IDT crystal part number
4 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR W/ZO=100OHMS
14
OCTOBER 18, 2016
Corporate Headquarters
6024 Silver Creek Valley Road
San Jose, CA 95138 USA
Sales
Tech Support
email: clocks@idt.com
1-800-345-7015 or 408-284-8200
Fax: 408-284-2775
www.IDT.com
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in
this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined
in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether
express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This
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