9SQL4958BNDGI8 [IDT]
8-output CK420BQ Derivative;
| 型号： | 9SQL4958BNDGI8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 8-output CK420BQ Derivative |
| 文件： | 总20页 (文件大小：318K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
8-output CK420BQ Derivative
9SQL4958
DATASHEET
Description
Features/Benefits
The 9SQL4958 is a member of IDT's 'Lite' family of server
clocks. It generates 8 100MHz outputs that exceed the
requirements of the CK420BQ CPU/SRC clocks. Each output
has its own OE# pin for clock management and supports 2
different spread spectrum levels in addition to spread off. It
also provides a copy of the 25MHz internal XO. The
9SQL4958 supports PCIe Common Clock (CC) and
Independent Reference Clock (IR) architectures.
• Direct connection to 85 transmission lines; saves 32
2
resistors and 55mm compared to standard HCSL
• 132mW typ. power consumption; eases thermal concerns
@ 1/10 the power of CK420BQ
• Contains default configuration; SMBus interface not
required for device operation
• OE# pins; support BLCK power management
• 25MHz input frequency; standard crystal frequency
• 25MHz REF output; eliminates XO from board
Recommended Application
• Pin/SMBus selectable 0%, -0.25% or -0.5% spread on
BLCK outputs; minimize EMI and phase jitter for each
application
PCIe Gen1, Gen2, Gen3, Gen4 Server Clock
Output Features
• BLCK outputs blocked until PLL is locked; clean system
• 8 -100MHz Low-power HCSL (LP-HCSL) CPU/SRC pairs
• Integrated terminations for 85Ω Zo
• 1 - 3.3V LVCMOS REF output w/Wake-On-LAN (WOL)
support
start-up
• Two selectable SMBus addresses; multiple devices can
easily share an SMBus segment
• Space saving 48-pin 6x6mm VFQFPN; minimal board
space
Key Specifications
• BCLK outputs
• Cycle-to-cycle jitter <50ps
• Output-to-output skew <50ps
• PCIe Gen1, Gen2, Gen3, Gen4 CC compliant
• PCIe Gen2, Gen3 IR compliant
• QPI/UPI compliant
• SAS12G compliant (SSC off)
• 12k-20M phase jitter <2ps rms (SSC off)
• REF output:
• Phase jitter <200fs rms (SSC off)
• ±50ppm frequency accuracy on all clocks
Block Diagram
vOE(7:0)#
8
REF
XIN/CLKIN_25
BCLK7
BCLK6
X2
SSC
BCLK5
Capable
BCLK4
PLL
vSADR
BCLK3
BCLK2
BCLK1
BCLK0
vSS_EN_tri
^CKPWRGD_PD#
Control
Logic
SDATA_3.3
SCLK_3.3
9SQL4958 OCTOBER 28, 2016
1
©2016 Integrated Device Technology, Inc.
9SQL4958 DATASHEET
Pin Configuration
48 47 46 45 44 43 42 41 40 39 38 37
vSS_EN_tri 1
GNDXTAL 2
XIN/CLKIN_25 3
X2 4
36 BCLK5#
35 BCLK5
34 vOE4#
33 BCLK4#
32 BCLK4
31 VDDIO
30 VDDA3.3
29 GNDA
VDDXTAL3.3 5
VDDREF3.3 6
vSADR/REF3.3 7
GNDREF 8
9SQL4958
connect epad to GND
GNDDIG 9
28 vOE3#
27 BCLK3#
26 BCLK3
25 vOE2#
SCLK_3.3 10
SDATA_3.3 11
VDDDIG3.3 12
13 14 15 16 17 18 19 20 21 22 23 24
48-pin VFQFPN, 6x6 mm, 0.4mm pitch
vv prefix indicates internal 60KOhm pull down resistor
v
^
prefix indicates internal 120KOhm pull down resistor
prefix indicates internal 120KOhm pull up resistor
SMBus Address Selection Table
+
Read/Write Bit
SADR
0
1
Address
1101000
1101010
x
x
State of SADR on first application
of CKPWRGD_PD#
Power Management Table3
SMBus
OE bit
BCLKx
REF
CKPWRGD_PD#
OEx# Pin
True O/P
Low1
Comp. O/P
Low1
Hi-Z2
Running
0
1
1
1
X
1
1
0
X
0
Running
Running
Disabled1
Disabled1
Disabled1
Disabled1 Disabled4
1
Running
X
Notes
1. The output state is set by B11[1:0] (Low/Low default)
2. REF is Hi-Z until the 1st assertion of CKPWRGD_PD# high. After this, when
CKPWRG_PD# is low, REF is disabled unless Byte3[5]=1, in which case REF is
running..
3. Input polarities defined at default SMBus values.
4. See SMBus description for Byte 3, bit 4
Power Connections
Pin Number
Description
VDD
VDDIO
GND
5
6
2
8
XTAL OSC
REF Power
Digital (dirty)
Power
12
9
13,21,31,39, 22,29,40,
20,38
30
BCLK outputs
PLL Analog
47
49
29
8-OUTPUT CK420BQ DERIVATIVE
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OCTOBER 28, 2016
9SQL4958 DATASHEET
Pin Descriptions
PIN #
PIN NAME
TYPE
DESCRIPTION
LATCHED Latched select input to select spread spectrum amount at initial power up :
1
vSS_EN_tri
IN
GND
IN
OUT
PWR
PWR
LATCHED
I/O
1 = -0.5% spread, M = -0.25%, 0 = Spread Off
GND for XTAL
Crystal input or Reference Clock input. Nominally 25MHz.
Crystal output.
2
3
4
5
6
GNDXTAL
XIN/CLKIN_25
X2
VDDXTAL3.3
VDDREF3.3
Power supply for XTAL, nominal 3.3V
VDD for REF output. nominal 3.3V.
7
vSADR/REF3.3
Latch to select SMBus Address/3.3V LVCMOS copy of X1/REFIN pin
8
9
GNDREF
GNDDIG
GND
GND
IN
I/O
PWR
PWR
Ground pin for the REF outputs.
Ground pin for digital circuitry
10 SCLK_3.3
Clock pin of SMBus circuitry, 3.3V tolerant.
Data pin for SMBus circuitry, 3.3V tolerant.
3.3V digital power (dirty power)
Power supply for differential outputs
Active low input for enabling output 0. This pin has an internal 120kohm pull-
down.
11 SDATA_3.3
12 VDDDIG3.3
13 VDDIO
14 vOE0#
IN
1 =disable outputs, 0 = enable outputs
True output of differential BCLK.
Complement output of differential BCLK.
Active low input for enabling output 1. This pin has an internal 120kohm pull-
down.
15 BCLK0
16 BCLK0#
OUT
OUT
17 vOE1#
IN
1 =disable outputs, 0 = enable outputs
True output of differential BCLK.
Complement output of differential BCLK.
Power supply, nominal 3.3V
Power supply for differential outputs
Ground pin.
True output of differential BCLK.
Complement output of differential BCLK.
Active low input for enabling output 2. This pin has an internal 120kohm pull-
down.
18 BCLK1
19 BCLK1#
20 VDD3.3
21 VDDIO
22 GND
OUT
OUT
PWR
PWR
GND
OUT
OUT
23 BCLK2
24 BCLK2#
25 vOE2#
IN
1 =disable outputs, 0 = enable outputs
True output of differential BCLK.
Complement output of differential BCLK.
Active low input for enabling output 3. This pin has an internal 120kohm pull-
down.
26 BCLK3
27 BCLK3#
OUT
OUT
28 vOE3#
IN
1 =disable outputs, 0 = enable outputs
Ground pin for the PLL core.
3.3V power for the PLL core.
Power supply for differential outputs
True output of differential BCLK.
Complement output of differential BCLK.
Active low input for enabling output 4. This pin has an internal 120kohm pull-
down.
29 GNDA
GND
PWR
PWR
OUT
OUT
30 VDDA3.3
31 VDDIO
32 BCLK4
33 BCLK4#
34 vOE4#
IN
1 =disable outputs, 0 = enable outputs
True output of differential BCLK.
Complement output of differential BCLK.
Active low input for enabling output 5. This pin has an internal 120kohm pull-
down.
35 BCLK5
36 BCLK5#
OUT
OUT
37 vOE5#
IN
1 =disable outputs, 0 = enable outputs
Power supply, nominal 3.3V
Power supply for differential outputs
38 VDD3.3
39 VDDIO
PWR
PWR
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8-OUTPUT CK420BQ DERIVATIVE
9SQL4958 DATASHEET
Pin Descriptions, cont.
PIN #
40 GND
41 BCLK6
42 BCLK6#
PIN NAME
TYPE
GND
OUT
OUT
DESCRIPTION
Ground pin.
True output of differential BCLK.
Complement output of differential BCLK.
Active low input for enabling output 6. This pin has an internal 120kohm pull-
down.
43 vOE6#
IN
1 =disable outputs, 0 = enable outputs
44 BCLK7
45 BCLK7#
OUT
OUT
True output of differential BCLK.
Complement output of differential BCLK.
Active low input for enabling output 7. This pin has an internal 120kohm pull-
down.
1 =disable outputs, 0 = enable outputs
46 vOE7#
IN
PWR
IN
47 VDDIO
Power supply for differential outputs
Input notifies device to sample latched inputs and start up on first high
assertion. Low enters Power Down Mode, subsequent high assertions exit
Power Down Mode. This pin has internal 120kohm pull-up resistor.
Connect to Ground.
48 ^CKPWRGD_PD#
49 EPAD
GND
Test Loads
Terminations
REF Output Test Load
Zo (Ω)
85
Rs (Ω)
0
100
7.5
Zo = 50 ohms
33
5pF
REF Output
Low-Power Differential Output Test Load
5 inches
Rs
Rs
Zo=85ohm
2pF
2pF
Note: The device can drive transmission line lengths greater
than those specified by the PCIe SIG
Alternate Terminations
The 9SQL family can easily drive LVPECL, LVDS, and CML logic. See “AN-891 Driving LVPECL, LVDS, and CML Logic with
IDT's "Universal" Low-Power HCSL Outputs” for details.
8-OUTPUT CK420BQ DERIVATIVE
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OCTOBER 28, 2016
9SQL4958 DATASHEET
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9SQL4958. These ratings, which are standard
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the
recommended operating temperature range.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
3.3V Supply Voltage
VDDxxx
Applies to all VDD pins
-0.5
3.9
V
1,2
VDD
0.5V
3.9
150
125
+
Input Voltage
VIN
-0.5
V
1, 3
Input High Voltage, SMBus
Storage Temperature
VIHSMB
Ts
Tj
SMBus clock and data pins
Human Body Model
V
°C
°C
1
1
1
-65
Junction Temperature
1
Input ESD protection
ESD prot
2500
V
Notes
1Guaranteed by design and characterization, not 100% tested in production.
2 Operation under these conditions is neither implied nor guaranteed.
3 Not to exceed 4.5V.
Electrical Characteristics–SMBus Parameters
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
SMBus Input Low Voltage
SMBus Input High Voltage
VILSMB
VIHSMB
VDDSMB = 3.3V
VDDSMB = 3.3V
@ IPULLUP
0.8
3.6
0.4
V
V
2.1
SMBus Output Low Voltage VOLSMB
V
SMBus Sink Current
Nominal Bus Voltage
SCLK/SDATA Rise Time
IPULLUP
VDDSMB
tRSMB
@ VOL
4
mA
V
2.7
3.6
1000
300
(Max VIL - 0.15) to (Min VIH + 0.15)
(Min VIH + 0.15) to (Max VIL - 0.15)
ns
ns
1
1
SCLK/SDATA Fall Time
SMBus Operating
Frequency
tFSMB
fSMBMAX
Maximum SMBus operating frequency
500
kHz
Notes
1 Guaranteed by design and characterization, not 100% tested in production.
OCTOBER 28, 2016
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8-OUTPUT CK420BQ DERIVATIVE
9SQL4958 DATASHEET
Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating
Conditions
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
VDDxxx
VDDIO
TAMB
CONDITIONS
Supply voltage for core, analog and single-ended
LVCMOS outputs.
MIN
TYP
MAX
3.465
3.465
85
UNITS NOTES
Supply Voltage
3.135
3.3
V
V
IO Supply Voltage
Ambient Operating
Temperature
Supply voltage for differential Low Power outputs.
0.9975 1.05-3.3
Industrial range
-40
25
°C
VDDx
0.3
+
Input High Voltage
Input Low Voltage
VIH
VIL
0.75 VDDx
-0.3
V
V
Single-ended inputs, except SMBus
0.25 VDDx
VDD + 0.3
Input High Voltage
Input Mid Voltage
Input Low Voltage
VIHtri
VIMtri
VILtri
IIN
0.75 VDDx
V
V
Single-ended tri-level inputs ('_tri' suffix)
0.4 VDDx 0.5 VDDx 0.6 VDDx
-0.3
-5
0.25 VDDx
5
V
Single-ended inputs, VIN = GND, VIN = VDD
Single-ended inputs
IN = 0 V; Inputs with internal pull-up resistors
uA
Input Current
V
IINP
-50
50
uA
VIN = VDD; Inputs with internal pull-down resistors
XTAL, or X1 input
Input Frequency
Pin Inductance
Fin
Lpin
25
MHz
7
5
6
nH
pF
pF
1
1
1
CIN
Logic Inputs, except DIF_IN
Output pin capacitance
1.5
Capacitance
COUT
From VDD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
(Triangular Modulation)
Clk Stabilization
TSTAB
0.35
1.8
ms
1,2
SS Modulation Frequency
OE# Latency
fMOD
30
1
31.6
2
33
3
kHz
1
DIF start after OE# assertion
DIF stop after OE# deassertion
DIF output enable after
tLATOE#
clocks
1,3
Tdrive_PD#
tDRVPD
28
300
us
1,3
PD# de-assertion
Tfall
Trise
tF
Fall time of single-ended control inputs
5
5
ns
ns
1,2
1,2
tR
Rise time of single-ended control inputs
Notes
1 Guaranteed by design and characterization, not 100% tested in production.
2 Control input must be monotonic from 20% to 80% of input swing.
3 Time from deassertion until outputs are >200 mV
8-OUTPUT CK420BQ DERIVATIVE
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OCTOBER 28, 2016
9SQL4958 DATASHEET
Electrical Characteristics–BLCK Low-Power HCSL Outputs
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS NOTES
V/ns
V/ns
mV
Scope averaging on, fast setting
Scope averaging, slow setting
Scope averaging off
2
1
250
2.7
1.9
409
14
4
3
550
140
2,3
2,3
1,4,5
1,4,9
Slew rate
Trf
Crossing Voltage (abs)
Crossing Voltage (var)
Vcross_abs
-Vcross
Scope averaging off
mV
Δ
ppm
Avg. Clock Period Accuracy
-50
0.0
+2550
2,10,13
TPERIOD_AVG
ns
Absolute Period
Includes jitter and Spread Spectrum Modulation
9.9491
10.0
16
10.1011
50
2,6
2
TPERIOD_ABS
tjcyc-cyc
Jitter, Cycle to cycle
ps
Statistical measurement on single-ended signal
using oscilloscope math function. (Scope
averaging on)
Voltage High
Voltage Low
VHIGH
VLOW
660
761
-7
850
1
1
mV
mV
-150
150
Absolute Max Voltage
Absolute Min Voltage
Duty Cycle
Slew rate matching
Skew, Output to Output
Vmax
Vmin
tDC
Measurement on single ended signal using
absolute value. (Scope averaging off)
819
-46
49.2
6
1150
1,7,15
1,8,15
2
1,14
2
-300
45
55
20
50
%
%
Trf
Δ
tsk3
Averaging on, VT = 50%
35
ps
Notes
1 Measured from single-ended waveform.
2 Measured from differential waveform.
3 Measured from -150 mV to +150 mV on the differential waveform (derived from REFCLK+ minus REFCLK-). The signal must be monotonic
through the measurement region for rise and fall time. The 300 mV measurement window is centered on the differential zero crossing.
4 Measured at crossing point where the instantaneous voltage value of the rising edge of REFCLK+ equals the falling edge of REFCLK-.
5 Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points
for this measurement.
6 Defines as the absolute minimum or maximum instantaneous period. This includes cycle to cycle jitter, relative PPM tolerance, and spread
spectrum modulation.
7 Defined as the maximum instantaneous voltage including overshoot.
8 Defined as the minimum instantaneous voltage including undershoot.
9 Defined as the total variation of all crossing voltages of Rising REFCLK+ and Falling REFCLK-. This is the maximum allowed variance in
VCROSS for any particular system.
10 Refer to Section 4.3.7.1.1 of the PCI Express Base Specification, Revision 3.0 for information regarding PPM considerations.
11 System board compliance measurements must use the test load. REFCLK+ and REFCLK- are to be measured at the load capacitors CL.
Single ended probes must be used for measurements requiring single ended measurements. Either single ended probes with math or
differential probe can be used for differential measurements. Test load CL = 2 pF.
12
T
is the time the differential clock must maintain a minimum 150 mV differential voltage after rising/falling edges before it is allowed
STABLE
to droop back into the VRB 100 mV differential range.
13 PPM refers to parts per million and is a DC absolute period accuracy specification. 1 PPM is 1/1,000,000th of 100.000000 MHz exactly or
100 Hz. For 300 PPM, then we have an error budget of 100 Hz/PPM * 300 PPM = 30 kHz. The period is to be measured with a frequency
counter with measurement window set to 100 ms or greater. The 300 PPM applies to systems that do not employ Spread Spectrum Clocking,
or that use common clock source. For systems employing Spread Spectrum Clocking, there is an additional 2,500 PPM nominal shift in
maximum period resulting from the 0.5% down spread resulting in a maximum average period specification of +2,800 PPM.
14 Matching applies to rising edge rate for REFCLK+ and falling edge rate for REFCLK-. It is measured using a 75 mV window centered on the
median cross point where REFCLK+ rising meets REFCLK- falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations. The Rise Edge Rate of REFCLK+ should be compared to the Fall Edge Rate of REFCLK-;
the maximum allowed difference should not exceed 20% of the slowest edge rate.
15 At default SMBus amplitude settings.
OCTOBER 28, 2016
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8-OUTPUT CK420BQ DERIVATIVE
9SQL4958 DATASHEET
Electrical Characteristics–Filtered Phase Jitter Parameters - PCIe Common Clocked
(CC) Architectures1, 2, 5
TAMB = over the specified operating range. Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
SPECIFICATION
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
LIMIT
tjphPCIeG1-CC
PCIe Gen 1
PCIe Gen 2 Low Band
10kHz < f < 1.5MHz
19
30
86
ps (p-p)
3
ps
(rms)
0.4
1.2
0.6
3
(PLL BW of 5-16MHz, 8-16MHz, CDR = 5MHz)
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
(PLL BW of 5-16MHz, 8-16MHz, CDR = 5MHz)
PCIe Gen 3
(PLL BW of 2-4MHz, 2-5MHz, CDR = 10MHz)
PCIe Gen 4
(PLL BW of 2-4MHz, 2-5MHz, CDR = 10MHz)
tjphPCIeG2-CC
Phase Jitter,
PLL Mode
ps
(rms)
1.9
3.1
ps
(rms)
ps
0.45
0.45
1
tjphPCIeG3-CC
tjphPCIeG4-CC
0.27
0.27
0.5
(rms)
Electrical Characteristics–Filtered Phase Jitter Parameters - PCIe Separate
Reference Independent Spread (SRIS) Architectures1, 5, 6
TAMB = over the specified operating range. Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
INDUSTRY
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
LIMIT
tjphPCIeG1-
ps
(rms)
PCIe Gen 1
n/a
None
2, 7
SRIS
tjphPCIeG2-
PCIe Gen 2
(PLL BW of 16MHz , CDR = 5MHz)
ps
2
0.7
0.5
n/a
1.2
2
(rms)
SRIS
tjphPCIeG3-
Phase Jitter, PLL
Mode
PCIe Gen 3
(PLL BW of 2-4MHz, CDR = 10MHz)
ps
2
0.65
0.7
(rms)
SRIS
tjphPCIeG4-
PCIe Gen 4
(PLL BW of 2-4MHz, CDR = 10MHz)
ps
(rms)
None
2, 7
SRIS
Notes on PCIe Filter Phase Jitter Tables
1 Applies to all differential outputs, guaranteed by design and characterization.
2 Based on PCIe Base Specification Rev4.0 version 0.7draft. See http://www.pcisig.com for latest specifications.
3 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.
4 Additive jitter for RMS values is calculated by solving for b where [b=sqrt(c 2-a2)], a is rms input jitter and c is rms total jitter.
5 Driven by 9FGL0841 or equivalent
6
IR is the new name for Separate Reference Independent Spread (SRIS) and Separate Reference no Spread (SRNS) PCIe clock
architectures.
7 According to the PCIe Base Specification Rev4.0 version 0.7 draft, the jitter transfer functions and corresponding jitter limits are not
defined for the IR clock architecture. Widely accepted industry limits using widely accepted industry filters are used to populate this
table. There are no accepted filters or limits for IR clock architectures at PCIe Gen1 or Gen4 data rates
8-OUTPUT CK420BQ DERIVATIVE
8
OCTOBER 28, 2016
9SQL4958 DATASHEET
Electrical Characteristics–Phase Jitter - QPI/UPI, SAS1, 2
TAMB = over the specified operating range. Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
SPECIFICATION
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
LIMIT
QPI & UPI
(100MHz or 133MHz, 4.8Gb/s,
6.4Gb/s 12UI)
ps
(rms)
0.13
0.2
0.5
Phase Jitter, PLL
Mode
tjphQPI_UPI
QPI & UPI
(100MHz, 8.0Gb/s, 12UI)
QPI & UPI
ps
(rms)
ps
0.10
0.08
0.15
0.12
0.3
0.2
(100MHz, 9.6Gb/s, 12UI)
(rms)
?
Phase Jitter,
SAS12G
BCLK Outputs
Notes
100MHz, SSC Off,
REF output enabled
ps
1,2
tjphSAS12G
0.50
0.55
1.2
(rms)
1 Applies to all differential outputs, guaranteed by design and characterization.
2 Calculated from Intel-supplied Clock Jitter Tool
3 For RMS values additive jitter is calculated by solving for b where [b=sqrt(c 2-a2)], a is rms input jitter and c is rms total jitter.
Electrical Characteristics–12kHz-20MHz Phase Jitter
TAMB = over the specified operating range. Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
SPECIFICATION
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
LIMIT
Phase Jitter,
12kHz-20MHz
BCLK Outputs
100MHz, SSC Off,
REF output enabled
ps
(rms)
tjph12k-20M
1.5
2
n/a
1
Notes
1 Applies to all differential outputs, guaranteed by design and characterization.
Electrical Characteristics–Current Consumption
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
IDDAOP
VDDA, All outputs active @100MHz
All other VDD, except VDDA, All outputs active
@100MHz
13
19
18
mA
IDDOP
26
mA
mA
Operating Supply Current
IDDIOOP VDDIO, All outputs active @100MHz, Zo=85ohm
31
0.9
6.5
40
1.5
9
IDDAPD
IDDPD
VDDA, BCLK outputs off, REF output on
All other VDD, except VDDA,
BCLK outputs off, REF output running
VDDIO, BCLK outputs off, REF output on,
Zo=85ohm
mA
mA
1
1
Wake-on-LAN Current
(Power down state and
Byte 3, bit 5 = '1')
IDDIOPD
0.05
0.1
mA
1
IDDAPD
IDDPD
VDDA, all outputs off
0.9
2.4
1.5
3
mA
mA
mA
Powerdown Current
(Power down state and
Byte 3, bit 5 = '0')
All other VDD, except VDDA, all outputs off
VDDIO, all outputs off, Zo=85ohm
IDDIOPD
0.05
0.1
Notes
1 This is the current required to have the REF output running in Wake-on-LAN mode (Byte 3, bit 5 = 1)
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8-OUTPUT CK420BQ DERIVATIVE
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Electrical Characteristics– REF
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
Long Accuracy
Clock period
ppm
Tperiod
VIH
see Tperiod min-max values
25 MHz output
0
40
ppm
ns
1,2
2
Output High Voltage
IOH = -2mA
0.8xVDDREF
V
0.2xVDDRE
Output Low Voltage
VIL
IOL = 2mA
V
F
Rise/Fall Slew Rate
Rise/Fall Slew Rate
Rise/Fall Slew Rate
Rise/Fall Slew Rate
Duty Cycle
trf1
trf1
Byte 3 = 1F, VOH = VDD-0.45V, VOL = 0.45V
Byte 3 = 5F, VOH = VDD-0.45V, VOL = 0.45V
Byte 3 = 9F, VOH = VDD-0.45V, VOL = 0.45V
Byte 3 = DF, VOH = VDD-0.45V, VOL = 0.45V
VT = VDD/2 V
0.5
0.9
1.3
1.7
45
0.8
1.4
2.0
2.6
49.8
0
1.1
V/ns
V/ns
V/ns
V/ns
%
1
1.9
2.7
3.5
55
1,3
1
trf1
trf1
1
dt1X
1,4
1,5
1,4
1,4
1,4
1,4
1,4
Duty Cycle Distortion
Jitter, cycle to cycle
Noise floor
dtcd
VT = VDD/2 V
-1
0
%
tjcyc-cyc
tjdBc1k
tjdBc10k
tjphREF
tjphREF
VT = VDD/2 V
70
250
-137
-140
0.2
2
ps
1kHz offset
dBc
Noise floor
10kHz offset to Nyquist
dBc
Jitter, phase
12kHz to 5MHz, SSC Off
0.13
1.5
ps (rms)
ps (rms)
Jitter, phase
12kHz to 5MHz, SSC On
Notes
1Guaranteed by design and characterization, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is trimmed to 25.00 MHz
3 Default SMBus Value
4 When driven by a crystal.
5 When driven by an external oscillator via the X1 pin, X2 should be floating.
8-OUTPUT CK420BQ DERIVATIVE
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General SMBus Serial Interface Information
How to Write
How to Read
• Controller (host) sends a start bit
• Controller (host) sends the write address
• IDT clock will acknowledge
• Controller (host) will send a start bit
• Controller (host) sends the write address
• IDT clock will acknowledge
• Controller (host) sends the beginning byte location = N
• IDT clock will acknowledge
• Controller (host) sends the beginning byte location = N
• IDT clock will acknowledge
• Controller (host) sends the byte count = X
• IDT clock will acknowledge
• Controller (host) will send a separate start bit
• Controller (host) sends the read address
• IDT clock will acknowledge
• Controller (host) starts sending Byte N through Byte
N+X-1
• IDT clock will send the data byte count = X
• IDT clock sends Byte N+X-1
• IDT clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
• IDT clock sends Byte 0 through Byte X (if X was
(H)
written to Byte 8)
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Write Operation
Index Block Read Operation
Controller (Host)
starT bit
Slave Address
IDT (Slave/Receiver)
Controller (Host)
starT bit
IDT (Slave/Receiver)
T
T
Slave Address
WR
WRite
WR
WRite
ACK
ACK
ACK
ACK
ACK
ACK
Beginning Byte = N
Data Byte Count = X
Beginning Byte N
Beginning Byte = N
RT
Repeat starT
Slave Address
ReaD
RD
ACK
O
O
O
O
O
O
Data Byte Count=X
Beginning Byte N
ACK
ACK
Byte N + X - 1
ACK
O
O
O
P
stoP bit
O
O
O
Note: SMBus Read/Write Address is Latched on SADR
pin.
Byte N + X - 1
N
P
Not acknowledge
stoP bit
OCTOBER 28, 2016
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9SQL4958 DATASHEET
SMBus Table: Output Enable Register 1
Byte 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Control Function
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
Default
BCLK OE7
BCLK OE6
BCLK OE5
BCLK OE4
BCLK OE3
BCLK OE2
BCLK OE1
BCLK OE0
Pin Control
Pin Control
Pin Control
Pin Control
Pin Control
Pin Control
Pin Control
Pin Control
1
1
1
1
1
1
1
1
See B11[1:0]
1. A low on these bits will overide the OE# pin and force the differential output to the state indicated by B11[1:0] (Low/Low default)
SMBus Table: SS Readback and Control Register
Byte 1
Bit 7
Bit 6
Name
SSENRB1
SSENRB1
Control Function
SS Enable Readback Bit1
SS Enable Readback Bit0
Type
R
R
0
1
Default
Latch
Latch
00' for SS_EN_tri = 0, '01' for SS_EN_tri
= 'M', '11 for SS_EN_tri = '1'
Values in B1[4:3]
SS control locked
SSEN_SWCNTRL
Enable SW control of SS
RW
0
Bit 5
control SS amount.
RW1
RW1
SSENSW1
SSENSW0
SS Enable Software Ctl Bit1
SS Enable Software Ctl Bit0
Reserved
00' = SS Off, '01' = -0.25% SS,
'10' = Reserved, '11'= -0.5% SS
0
Bit 4
0
X
1
0
Bit 3
Bit 2
Bit 1
Bit 0
AMPLITUDE 1
AMPLITUDE 0
RW
RW
00 = 0.6V
01= 0.68V
11 = 0.85V
Controls Output Amplitude
10 = 0.75V
1. Spread must be selected OFF or ON with the hardware latch pin. These bits should not be used to turn spread ON or OFF after
power up. These bits can be used to change the spread amount, and B1[5] must be set to a 1 for these bits to have any effect on
the part. If These bits are used to turn spread OFF or ON, the system will need to be reset.
SMBus Table: BCLK Slew Rate Control Register
Byte 2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Control Function
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
Default
SLEWRATESEL BCLK7
SLEWRATESEL BCLK6
SLEWRATESEL BCLK5
SLEWRATESEL BCLK4
SLEWRATESEL BCLK3
SLEWRATESEL BCLK2
SLEWRATESEL BCLK1
SLEWRATESEL BCLK0
Adjust Slew Rate of BCLK7
Adjust Slew Rate of BCLK6
Adjust Slew Rate of BCLK5
Adjust Slew Rate of BCLK4
Adjust Slew Rate of BCLK3
Adjust Slew Rate of BCLK2
Adjust Slew Rate of BCLK1
Adjust Slew Rate of BCLK0
Slow Setting
Slow Setting
Slow Setting
Slow Setting
Slow Setting
Slow Setting
Slow Setting
Slow Setting
Fast Setting
Fast Setting
Fast Setting
Fast Setting
Fast Setting
Fast Setting
Fast Setting
Fast Setting
1
1
1
1
1
1
1
1
Note: See "Low-Power HCSL Outputs" table for slew rates.
SMBus Table: Nominal Vhigh Amplitude Control/ REF Control Register
Byte 3
Bit 7
Bit 6
Name
Control Function
Type
RW
RW
0
1
01 =Slow
11 = Fastest
REF runs in Power
Down
Default
00 = Slowest
10 = Fast
REF disabled in
Power Down
Disabled1
0
1
REF
Slew Rate Control
REF Power Down Function Wake-on-Lan Enable for REF
REF OE REF Output Enable
Reserved
RW
RW
0
Bit 5
Enabled
1
X
X
X
X
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
1. The disabled state depends on Byte11[1:0]. '00' = Low, '01'=HiZ, '10'=Low, '11'=HIgh
Byte 4 is Reserved
8-OUTPUT CK420BQ DERIVATIVE
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SMBus Table: Revision and Vendor ID Register
Byte 5
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
RID3
RID2
RID1
RID0
VID3
VID2
VID1
VID0
Control Function
Type
R
R
R
R
R
R
R
R
0
1
Default
0
0
0
1
0
0
0
1
Revision ID
B rev = 0001
0001 = IDT
VENDOR ID
SMBus Table: Device Type/Device ID
Byte 6
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Control Function
Type
R
R
R
R
R
R
R
R
0
1
Default
Device Type1
Device Type0
Device ID5
Device ID4
Device ID3
Device ID2
Device ID1
Device ID0
0
0
0
0
1
0
0
0
Device Type
00 = 9SQL49xx
Device ID
001000 binary or 08 hex
SMBus Table: Byte Count Register
Byte 7
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Control Function
Type
0
1
Default
Reserved
Reserved
Reserved
X
X
X
0
1
0
0
0
BC4
BC3
BC2
BC1
BC0
RW
RW Writing to this register will configure how
RW many bytes will be read back, default is
RW
RW
Byte Count Programming
= 8 bytes.
Bytes 8 and 9 are Reserved.
SMBus Table: PLL MN Enable, PD_Restore
Byte 10
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
PLL M/N En
Control Function
M/N Programming Enable
Type
0
1
Default
RW M/N Prog. Disabled M/N Prog. Enabled
RW Clear Config in PD Keep Config in PD
0
1
Power-Down (PD) Restore Restore Default Config. In PD
Reserved
Reserved
Reserved
Reserved
Reserved
X
X
X
X
X
X
Reserved
SMBus Table: Stop State Control
Byte 11
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Control Function
Reserved
Type
0
1
Default
X
X
X
X
X
X
0
Reserved
Reserved
Reserved
Reserved
Reserved
STP[1]
STP[0]
True/Complement BCLK Output RW
Disable State RW
00 = Low/Low
01 = HiZ/HiZ
10 = High/Low
11 = Low/High
0
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SMBus Table: Impedance Control
Byte 12
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Control Function
BCLK3 Zo
BCLK3 Zo
BCLK2 Zo
BCLK2 Zo
BCLK1 Zo
BCLK1 Zo
BCLK0 Zo
BCLK0 Zo
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
Default
BCLK3_imp[1]
BCLK3_imp[0]
BCLK2_imp[1]
BCLK2_imp[0]
BCLK1_imp[1]
BCLK1_imp[0]
BCLK0_imp[1]
BCLK0_imp[0]
00=33 ohm Zo
01=85 ohm Zo
00=33 ohm Zo
01=85 ohm Zo
00=33 ohm Zo
01=85 ohm Zo
00=33 ohm Zo
01=85 ohm Zo
10=100 ohm Zo
11 = Reserved
10=100 ohm Zo
11 = Reserved
10=100 ohm Zo
11 = Reserved
10=100 ohm Zo
11 = Reserved
see Note
SMBus Table: Impedance Control
Byte 13
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Control Function
BCLK7 Zo
BCLK7 Zo
BCLK6 Zo
BCLK6 Zo
BCLK5 Zo
BCLK5 Zo
BCLK4 Zo
BCLK4 Zo
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
Default
BCLK7_imp[1]
BCLK7_imp[0]
BCLK6_imp[1]
BCLK6_imp[0]
BCLK5_imp[1]
BCLK5_imp[0]
BCLK4_imp[1]
BCLK4_imp[0]
00=33 ohm Zo
01=85 ohm Zo
00=33 ohm Zo
01=85 ohm Zo
00=33 ohm Zo
01=85 ohm Zo
00=33 ohm Zo
01=85 ohm Zo
10=100 ohm Zo
11 = Reserved
10=100 ohm Zo
11 = Reserved
10=100 ohm Zo
11 = Reserved
10=100 ohm Zo
11 = Reserved
see Note
SMBus Table: Pull-up Pull-down Control
Byte 14
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Control Function
OE3 Pull-up(PuP)/
Pull-down(Pdwn) control
OE2 Pull-up(PuP)/
Pull-down(Pdwn) control
OE1 Pull-up(PuP)/
Pull-down(Pdwn) control
OE0 Pull-up(PuP)/
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
Default
OE3_pu/pd[1]
OE3_pu/pd[0]
OE2_pu/pd[1]
OE2_pu/pd[0]
OE1_pu/pd[1]
OE1_pu/pd[0]
OE0_pu/pd[1]
OE0_pu/pd[0]
00=None
01=Pdwn
00=None
01=Pdwn
00=None
01=Pdwn
00=None
01=Pdwn
10=Pup
11 = Pup+Pdwn
10=Pup
11 = Pup+Pdwn
10=Pup
11 = Pup+Pdwn
10=Pup
0
1
0
1
0
1
0
1
Pull-down(Pdwn) control
11 = Pup+Pdwn
SMBus Table: Pull-up Pull-down Control
Byte 15
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Control Function
OE7 Pull-up(PuP)/
Pull-down(Pdwn) control
OE6 Pull-up(PuP)/
Pull-down(Pdwn) control
OE5 Pull-up(PuP)/
Pull-down(Pdwn) control
OE4 Pull-up(PuP)/
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
Default
OE7_pu/pd[1]
OE7_pu/pd0]
OE6_pu/pd[1]
OE6_pu/pd[0]
OE5_pu/pd[1]
OE5_pu/pd[0]
OE4_pu/pd[1]
OE4_pu/pd[0]
00=None
01=Pdwn
00=None
01=Pdwn
00=None
01=Pdwn
00=None
01=Pdwn
10=Pup
11 = Pup+Pdwn
10=Pup
11 = Pup+Pdwn
10=Pup
11 = Pup+Pdwn
10=Pup
0
1
0
1
0
1
0
1
Pull-down(Pdwn) control
11 = Pup+Pdwn
SMBus Table: Pull-up Pull-down Control
Byte 16
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Control Function
Type
0
1
Default
Reserved
X
X
X
X
X
X
1
Reserved
Reserved
Reserved
Reserved
Reserved
CKPWRGD_PD_pu/pd[1] CKPWRGD_PD Pull-up(PuP)/ RW
CKPWRGD_PD_pu/pd[0] Pull-down(Pdwn) control RW
00=None
01=Pdwn
10=Pup
11 = Pup+Pdwn
0
Bytes 17 is Reserved
8-OUTPUT CK420BQ DERIVATIVE
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SMBus Table: Polarity Control
Byte 18
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Control Function
Sets OE7 polarity
Sets OE6 polarity
Sets OE5 polarity
Sets OE4 polarity
Sets OE3 polarity
Sets OE2 polarity
Sets OE1 polarity
Sets OE0 polarity
Type
0
1
Default
OE7_polarity
OE6_polarity
OE5_polarity
OE4_polarity
OE3_polarity
OE2_polarity
OE1_polarity
OE0_polarity
RW Enabled when Low Enabled when High
RW Enabled when Low Enabled when High
RW Enabled when Low Enabled when High
RW Enabled when Low Enabled when High
RW Enabled when Low Enabled when High
RW Enabled when Low Enabled when High
RW Enabled when Low Enabled when High
RW Enabled when Low Enabled when High
0
0
0
0
0
0
0
0
SMBus Table: Polarity Control
Byte 19
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Name
Control Function
Type
0
1
Default
Reserved
X
X
X
X
X
X
X
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Determines
CKPWRGD_PD polarity
Power Down when Power Down when
Low High
CKPWRGD_PD
RW
0
Bit 0
OCTOBER 28, 2016
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9SQL4958 DATASHEET
Recommended Crystal Characteristics (3225 package)
PARAMETER
VALUE
UNITS
NOTES
Frequency
Resonance Mode
25
MHz
-
1
1
1
Fundamental
Frequency Tolerance @ 25°C
Frequency Stability, ref @ 25°C Over
Operating Temperature Range
Temperature Range (commerical)
Temperature Range (industrial)
Equivalent Series Resistance (ESR)
Shunt Capacitance (CO)
20
±
PPM Max
20
±
PPM Max
1
C
°
C
°
0~70
-40~85
50
1
1
1
1
Ω
Max
7
pF Max
Load Capacitance (CL)
Drive Level
8
0.3
±5
pF Max
mW Max
PPM Max
1
1
1
Aging per year
Marking Diagram
IDT9SQL4
958BNDGI
YYWW$
LOT
Notes:
1. “YYWW” is the last two digits of the year and week that the part was assembled.
2. “$” denotes the mark code.
3. “I” denotes industrial temperature range device.
4. “LOT” is the lot sequence number.
Thermal Characteristics
PARAMETER
SYMBOL
CONDITIONS
Junction to Case
PKG
TYP.
33
UNITS
NOTES
C/W
°
°
1
1
1
1
1
1
θJC
θJb
θJA0
θJA1
θJA3
θJA5
C/W
Junction to Base
2.1
37
C/W
Junction to Air, still air
Junction to Air, 1 m/s air flow
Junction to Air, 3 m/s air flow
Junction to Air, 5 m/s air flow
°
°
°
°
Thermal Resistance
NDG48
C/W
C/W
C/W
30
27
26
1ePad soldered to board
8-OUTPUT CK420BQ DERIVATIVE
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9SQL4958 DATASHEET
Package Outline and Dimensions (NDG48)
OCTOBER 28, 2016
17
8-OUTPUT CK420BQ DERIVATIVE
9SQL4958 DATASHEET
Package Outline and Dimensions (NDG48), cont.
8-OUTPUT CK420BQ DERIVATIVE
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9SQL4958 DATASHEET
Ordering Information
Part / Order Number Shipping Packaging
Package
Temperature
9SQL4958BNDGI
9SQL4958BNDGI8
Trays
Tape and Reel
48-pin VFQFPN -40 to +85° C
48-pin VFQFPN -40 to +85° C
“G” suffix to the part number are the Pb-Free configuration and are RoHS compliant.
“B” is the device revision designator (will not correlate with the datasheet revision).
Revision History
Rev.
Issue Date Intiator Description
1. Updated electrical tables per PCIe Base Spec 4.0v7 of Oct. 2016
Page #
to add PCIe Gen4 CC and PCIe Gen2-3 IR to the data sheet.
2. Separated PCIe and QPI/UPI, SAS electrical tables
3. Updated front page text for clarity
4. Added note about hardware latching Spread Spectrum versus
software control of on/off to Byte 1.
A
10/28/2016
RDW
Various
5. Updated block diagram for formatting, and test loads
6. Removed IDT Crystal Part numbers from DS.
7. Changed pin name of DIF outputs to BCLK to better indicate
usage
OCTOBER 28, 2016
19
8-OUTPUT CK420BQ DERIVATIVE
Corporate Headquarters
6024 Silver Creek Valley Road
San Jose, CA 95138 USA
www.idt.com
Sales
Tech Support
www.idt.com/go/support
1-800-345-7015 or 408-284-8200
Fax: 408-284-2775
www.idt.com/go/sales
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in
this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined
in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether
express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This
document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.
IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably
expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Product specification subject to change without notice. Other trademarks and service marks used herein, including protected
names, logos and designs, are the property of IDT or their respective third party owners.
Copyright ©2016 Integrated Device Technology, Inc.. All rights reserved.
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