ADC1212D065HN/C1
更新时间：2024-09-18 18:22:20
品牌：IDT
描述：PROPRIETARY METHOD ADC, PQCC64, 9 X 9 MM, 0.85 MM HEIGHT, PLASTIC, SOT804-3, VQFN-64
概述
规格参数
数据手册ADC1212D065HN/C1 概述
PROPRIETARY METHOD ADC, PQCC64, 9 X 9 MM, 0.85 MM HEIGHT, PLASTIC, SOT804-3, VQFN-64 模数转换器
ADC1212D065HN/C1 规格参数
| 生命周期： | Obsolete | 零件包装代码： | QFN |
| 包装说明： | , | 针数： | 64 |
| Reach Compliance Code： | unknown | 风险等级： | 5.57 |
| 转换器类型： | ADC, PROPRIETARY METHOD | JESD-30 代码： | S-PQCC-N64 |
| 端子数量： | 64 | 输出位码： | OFFSET BINARY |
| 封装主体材料： | PLASTIC/EPOXY | 封装形状： | SQUARE |
| 封装形式： | CHIP CARRIER | 认证状态： | Not Qualified |
| 表面贴装： | YES | 端子形式： | NO LEAD |
| 端子位置： | QUAD | Base Number Matches： | 1 |
ADC1212D065HN/C1 数据手册
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PDF下载ADC1212D series
Dual 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps;
CMOS or LVDS DDR digital outputs
Rev. 01 — 6 August 2010
Preliminary data sheet
1. General description
The ADC1212D is a dual channel 12-bit Analog-to-Digital Converter (ADC) optimized for
high dynamic performances and low power consumption at sample rates up to 125 Msps.
Pipelined architecture and output error correction ensure the ADC1212D is accurate
enough to guarantee zero missing codes over the entire operating range. Supplied from a
single 3 V source, it can handle output logic levels from 1.8 V to 3.3 V in
Complementary Metal Oxide Semiconductor (CMOS) mode, because of a separate digital
output supply. It supports the Low Voltage Differential Signalling (LVDS) Double Data Rate
(DDR) output standard. An integrated Serial Peripheral Interface (SPI) allows the user to
easily configure the ADC. The device also includes an SPI programmable full-scale to
allow a flexible input voltage range of 1 V to 2 V (peak-to-peak). With excellent dynamic
performance from the baseband to input frequencies of 170 MHz or more, the ADC1212D
is ideal for use in communications, imaging and medical applications.
2. Features and benefits
SNR, 70.5 dBFS
Input bandwidth, 600 MHz
SFDR, 86 dBc
Power dissipation, 855 mW at 80 Msps
Serial Peripheral Interface (SPI)
Duty cycle stabilizer
Sample rate up to 125 Msps
Clock input divider by 2 for less jitter
contribution
Single 3 V supply
Fast OuT-of-Range (OTR) detection
INL: ± 0.25 LSB; DNL: ± 0.12 LSB
Flexible input voltage range:
1 V to 2 V (p-p)
CMOS or LVDS DDR digital outputs
Offset binary, two’s complement, gray
code
Pin and software compatible with
Power-down and Sleep modes
ADC1412D series.
HVQFN64 package
3. Applications
Wireless and wired broadband
Spectral analysis
communications
Portable instrumentation
Imaging systems
Ultrasound equipment
Software defined radio
ADC1212D series
NXP Semiconductors
CMOS or LVDS DDR digital outputs
4. Ordering information
Table 1.
Ordering information
Type number
fs (Msps) Package
Name
Description
Version
ADC1212D125HN/C1 125
ADC1212D105HN/C1 105
ADC1212D080HN/C1 80
ADC1212D065HN/C1 65
HVQFN64 plastic thermal enhanced very thin quad flat package;
SOT804-3
SOT804-3
SOT804-3
SOT804-3
no leads; 64 terminals; body 9 × 9 × 0.85 mm
HVQFN64 plastic thermal enhanced very thin quad flat package;
no leads; 64 terminals; body 9 × 9 × 0.85 mm
HVQFN64 plastic thermal enhanced very thin quad flat package;
no leads; 64 terminals; body 9 × 9 × 0.85 mm
HVQFN64 plastic thermal enhanced very thin quad flat package;
no leads; 64 terminals; body 9 × 9 × 0.85 mm
5. Block diagram
SDIO/ODS
SCLK/DFS
CS
ADC1212D
ERROR
CORRECTION AND
DIGITAL
SPI INTERFACE
PROCESSING
OTRA
CMOS:
DA11 to DA0
or
LVDS/DDR:
DA10_DA11_P to DA0_DA1_P,
DA10_DA11_M to DA0_DA1_M
INAP
INAM
T/H
INPUT
STAGE
ADC CORE
12-BIT
PIPELINED
OUTPUT
DRIVERS
CMOS:
DAV
CLKP
CLKM
CLOCK INPUT
STAGE AND DUTY
CYCLE CONTROL
or
OUTPUT
DRIVERS
LVDS/DDR:
DAVP
DAVM
CMOS:
DB11 to DB0
or
LVDS/DDR:
DB10_DB11_P to DB0_DB1_P,
DB10_DB11_M to DB0_DB1_M
INBP
INBM
T/H
INPUT
STAGE
ADC CORE
12-BIT
PIPELINED
OUTPUT
DRIVERS
OTRB
ERROR
CORRECTION AND
DIGITAL
SYSTEM
REFERENCE AND
POWER
CTRL
PROCESSING
MANAGEMENT
REFBT
REFBB
VCMB
SENSE VREF
REFAB
REFAT
VCMA
005aaa128
Fig 1. Block diagram
ADC1212D_SER
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 01 — 6 August 2010
2 of 38
ADC1212D series
NXP Semiconductors
CMOS or LVDS DDR digital outputs
6. Pinning information
6.1 CMOS outputs selected
6.1.1 Pinning
terminal 1
index area
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
INAP
INAM
DA3
DA2
DA1
DA0
n.c.
3
AGND
VCMA
REFAT
REFAB
AGND
CLKP
4
5
6
n.c.
7
DAVP
DAVM
n.c.
8
ADC1212D
HVQFN64
9
CLKM
AGND
REFBB
REFBT
VCMB
AGND
INBM
10
11
12
13
14
15
16
n.c.
DB0
DB1
DB2
DB3
DB4
DB5
INBP
Transparent top view
005aaa129
Fig 2. Pin configuration with CMOS digital outputs selected
6.1.2 Pin description
Table 2.
Symbol
Pin description (CMOS digital outputs)
Pin
1
Type [1]
Description
INAP
I
analog input; channel A
INAM
2
I
complementary analog input; channel A
analog ground
AGND
VCMA
REFAT
REFAB
AGND
CLKP
3
G
O
O
O
G
I
4
common-mode output voltage; channel A
top reference; channel A
bottom reference; channel A
analog ground
5
6
7
8
clock input
CLKM
AGND
REFBB
REFBT
9
I
complementary clock input
analog ground
10
11
12
G
O
O
bottom reference; channel B
top reference; channel B
ADC1212D_SER
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 01 — 6 August 2010
3 of 38
ADC1212D series
NXP Semiconductors
CMOS or LVDS DDR digital outputs
Table 2.
Pin description (CMOS digital outputs) …continued
Symbol
VCMB
AGND
INBM
INBP
VDDA
VDDA
SCLK/DFS
SDIO/ODS
CS
Pin
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
Type [1]
O
G
I
Description
common-mode output voltage; channel B
analog ground
complementary analog input; channel B
analog input; channel B
I
P
analog power supply
P
analog power supply
I
SPI clock/data format select
SPI data IO/output data standard
SPI chip select
I/O
I
CTRL
DECB
OTRB
DB11
DB10
DB9
I
control mode select
O
O
O
O
O
O
O
O
P
regulator decoupling node; channel B
out-of-range; channel B
data output bit 11 (Most Significant Bit (MSB)); channel B
data output bit 10; channel B
data output bit 9; channel B
data output bit 8; channel B
data output bit 7; channel B
data output bit 6; channel B
output power supply
DB8
DB7
DB6
VDDO
VDDO
DB5
P
output power supply
O
O
O
O
O
O
-
data output bit 5; channel B
data output bit 4; channel B
data output bit 3; channel B
data output bit 2; channel B
data output bit 1; channel B
data output bit 0 (Least Significant Bit(LSB)); channel B
not connected
DB4
DB3
DB2
DB1
DB0
n.c.
n.c.
-
not connected
DAVM
DAVP
n.c.
O
O
-
data valid output clock, complement
data valid output clock, true
not connected
n.c.
-
not connected
DA0
O
O
O
O
P
data output bit 0 (LSB); channel A
data output bit 1; channel A
data output bit 2; channel A
data output bit 3; channel A
output power supply
DA1
DA2
DA3
VDDO
VDDO
DA4
P
output power supply
O
O
O
O
O
O
data output bit 4; channel A
data output bit 5; channel A
data output bit 6; channel A
data output bit 7; channel A
data output bit 8; channel A
data output bit 9; channel A
DA5
DA6
DA7
DA8
DA9
ADC1212D_SER
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 01 — 6 August 2010
4 of 38
ADC1212D series
NXP Semiconductors
CMOS or LVDS DDR digital outputs
Table 2.
Pin description (CMOS digital outputs) …continued
Symbol
DA10
Pin
57
58
59
60
61
62
63
64
Type [1]
Description
O
O
O
O
P
data output bit 10; channel A
data output bit 11 (MSB); channel A
out-of-range; channel A
DA11
OTRA
DECA
VDDA
SENSE
VREF
VDDA
regulator decoupling node; channel A
analog power supply
I
reference programming pin
voltage reference input/output
analog power supply
I/O
P
[1] P: power supply; G: ground; I: input; O: output; I/O: input/output.
6.2 LVDS/DDR outputs selected
6.2.1 Pinning
terminal 1
index area
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
INAP
INAM
DA2_DA3_M
DA2_DA3_P
DA0_DA1_M
DA0_DA1_P
n.c.
3
AGND
VCMA
REFAT
REFAB
AGND
CLKP
4
5
6
n.c.
7
DAVP
8
DAVM
ADC1212D
HVQFN64
9
CLKM
AGND
REFBB
REFBT
VCMB
AGND
INBM
n.c.
10
11
12
13
14
15
16
n.c.
DB0_DB1_P
DB0_DB1_M
DB2_DB3_P
DB2_DB3_M
DB4_DB5_P
DB4_DB5_M
INBP
Transparent top view
005aaa130
Fig 3. Pin configuration with LVDS/DDR digital outputs selected
ADC1212D_SER
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 01 — 6 August 2010
5 of 38
ADC1212D series
NXP Semiconductors
CMOS or LVDS DDR digital outputs
6.2.2 Pin description
Table 3.
Symbol
Pin description (LVDS/DDR) digital outputs)[1]
Pin Type [2] Description
DB10_DB11_M 25
O
differential output data DB10 and DB11 multiplexed,
complement
DB10_DB11_P 26
O
O
O
O
O
O
O
O
O
O
O
-
differential output data DB10 and DB11 multiplexed, true
differential output data DB8 and DB9 multiplexed, complement
differential output data DB8 and DB9 multiplexed, true
differential output data DB6 and DB7 multiplexed, complement
differential output data DB6 and DB7 multiplexed, true
differential output data DB4 and DB5 multiplexed, complement
differential output data DB4 and DB5 multiplexed, true
differential output data DB2 and DB3 multiplexed, complement
differential output data DB2 and DB3 multiplexed, true
differential output data DB0 and DB1 multiplexed, complement
differential output data DB0 and DB1 multiplexed, true
not connected
DB8_DB9_M
DB8_DB9_P
DB6_DB7_M
DB6_DB7_P
DB4_DB5_M
DB4_DB5_P
DB2_DB3_M
DB2_DB3_P
DB0_DB1_M
DB0_DB1_P
n.c.
27
28
29
30
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
51
52
53
54
55
56
n.c.
-
not connected
DAVM
O
O
-
data valid output clock, complement
DAVP
data valid output clock, true
n.c.
not connected
n.c.
-
not connected
DA0_DA1_P
DA0_DA1_M
DA2_DA3_P
DA2_DA3_M
DA4_DA5_P
DA4_DA5_M
DA6_DA7_P
DA6_DA7_M
DA8_DA9_P
DA8_DA9_M
O
O
O
O
O
O
O
O
O
O
O
O
differential output data DA0 and DA1 multiplexed, true
differential output data DA0 and DA1 multiplexed, complement
differential output data DA2 and DA3 multiplexed, true
differential output data DA2 and DA3 multiplexed, complement
differential output data DA4 and DA5 multiplexed, true
differential output data DA4 and DA5 multiplexed, complement
differential output data DA6 and DA7 multiplexed, true
differential output data DA6 and DA7 multiplexed, complement
differential output data DA8 and DA9 multiplexed, true
differential output data DA8 and DA9 multiplexed, complement
differential output data DA10 and DA11 multiplexed, true
DA10_DA11_P 57
DA10_DA11_M 58
differential output data DA10 and DA11 multiplexed,
complement
[1] Pins 1 to 24, pin 59 to 64 and pins 31, 32, 49 and 50 are the same for both CMOS and LVDS DDR outputs
(see Table 2).
[2] P: power supply; G: ground; I: input; O: output; I/O: input/output.
ADC1212D_SER
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 01 — 6 August 2010
6 of 38
ADC1212D series
NXP Semiconductors
CMOS or LVDS DDR digital outputs
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
Max
Unit
VO
output voltage
pins DA11 to DA0 and
−0.4
+3.9
V
DB11 to DB0 or pins
DA10_DA11_P to DA0_DA1_P,
DA10_DA11_M to DA0_DA1_M,
DB10_DB11_P to DB0_DB1_P
and
DB10_DB11_M to DB0_DB1_M
VDDA
analog supply
voltage
−0.4
+3.9
V
VDDO
Tstg
Tamb
Tj
output supply voltage
storage temperature
ambient temperature
junction temperature
−0.4
−55
−40
-
+3.9
+125
+85
V
°C
°C
°C
125
8. Thermal characteristics
Table 5.
Symbol
Rth(j-a)
Thermal characteristics
Parameter
Conditions
Typ
Unit
[1]
[1]
thermal resistance from junction to ambient
thermal resistance from junction to case
15.6
6.3
K/W
K/W
Rth(j-c)
[1] Value for six layers board in still air with a minimum of 64 thermal vias.
9. Static characteristics
Table 6.
Symbol
Supplies
VDDA
Static characteristics[1]
Parameter
Conditions
Min
Typ
Max
Unit
analog supply voltage
output supply voltage
2.85
1.65
2.85
-
3.0
1.8
3.0
400
20
3.4
3.6
3.6
-
V
VDDO
CMOS mode
V
LVDS DDR mode
V
IDDA
IDDO
analog supply current
output supply current
fclk = 125 Msps; fi = 70 MHz
mA
mA
CMOS mode; fclk = 125 Msps;
fi = 70 MHz
-
-
LVDS DDR mode:
-
90
-
mA
fclk = 125 Msps; fi = 70 MHz
ADC1212D_SER
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 01 — 6 August 2010
7 of 38
ADC1212D series
NXP Semiconductors
CMOS or LVDS DDR digital outputs
Table 6.
Symbol
P
Static characteristics[1] …continued
Parameter
Conditions
Min
Typ
Max
Unit
power dissipation
ADC1212D125;
-
1200
-
mW
analog supply only
ADC1212D105;
analog supply only
-
-
-
1090
855
-
-
-
mW
mW
mW
ADC1212D080;
analog supply only
ADC1212D065;
795
analog supply only
Power-down mode
Sleep mode
-
-
25
80
-
-
mW
mW
Clock inputs: pins CLKP and CLKM
LVPECL
Vi(clk)dif
LVDS
Vi(clk)dif
SINE
differential clock input voltage
peak-to-peak
peak-to-peak
peak-to-peak
-
±1.6
±0.70
±3.0
-
-
-
V
V
V
differential clock input voltage
differential clock input voltage
-
Vi(clk)dif
LVCMOS
VIL
±0.8
LOW-level input voltage
HIGH-level input voltage
-
-
-
0.3VDDA
-
V
V
VIH
0.7VDDA
Logic input: pin CTRL
VIL
LOW-level input voltage
-
0
-
V
LOW-medium level
medium-HIGH level
-
0.3VDDA
-
V
-
0.6VDDA
-
V
VIH
IIL
HIGH-level input voltage
LOW-level input current
HIGH-level input current
-
VDDA
-
V
<tbd>
−10
-
-
<tbd>
+10
μA
μA
IIH
Serial peripheral interface: pins CS, SDIO/ODS, SCLK/DFS
VIL
VIH
IIL
LOW-level input voltage
HIGH-level input voltage
LOW-level input current
HIGH-level input current
input capacitance
0
-
0.3VDDA
VDDA
+10
V
0.7VDDA
−10
−50
-
-
V
-
μA
μA
pF
IIH
CI
-
+50
4
-
Digital outputs, CMOS mode: pins DA11 to DA0, DB11 to DB0, OTRA, OTRB and DAV
Output levels, VDDO= 3 V
VOL
VOH
IOL
LOW-level output voltage
HIGH-level output voltage
LOW-level output current
HIGH-level output current
output capacitance
IOL = <tbd>
OGND
-
0.2VDDO
V
IOH = <tbd>
0.8VDDO
-
VDDO
V
3-state; output level = 0 V
3-state; output level = VDDA
high impedance; see Table 10
-
-
-
<tbd>
<tbd>
3
-
-
-
μA
μA
pF
IOH
CO
Output levels, VDDO = 1.8 V
VOL
LOW-level output voltage
IOL = <tbd>
OGND
-
0.2VDDO
V
ADC1212D_SER
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 01 — 6 August 2010
8 of 38
ADC1212D series
NXP Semiconductors
CMOS or LVDS DDR digital outputs
Table 6.
Symbol
VOH
Static characteristics[1] …continued
Parameter
Conditions
Min
Typ
Max
Unit
HIGH-level output voltage
IOH = <tbd>
0.8VDDO
-
VDDO
V
Digital outputs, LVDS DDR mode: pins DA10_DA11_P to DA0_DA1_P, DA10_DA11_M to DA0_DA1_M,
DB10_DB11_P to DB0_DB1_P, DB10_DB11_M to DB0_DB1_M; DAVP and DAVM
Output levels, VDDO = 3 V only, RL = 100 Ω
VO(offset)
VO(dif)
CO
output offset voltage
differential output voltage
output capacitance
output buffer current set to
3.5 mA
-
-
-
1.2
-
-
-
V
output buffer current set to
3.5 mA
350
mV
pF
<tbd>
Analog inputs: pins INAP, INAM, INBP and INBM
II
input current
−5
-
-
+5
-
μA
Ω
RI
input resistance
<tbd>
5
CI
input capacitance
common-mode input voltage
input bandwidth
-
-
pF
V
VI(cm)
Bi
VINAP = VINAM; VINBP = VINBM
0.9
-
1.5
600
-
2
-
MHz
V
VI(dif)
differential input voltage
peak-to-peak
1
2
Common mode output voltage: pins VCMA and VCMB
VO(cm)
IO(cm)
common-mode output voltage
common-mode output current
-
-
0.5VDDA
<tbd>
-
-
V
μA
I/O reference voltage: pin VREF
VVREF
voltage on pin VREF
output
input
-
0.5 to 1
-
-
V
V
0.5
1
Accuracy
INL
integral non-linearity
differential non-linearity
offset error
−1.25
± 0.25
± 0.5
±2
+5
LSB
LSB
mV
DNL
guaranteed no missing codes
−0.95
+0.95
Eoffset
EG
-
-
-
-
-
-
gain error
±0.5
<tbd>
%FS
%
MG(CTC)
channel-to-channel gain
matching
Supply
PSRR
power supply rejection ratio
100 mV (p-p) on VDDA
-
35
-
dBc
[1] Typical values measured at VDDA = 3 V, VDDO = 1.8 V, Tamb = 25 °C and CL = 5 pF; minimum and maximum values are across the full
temperature range Tamb = −40 °C to +85 °C at VDDA = 3 V, VDDO = 1.8 V; VINAP − VINAM = −1 dBFS; VINBP − VINBM = −1 dBFS; internal
reference mode; applied to CMOS and LVDS interface; unless otherwise specified.
ADC1212D_SER
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 01 — 6 August 2010
9 of 38
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10. Dynamic characteristics
10.1 Dynamic characteristics
Table 7.
Characteristics[1]
Symbol Parameter
Conditions
ADC1212D065
Min Typ
ADC1212D080
Max Min Typ
ADC1212D105
Max Min Typ
ADC1212D125
Max Min Typ
Unit
Max
Analog signal processing
α2H
second harmonic level fi = 3 MHz
fi = 30 MHz
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
87
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
87
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
86
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
88
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
Bits
86
86
86
87
fi = 70 MHz
85
85
84
85
fi = 170 MHz
82
82
81
83
α3H
third harmonic level
fi = 3 MHz
86
86
85
87
fi = 30 MHz
fi = 70 MHz
fi = 170 MHz
85
85
85
86
84
84
83
84
81
81
80
82
THD
ENOB
SNR
SFDR
total harmonic distortion fi = 3 MHz
fi = 30 MHz
85
85
84
86
84
84
84
85
fi = 70 MHz
83
83
82
83
fi = 170 MHz
80
80
79
81
effective number of bits fi = 3 MHz
fi = 30 MHz
11.3
11.3
11.2
11.1
70.0
69.5
69.2
68.8
86
11.3
11.3
11.2
11.1
69.9
69.5
69.2
68.8
86
11.3
11.3
11.2
11.1
69.8
69.5
69.1
68.7
85
11.3
11.2
11.2
11.1
69.6
69.4
69.0
68.6
87
Bits
fi = 70 MHz
Bits
fi = 170 MHz
Bits
signal-to-noise ratio
fi = 3 MHz
dBFS
dBFS
dBFS
dBFS
dBc
dBc
dBc
dBc
fi = 30 MHz
fi = 70 MHz
fi = 170 MHz
fi = 3 MHz
spurious-free dynamic
range
fi = 30 MHz
fi = 70 MHz
fi = 170 MHz
85
85
85
86
84
84
83
84
81
81
80
82
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Table 7.
Characteristics[1] …continued
Symbol Parameter
Conditions
ADC1212D065
Min Typ
ADC1212D080
Max Min Typ
ADC1212D105
Max Min Typ
ADC1212D125
Max Min Typ
Unit
Max
IMD
intermodulation
distortion
fi = 3 MHz
-
-
-
-
-
89
-
-
-
-
-
-
-
-
-
-
89
88
87
85
100
-
-
-
-
-
-
-
-
-
-
88
88
86
83
100
-
-
-
-
-
-
-
-
-
-
89
88
86
84
100
-
-
-
-
-
dBc
dBc
dBc
dBc
dBc
fi = 30 MHz
fi = 70 MHz
fi = 170 MHz
fi = 70 MHz
88
87
84
αct(ch)
channel crosstalk
100
[1] Typical values measured at VDDA = 3 V, VDDO = 1.8 V, Tamb = 25 °C and CL = 5 pF; minimum and maximum values are across the full temperature range Tamb = −40 °C to +85 °C
at VDDA = 3 V, VDDO = 1.8 V; VINAP − VINAM = −1 dBFS; VINBP − VINBM = −1 dBFS; internal reference mode; applied to CMOS and LVDS interface; unless otherwise specified.
10.2 Clock and digital output timing
Table 8.
Symbol Parameter
Clock and digital output timing characteristics[1]
Conditions ADC1412D065
Min Typ Max
ADC1412D080
Min Typ Max
ADC1412D105
Min Typ Max
ADC1412D125
Min Typ Max
Unit
Clock timing input: pins CLKP and CLKM
fclk clock frequency
tlat(data) data latency time
20
-
-
65
-
60
-
-
80
-
75
-
-
105
-
100
-
-
125
-
MHz
14
14
14
14
clock
cycle
s
δclk
clock duty cycle
DCS_EN = 1
DCS_EN = 0
30
45
-
50
50
0.8
70
55
-
30
45
-
50
50
0.8
70
55
-
30
45
-
50
50
0.8
70
55
-
30
45
-
50
50
0.8
70
55
-
%
%
ns
td(s)
sampling delay
time
twake
wake-up time
-
tbd
-
-
tbd
-
-
tbd
-
-
tbd
-
ns
CMOS mode timing: pins DA11 to DA0, DB13 to DB0 and DAV
tPD
propagation delay DATA
DAV
-
3.9
4.2
8.6
4.8
-
-
-
3.9
4.2
7.4
3.4
-
-
-
3.9
4.2
6.1
1.8
-
-
-
3.9
4.2
5.7
1.4
-
-
ns
ns
ns
ns
ns
ns
ns
-
-
-
-
-
-
-
-
tsu
th
set-up time
-
-
-
-
-
-
-
-
hold time
-
-
-
-
-
-
-
-
[2]
[2]
tr
rise time
fall time
DATA
DAV
0.5
0.5
0.5
2.4
2.4
2.4
0.5
0.5
0.5
2.4
2.4
2.4
0.5
0.5
0.5
2.4
2.4
2.4
0.5
0.5
0.5
2.4
2.4
2.4
-
-
-
-
tf
DATA
-
-
-
-
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Table 8.
Clock and digital output timing characteristics[1] …continued
Symbol Parameter
Conditions
ADC1412D065
Min Typ Max
ADC1412D080
Min Typ Max
ADC1412D105
Min Typ Max
ADC1412D125
Min Typ Max
Unit
LVDS DDR mode timing: pins DA10_DA11_P to DA0_DA1_P, DA10_DA11_M to DA0_DA1_M, DB10_DB11_P to DB0_DB1_P,
DB10_DB11_M to DB0_DB1_M; DAVP and DAVM
tPD
propagation delay DATA
DAV
-
3.9
4.2
-
-
3.9
4.2
-
-
3.9
4.2
-
-
3.9
-
ns
ns
ns
ns
ps
ps
ps
ps
-
-
-
-
-
-
-
4.2
1.4
-
tsu
th
set-up time
-
5.1
-
-
3.5
-
-
2.1
-
-
-
hold time
-
2.0
-
-
2.0
-
-
2.0
-
-
2.0
-
[3]
[3]
tr
rise time
DATA
DAV
50
50
50
50
100
100
100
100
200
200
200
200
50
50
50
50
100
100
100
100
200
200
200
200
50
50
50
50
100
100
100
100
200
200
200
200
50
50
50
50
100
100
100
100
200
200
200
200
tf
fall time
DATA
DAV
[1] Typical values measured at VDDA = 3 V, VDDO = 1.8 V, Tamb = 25 °C and CL = 5 pF; minimum and maximum values are across the full temperature range Tamb = −40 °C to 85 °C at
DDA = 3 V, VDDO = 1.8 V; VINAP − VINAM = −1 dBFS; VINBP − VINBM = −1 dBFS; unless otherwise specified.
V
[2] Measured between 20 % to 80 % of VDDO
.
[3] Rise time measured from −50 mV to +50 mV; fall time measured from +50 mV to −50 mV.
ADC1212D series
NXP Semiconductors
CMOS or LVDS DDR digital outputs
N
N + 1
t
d(s)
N + 2
t
clk
CLKP
CLKM
t
PD
(N − 14)
(N − 13)
(N − 12)
(N − 11)
DATA
DAV
t
PD
t
su
t
h
t
clk
005aaa060
Fig 4. CMOS mode timing
N
N + 1
t
d(s)
N + 2
t
clk
CLKP
CLKM
t
PD
(N − 14)
(N − 13)
(N − 12)
(N − 11)
DA _DA
x
_P/
x + 1
DB _DB
_P
x
x + 1
DA /
DA
DB
DA /
DA
DB
DA /
DA
DA /
DA
DA /
DA
x
x+1/
x
x+1/
x
x+1/
DB
x
x+1/
DB
x
x+1/
DB
DB
DB
DB
DB
DB
x
x+1
x
x+1
x
x+1
x
x+1
x
x+1
DA _DA
_M/
x + 1
x
DB _DB
x
_M
x + 1
t
t
t
t
su
su
h
h
t
PD
DAVP
DAVM
t
clk
005aaa114
Fig 5. LVDS DDR mode timing
ADC1212D_SER
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Preliminary data sheet
Rev. 01 — 6 August 2010
13 of 38
ADC1212D series
NXP Semiconductors
CMOS or LVDS DDR digital outputs
10.3 SPI timings
Table 9.
Symbol
Characteristics [1]
Parameter
Conditions
Min Typ
Max
Unit
SPI timings
tw(SCLK)
tw(SCLKH)
tw(SCLKL)
tsu
SCLK pulse width
SCLK HIGH pulse width
SCLK LOW pulse width
set-up time
40
16
16
5
-
-
-
-
-
-
-
-
-
ns
-
ns
-
ns
data to SCLK HIGH
CS to SCLK HIGH
data to SCLK HIGH
CS to SCLK HIGH
-
ns
5
-
ns
th
hold time
2
-
ns
2
-
ns
fclk(max)
maximum clock frequency
-
25
MHz
[1] Typical values measured at VDDA = 3 V, VDDO = 1.8 V, Tamb = 25 °C and CL = 5 pF; minimum and maximum
values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA = 3 V, VDDO = 1.8 V.
t
t
su
w(SCLKL)
t
h
t
h
su
t
t
w(SCLKH)
t
w(SCLK)
CS
SCLK
SDIO
W1
W0
A12
A11
D2
D1
D0
R/W
005aaa065
Fig 6. SPI timing
11. Application information
11.1 Device control
The ADC1212D can be controlled via the Serial Peripheral Interface (SPI control mode) or
directly via the I/O pins (Pin control mode).
11.1.1 SPI and Pin control modes
The device enters Pin control mode at power-up and remains in this mode as long as pin
CS is held HIGH. In Pin control mode, the SPI pins SDIO, CS and SCLK are used as
static control pins.
SPI control mode is enabled by forcing pin CS LOW. Once SPI control mode has been
enabled, the device remains in this mode. The transition from Pin control mode to SPI
control mode is illustrated in Figure 7.
ADC1212D_SER
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© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 01 — 6 August 2010
14 of 38
ADC1212D series
NXP Semiconductors
CMOS or LVDS DDR digital outputs
CS
SCLK/DFS
SDIO/ODS
Pin control mode
SPI control mode
Data format
offset binary
Data format
two's complement
LVDS DDR
R/W
W1
W0
A12
CMOS
005aaa039
Fig 7. Control mode selection.
When the device enters SPI control mode, the output data standard and data format are
determined by the level on pin SDIO as soon as a transition is triggered by a falling edge
on CS.
11.1.2 Operating mode selection
The active ADC1212D operating mode (Power-up, Power-down or Sleep) can be selected
via the SPI interface (see Table 21) or by using pin CTRL in Pin control mode, as
described in Table 10.
Table 10. Operating mode selection via pin CTRL
Pin CTRL
0
Operating mode
Power-down
Sleep
Output high-Z
yes
yes
yes
no
0.3VDDA
0.6VDDA
VDDA
Power-up
Power-up
11.1.3 Selecting the output data standard
The output data standard (CMOS or LVDS DDR) can be selected via the SPI interface
(see Table 24) or by using pin ODS in Pin control mode. LVDS DDR is selected when
ODS is HIGH, otherwise CMOS is selected.
11.1.4 Selecting the output data format
The output data format can be selected via the SPI interface (offset binary,
two’s complement or gray code; see Table 24) or by using pin DFS in Pin control mode
(offset binary or two’s complement). Offset binary is selected when DFS is LOW. When
DFS is HIGH, two’s complement is selected.
11.2 Analog inputs
11.2.1 Input stage
The analog input of the ADC1212D supports a differential or a single-ended input drive.
Optimal performance is achieved using differential inputs with the common-mode input
voltage (VI(cm)) on pins INAP, INAM, INBP and INBM set to 0.5VDDA
.
The full-scale analog input voltage range is configurable between 1 V (p-p) and 2 V (p-p)
via a programmable internal reference (see Section 11.3 and Table 23).
The equivalent circuit of the sample and hold input stage, including ElectroStatic
Discharge (ESD) protection and circuit and package parasitics, is shown in Figure 8.
ADC1212D_SER
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Preliminary data sheet
Rev. 01 — 6 August 2010
15 of 38
ADC1212D series
NXP Semiconductors
CMOS or LVDS DDR digital outputs
Package
ESD
Parasitics
Switch
R
= 14 Ω
on
4 pF
INAP/INBP
INAM/INBM
Sampling
capacitor
internal
clock
Switch
on
R
= 14 Ω
4 pF
Sampling
capacitor
internal
clock
005aaa092
Fig 8. Input sampling circuit
The sample phase occurs when the internal clock (derived from the clock signal on pin
CLKP/CLKM) is HIGH. The voltage is then held on the sampling capacitors. When the
clock signal goes LOW, the stage enters the hold phase and the voltage information is
transmitted to the ADC core.
11.2.2 Anti-kickback circuitry
Anti-kickback circuitry (RC filter in Figure 9 is needed to counteract the effects of charge
injection generated by the sampling capacitance.
The RC filter is also used to filter noise from the signal before it reaches the sampling
stage. The value of the capacitor should be chosen to maximize noise attenuation without
degrading the settling time excessively.
R
INAP/INBP
C
R
INAM/INBM
005aaa093
Fig 9. Anti-kickback circuit
The component values are determined by the input frequency and should be selected so
as not to affect the input bandwidth.
ADC1212D_SER
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© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 01 — 6 August 2010
16 of 38
ADC1212D series
NXP Semiconductors
CMOS or LVDS DDR digital outputs
Table 11. RC coupling versus input frequency, typical values
Input frequency
R
C
3 MHz
25 Ω
12 Ω
12 Ω
12 pF
8 pF
8 pF
70 MHz
170 MHz
11.2.3 Transformer
The configuration of the transformer circuit is determined by the input frequency. The
configuration shown in Figure 10 would be suitable for a baseband application.
ADT1-1WT
100 nF
25 Ω
INAP/INBP
100 nF
Analog
input
25 Ω
12 pF
25 Ω
100 nF
25 Ω
100 nF
INAM/INBM
VCMA/VCMB
100 nF
100 nF
005aaa094
Fig 10. Single transformer configuration suitable for baseband applications
The configuration shown in Figure 11 is recommended for high frequency applications. In
both cases, the choice of transformer is a compromise between cost and performance.
ADT1-1WT
ADT1-1WT
12 Ω
12 Ω
INAP/INBP
100 nF
50 Ω
50 Ω
50 Ω
50 Ω
Analog
input
8.2 pF
INAM/INBM
100 nF
VCMA/VCMB
100 nF
100 nF
005aaa095
Fig 11. Dual transformer configuration suitable for high intermediate frequency
application
ADC1212D_SER
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© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 01 — 6 August 2010
17 of 38
ADC1212D series
NXP Semiconductors
CMOS or LVDS DDR digital outputs
11.3 System reference and power management
11.3.1 Internal/external references
The ADC1212D has a stable and accurate built-in internal reference voltage to adjust the
ADC full-scale. This reference voltage can be set internally via SPI or with pin VREF and
SENSE (programmable in 1 dB steps between 0 dB and −6 dB via control bits INTREF
when bit INTREF_EN = logic 1; see Table 23). See Figure 13 to Figure 16. The equivalent
reference circuit is shown in Figure 12. External reference is also possible by providing a
voltage on pin VREF as described in Figure 15.
REFAT/
REFBT
REFERENCE
AMP
REFAB/
REFBB
VREF
EXT_ref
BANDGAP
REFERENCE
EXT_ref
BUFFER
ADC CORE
SENSE
SELECTION
LOGIC
005aaa164
Fig 12. Reference equivalent schematic
If bit INTREF_EN is set to logic 0, the reference voltage is determined either internally or
externally as detailed in Table 12.
Table 12. Reference selection
Selection
SPI bit
SENSE pin
VREF pin
Full-scale (p-p)
INTREF_EN
internal
(Figure 13)
0
0
0
1
AGND
330 pF capacitor to
AGND
2 V
internal
(Figure 14)
pin VREF connected to pin SENSE and 1 V
via a 330 pF capacitor to AGND
external
(Figure 15)
VDDA
external voltage between 1 V to 2 V
0.5 V and 1 V[1]
internal via SPI
(Figure 16)
pin VREF connected to pin SENSE and 1 V to 2 V
via 330 pF capacitor to AGND
[1] The voltage on pin VREF is doubled internally to generate the internal reference voltage.
ADC1212D_SER
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© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 01 — 6 August 2010
18 of 38
ADC1212D series
NXP Semiconductors
CMOS or LVDS DDR digital outputs
Figure 13 to Figure 16 illustrate how to connect the SENSE and VREF pins to select the
required reference voltage source.
VREF
VREF
330
pF
330 pF
REFERENCE
EQUIVALENT
SCHEMATIC
REFERENCE
EQUIVALENT
SCHEMATIC
SENSE
SENSE
005aaa116
005aaa117
Fig 13. Internal reference, 2 V (p-p) full-scale
Fig 14. Internal reference, 1 V (p-p) full-scale
VREF
VREF
330 pF
0.1 μF
V
REFERENCE
EQUIVALENT
SCHEMATIC
REFERENCE
EQUIVALENT
SCHEMATIC
SENSE
SENSE
VDDA
005aaa119
005aaa118
Fig 15. External reference, 1 V (p-p) to 2 V (p-p)
full-scale
Fig 16. Internal reference via SPI, 1 V (p-p) to 2 V (p-p)
full-scale
11.3.2 Reference gain control
The reference gain is programmable between 0 dB to −6 dB in 1 dB steps via the SPI (see
Table 23). The corresponding full-scale input voltage range varies between 2 V (p-p) and
1 V (p-p), as shown in Table 13.
Table 13. Reference SPI gain control
INTREF
000
Gain
Full-scale (p-p)
2 V
0 dB
001
−1 dB
−2 dB
−3 dB
−4 dB
−5 dB
−6 dB
reserved
1.78 V
1.59 V
1.42 V
1.26 V
1.12 V
1 V
010
011
100
101
110
111
x
11.3.3 Common-mode output voltage (VO(cm)
)
A 0.1 μF filter capacitor should be connected between pin VCMA/VCMB and ground to
ensure a low-noise common-mode output voltage. When AC-coupled, pin VCMA/VCMB
can then be used to set the common-mode reference for the analog inputs, for instance
via a transformer middle point.
ADC1212D_SER
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© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 01 — 6 August 2010
19 of 38
ADC1212D series
NXP Semiconductors
CMOS or LVDS DDR digital outputs
Package
ESD
Parasitics
COMMON MODE
REFERENCE
VCMA/VCMB
1.5 V
0.1 μF
ADC CORE
005aaa099
Fig 17. Equivalent schematic of the common-mode reference circuit
11.3.4 Biasing
The common-mode input voltage (VI(cm)) on pins INAP/INBP and INAM/INBM should be
set externally to 0.5VDDA for optimal performance and should always be between 0.9 V
and 2 V.
11.4 Clock input
11.4.1 Drive modes
The ADC1212D can be driven differentially (SINE, LVPECL or LVDS) with little or no
degradation on dynamic performance. It can also be driven by a single-ended Low
Voltage Complementary Metal Oxide Semiconductor (LVCMOS) signal connected to pin
CLKP (pin CLKM should be connected to ground via a capacitor) or CLKM (pin CLKP
should be connected to ground via a capacitor).
CLKP
CLKM
LVCMOS
clock input
CLKP
CLKM
LVCMOS
clock input
005aaa174
005aaa053
a. Rising edge LVCMOS
b. Falling edge LVCMOS
Fig 18. LVCMOS single-ended clock input
ADC1212D_SER
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© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 01 — 6 August 2010
20 of 38
ADC1212D series
NXP Semiconductors
CMOS or LVDS DDR digital outputs
CLKP
CLKM
Sine
clock input
CLKP
CLKM
Sine
clock input
005aaa173
005aaa054
a. Sine clock input
b. Sine clock input (with transformer)
CLKP
CLKP
LVPECL
clock input
LVDS
clock input
CLKM
CLKM
005aaa055
005aaa172
c. LVDS clock input
d. LVPECL clock input
Fig 19. Differential clock input
11.4.2 Equivalent input circuit
The equivalent circuit of the input clock buffer is shown in Figure 20. The common-mode
voltage of the differential input stage is set via internal 5 kΩ resistors.
Package
ESD
Parasitics
CLKP
CLKM
V
cm(clk)
SE_SEL SE_SEL
5 kΩ
5 kΩ
005aaa056
Vcm(clk) = common-mode voltage of the differential input stage
Fig 20. Equivalent input circuit
ADC1212D_SER
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© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 01 — 6 August 2010
21 of 38
ADC1212D series
NXP Semiconductors
CMOS or LVDS DDR digital outputs
Single-ended or differential clock inputs can be selected via the SPI interface
(see Table 22). If single-ended is enabled, the input pin (CLKM or CLKP) is selected via
control bit SE_SEL.
If single-ended is implemented without setting bit SE_SEL to the appropriate value, the
unused pin should be connected to ground via a capacitor.
11.4.3 Duty cycle stabilizer
The duty cycle stabilizer can improve the overall performances of the ADC by
compensating the duty cycle of the input clock signal. When the duty cycle stabilizer is
active (bit DCS_EN = logic 1; see Table 22), the circuit can handle signals with duty cycles
of between 30 % and 70 % (typical). When the duty cycle stabilizer is disabled
(DCS_EN = logic 0), the input clock signal should have a duty cycle of between 45 % and
55 %.
11.4.4 Clock input divider
The ADC1212D contains an input clock divider that divides the incoming clock by a factor
of 2 (when bit CLKDIV = logic 1; see Table 22). This feature allows the user to deliver a
higher clock frequency with better jitter performance, leading to a better SNR result once
acquisition has been performed.
11.5 Digital outputs
11.5.1 Digital output buffers: CMOS mode
The digital output buffers can be configured as CMOS by setting bit LVDS_CMOS to
logic 0 (see Table 24).
Each digital output has a dedicated output buffer. The equivalent circuit of the CMOS
digital output buffer is shown in Figure 21. The buffer is powered by a separate
OGND/VDDO to ensure 1.8 V to 3.3 V compatibility and is isolated from the ADC core.
Each buffer can be loaded by a maximum of 10 pF.
VDDO
Parasitics
ESD
Package
50 Ω
Dx
LOGIC
DRIVER
OGND
005aaa057
Fig 21. CMOS digital output buffer
ADC1212D_SER
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Preliminary data sheet
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ADC1212D series
NXP Semiconductors
CMOS or LVDS DDR digital outputs
The output resistance is 50 Ω and is the combination of the an internal resistor and the
equivalent output resistance of the buffer. There is no need for an external damping
resistor. The drive strength of both DATA and DAV buffers can be programmed via the SPI
in order to adjust the rise and fall times of the output digital signals (see Table 31).
11.5.2 Digital output buffers: LVDS DDR mode
The digital output buffers can be configured as LVDS DDR by setting bit LVDS_CMOS to
logic 1 (see Table 24).
VDDO
3.5 mA
typ
−
+
DAn_DAn + 1_P; DBn_DBn + 1_P
DAn_DAn + 1_M; DBn_DBn + 1_M
RECEIVER
100 Ω
+
−
OGND
005aaa112
Fig 22. LVDS DDR digital output buffer - externally terminated
Each output should be terminated externally with a 100 Ω resistor (typical) at the receiver
side (Figure 22) or internally via SPI control bits LVDS_INT_TER (see Figure 23 and
Table 33).
VDDO
3.5 mA
typ
−
+
DAn_DAn + 1_P; DBn_DBn + 1_P
DAn_DAn + 1_M; DBn_DBn + 1_M
RECEIVER
100 Ω
100 Ω
+
−
OGND
005aaa113
Fig 23. LVDS DDR digital output buffer - internally terminated
The default LVDS DDR output buffer current is set to 3.5 mA. It can be programmed via
the SPI (bits DAVI and DATAI; see Table 32) in order to adjust the output logic voltage
levels.
ADC1212D_SER
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Preliminary data sheet
Rev. 01 — 6 August 2010
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ADC1212D series
NXP Semiconductors
CMOS or LVDS DDR digital outputs
Table 14. LVDS DDR output register 2
LVDS_INT_TER[2:0]
Resistor value
000
001
010
011
100
101
110
111
no internal termination
300 Ω
180 Ω
110 Ω
150 Ω
100 Ω
81 Ω
60 Ω
11.5.3 DAta Valid (DAV) output clock
A data valid output clock signal (DAV) is provided that can be used to capture the data
delivered by the ADC1212D. Detailed timing diagrams for CMOS and LVDS DDR modes
are provided in Figure 4 and Figure 5 respectively. In LVDS DDR mode, it is highly
recommended to shift ahead the DAV by 1 ns (bits DAVPHASE[2:0] = 0b100;
see Table 25).
11.5.4 OuT-of-Range (OTR)
An out-of-range signal is provided on pin OTRA for ADC channel A and on pin OTRB for
ADC channel B. The latency of OTRA/OTRB is fourteen clock cycles. The OTR response
can be speeded up by enabling Fast OTR (bit FASTOTR = logic 1; see Table 30). In this
mode, the latency of OTRA/OTRB is reduced to only four clock cycles. The Fast OTR
detection threshold (below full-scale) can be programmed via bits FASTOTR_DET.
Table 15. Fast OTR register
FASTOTR_DET[2:0]
Detection level
−20.56 dB
−16.12 dB
−11.02 dB
−7.82 dB
000
001
010
011
100
101
110
111
−5.49 dB
−3.66 dB
−2.14 dB
−0.86 dB
11.5.5 Digital offset
By default, the ADC1212D delivers output code that corresponds to the analog input.
However, it is possible to add a digital offset to the output code via the SPI
(bits DIG_OFFSET; see Table 26).
ADC1212D_SER
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Preliminary data sheet
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ADC1212D series
NXP Semiconductors
CMOS or LVDS DDR digital outputs
11.5.6 Test patterns
For test purposes, the ADC1212D can be configured to transmit one of a number of
predefined test patterns (via bits TESTPAT_SEL; see Table 27). A custom test pattern can
be defined by the user (TESTPAT_USER; see Table 28 and Table 29) and is selected
when TESTPAT_SEL = 101. The selected test pattern is transmitted regardless of the
analog input.
11.5.7 Output codes versus input voltage
Table 16. Output codes
VINAP − VINAM/ Offset binary
VINBP − VINBM
Two’s complement
OTRA/OTRB
pin
< −1
0000 0000 0000
0000 0000 0000
0000 0000 0001
0000 0000 0010
0000 0000 0011
0000 0000 0100
....
1000 0000 0000
1000 0000 0000
1000 0000 0001
1000 0000 0010
1000 0000 0011
1000 0000 0100
....
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
−1.0000000
−0.9995117
−0.9990234
−0.9985352
−0.9980469
....
−0.0009766
−0.0004883
+0.0000000
+0.0004883
+0.0009766
....
0111 1111 1110
0111 1111 1111
1000 0000 0000
1000 0000 0001
1000 0000 0010
....
1111 1111 1110
1111 1111 1111
0000 0000 0000
0000 0000 0001
0000 0000 0010
....
+0.9980469
+0.9985352
+0.9990234
+0.9995117
+1
1111 1111 1011
1111 1111 1100
1111 1111 1101
1111 1111 1110
1111 1111 1111
1111 1111 1111
0111 1111 1011
0111 1111 1100
0111 1111 1101
0111 1111 1110
0111 1111 1111
0111 1111 1111
> +1
11.6 Serial Peripheral Interface (SPI)
11.6.1 Register description
The ADC1212D serial interface is a synchronous serial communications port that allows
for easy interfacing with many commonly used microprocessors. It provides access to the
registers that control the operation of the chip.
This interface is configured as a 3-wire type (SDIO as bidirectional pin).
Pin SCLK is the serial clock input and CS is the chip select pin.
Each read/write operation is initiated by a LOW level on CS. A minimum of three bytes is
transmitted (two instruction bytes and at least one data byte). The number of data bytes is
determined by the value of bits W1 and W2 (see Table 18).
ADC1212D_SER
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ADC1212D series
NXP Semiconductors
CMOS or LVDS DDR digital outputs
Table 17. Instruction bytes for the SPI
MSB
LSB
Bit
7
6
5
4
3
2
1
0
Description
R/W[1]
A7
W1[2]
W0[2]
A12
A4
A11
A3
A10
A2
A9
A1
A8
A0
A6
A5
[1] Bit R/W indicates whether it is a read (logic 1) or a write (logic 0) operation.
[2] Bits W1 and W0 indicate the number of bytes to be transferred after the instruction byte (see Table 18).
Table 18. Number of data bytes to be transferred after the instruction bytes
W1
0
W0
0
Number of bytes transmitted
1 byte
0
1
2 bytes
1
0
3 bytes
1
1
4 bytes or more
Bits A12 to A0 indicate the address of the register being accessed. In the case of a
multiple byte transfer, this address is the first register to be accessed. An address counter
is increased to access subsequent addresses.
The steps for a data transfer:
1. A falling edge on CS in combination with a rising edge on SCLK determine the start of
communications.
2. The first phase is the transfer of the 2-byte instruction.
3. The second phase is the transfer of the data which can vary in length but is always a
multiple of 8 bits. The MSB is always sent first (for instruction and data bytes).
4. A rising edge on CS indicates the end of data transmission.
CS
SCLK
SDIO
W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
R/W
Instruction bytes
Register N (data)
Register N + 1 (data)
005aaa062
Fig 24. SPI mode timing
11.6.2 Default modes at start-up
During circuit initialization it does not matter which output data standard has been
selected. At power-up, the device enters Pin control mode.
A falling edge on CS triggers a transition to SPI control mode. When the ADC1212D
enters SPI control mode, the output data standard (CMOS/LVDS DDR) is determined by
the level on pin SDIO (see Figure 25). Once in SPI control mode, the output data standard
can be changed via bit LVDS_CMOS in Table 24.
ADC1212D_SER
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ADC1212D series
NXP Semiconductors
CMOS or LVDS DDR digital outputs
When the ADC1212D enters SPI control mode, the output data format (two’s complement
or offset binary) is determined by the level on pin SCLK (gray code can only be selected
via the SPI). Once in SPI control mode, the output data format can be changed via bit
DATA_FORMAT in Table 24.
CS
SCLK
(Data fo
rmat)
SDIO
(CMOS LVDS DDR)
Offset binary, LVDS DDR
default mode at start-up
005aaa063
Fig 25. Default mode at start-up: SCLK LOW = offset binary; SDIO HIGH = LVDS DDR
CS
SCLK
(Data fo
rmat)
SDIO
(CMOS LVDS DDR)
two's complement, CMOS
default mode at start-up
005aaa064
Fig 26. Default mode at start-up: SCLK HIGH = two’s complement; SDIO LOW = CMOS
ADC1212D_SER
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11.6.3 Register allocation map
Table 19. Register allocation map
Addr
(Hex)
Register name
R/W
Bit definition
Default
(Bin)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADCA
0003
0005
Channel index
R/W
R/W
RESERVED[5:0]
ADCB
1111 1111
Reset and
operating mode
SW_
RST
RESERVED[2:0]
-
-
-
OP_MODE[1:0]
0000
0000
0006
0008
0011
Clock
R/W
-
-
-
-
-
-
-
-
-
-
SE_SEL
DIFF_SE
INTREF_EN
OUTBUF
DAVINV
CLKDIV DCS_EN
0000
0001
Internal reference R/W
-
INTREF[2:0]
0000
0000
Output data
standard.
R/W
LVDS_
CMOS
OUTBUS_SWAP
DATA_FORMAT[1:0]
0000
0000
0012
0013
Output clock
Offset
R/W
R/W
-
-
-
-
-
DAVPHASE[2:0]
0000 1110
DIG_OFFSET[5:0]
0000
0000
0014
0015
0016
0017
Test pattern 1
Test pattern 2
Test pattern 3
Fast OTR
R/W
R/W
R/W
R/W
R/W
-
-
-
-
-
-
TESTPAT_SEL[2:0]
0000
0000
TESTPAT_USER[11:4]
0000
0000
TESTPAT_USER[3:0]
-
-
-
-
0000
0000
-
-
-
-
FASTOTR
FASTOTR_DET[2:0]
0000
0000
0020
0021
CMOS output
-
-
-
-
-
DAV_DRV[1:0]
DATA_DRV[1:0]
DATAI[1:0]
0000 1110
LVDS DDR O/P 1 R/W
RESERVED
DAVI[1:0]
RESERVED
0000
0000
0022
LVDS DDR O/P 2 R/W
-
-
-
-
BIT_BYTE_WISE
LVDS_INT_TER[2:0]
0000
0000
ADC1212D series
NXP Semiconductors
CMOS or LVDS DDR digital outputs
Table 20. Channel index control register (address 0003h) bit description
Default values are highlighted.
Bit
7 to 2
1
Symbol
Access
Value
111111 reserved
next SPI command for ADC B
ADC B not selected
Description
RESERVED[5:0]
ADCB
R/W
0
1
ADC B selected
0
ADCA
R/W
next SPI command for ADC A
ADC A not selected
ADC A selected
0
1
Table 21. Reset and operating mode control register (address 0005h) bit description
Default values are highlighted.
Bit
Symbol
Access
Value
Description
7
SW_RST
R/W
reset digital section
no reset
0
1
performs a reset on SPI registers
reserved
6 to 4
3 to 2
1 to 0
RESERVED[2:0]
000
00
-
not used
OP_MODE[1:0]
R/W
operating mode
normal (Power-up)
Power-down
00
01
10
11
Sleep
normal (Power-up)
Table 22. Clock control register (address 0006h) bit description
Default values are highlighted.
Bit
7 to 5
4
Symbol
-
Access
Value
Description
000
not used
SE_SEL
R/W
single-ended clock input pin select
0
CLKM
1
CLKP
3
DIFF_SE
R/W
differential/single-ended clock input select
0
1
0
fully differential
single-ended
reserved
2
1
RESERVED
CLKDIV
R/W
R/W
clock input divide by 2
disabled
0
1
enabled
0
DCS_EN
duty cycle stabilizer
disabled
0
1
enabled
ADC1212D_SER
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ADC1212D series
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CMOS or LVDS DDR digital outputs
Table 23. Internal reference control register (address 0008h) bit description
Default values are highlighted.
Bit
7 to 4
3
Symbol
Access
Value
Description
-
0000
not used
INTREF_EN
R/W
programmable internal reference enable
disable
0
1
active
2 to 0
INTREF[2:0]
R/W
programmable internal reference
0 dB (FS = 2 V)
000
001
010
011
100
101
110
111
−1 dB (FS = 1.78 V)
−2 dB (FS = 1.59 V)
−3 dB (FS = 1.42 V)
−4 dB (FS = 1.26 V)
−5 dB (FS = 1.12 V)
−6 dB (FS = 1 V)
reserved
Table 24. Output data standard control register (address 0011h) bit description
Default values are highlighted.
Bit
7 to 5
4
Symbol
Access
Value
Description
-
000
not used
LVDS_CMOS
R/W
output data standard: LVDS DDR or CMOS
CMOS
0
1
LVDS DDR
3
2
OUTBUF
R/W
R/W
output buffers enable
output enabled
0
1
output disabled (high Z)
output bus swap
no swapping
OUTBUS_SWAP
0
1
output bus is swapped (MSB becomes LSB and
vice versa)
1 to 0
DATA_FORMAT[1:0]
R/W
output data format
offset binary
00
01
10
11
two’s complement
gray code
offset binary
Table 25. Output clock register (address 0012h) bit description
Default values are highlighted.
Bit
7 to 4
3
Symbol
-
Access
Value
Description
0000
not used
DAVINV
R/W
output clock data valid (DAV) polarity
0
normal
1
inverted
ADC1212D_SER
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Preliminary data sheet
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ADC1212D series
NXP Semiconductors
CMOS or LVDS DDR digital outputs
Table 25. Output clock register (address 0012h) bit description …continued
Default values are highlighted.
Bit
Symbol
Access
Value
Description
2 to 0
DAVPHASE[2:0]
R/W
DAV phase select
000
001
010
011
100
101
110
111
output clock shifted (ahead) by 3 ns
output clock shifted (ahead) by 2.5 ns
output clock shifted (ahead) by 2 ns
output clock shifted (ahead) by 1.5 ns
output clock shifted (ahead) by 1 ns
output clock shifted (ahead) by 0.5 ns
default value as defined in timing section
output clock shifted (delayed) by 0.5 ns
Table 26. Offset register (address 0013h) bit description
Default values are highlighted.
Bit
Symbol
Access
Value
Description
7 to 6
5 to 0
-
00
not used
DIG_OFFSET[5:0]
R/W
digital offset adjustment
011111
...
+31 LSB
...
000000
...
0
...
100000
−32 LSB
Table 27. Test pattern register 1 (address 0014h) bit description
Default values are highlighted.
Bit
Symbol
Access
Value
Description
7 to 3
2 to 0
-
00000
not used
TESTPAT_SEL[2:0]
R/W
digital test pattern select
000
001
010
011
100
101
110
111
off
mid scale
−FS
+FS
toggle ‘1111..1111’/’0000..0000’
custom test pattern
‘0101..0101’
‘1010..1010.’
Table 28. Test pattern register 2 (address 0015h) bit description
Default values are highlighted.
Bit
Symbol
Access
Value
Description
7 to 0
TESTPAT_USER[11:4]
R/W
0000
0000
custom digital test pattern (bits 11 to 4)
ADC1212D_SER
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ADC1212D series
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CMOS or LVDS DDR digital outputs
Table 29. Test pattern register 3 (address 0016h) bit description
Default values are highlighted.
Bit
Symbol
Access
Value
0000
0000
Description
7 to 4
3 to 0
TESTPAT_USER[3:0]
-
R/W
custom digital test pattern (bits 3 to 0)
not used
Table 30. Fast OTR register (address 0017h) bit description
Default values are highlighted.
Bit
7 to 4
3
Symbol
-
Access
Value
Description
not used
0000
FASTOTR
R/W
fast OuT-of-Range (OTR) detection
disabled
0
1
enabled
2 to 0
FASTOTR_DET[2:0]
R/W
set fast OTR detect level
−20.56 dB
000
001
010
011
100
101
110
111
−16.12 dB
−11.02 dB
−7.82 dB
−5.49 dB
−3.66 dB
−2.14 dB
−0.86 dB
Table 31. CMOS output register (address 0020h) bit description
Default values are highlighted.
Bit
Symbol
Access
Value
Description
7 to 4
3 to 2
-
0000
not used
DAV_DRV[1:0]
R/W
drive strength for DAV CMOS output buffer
00
01
10
11
low
medium
high
very high
1 to 0
DATA_DRV[1:0]
R/W
drive strength for DATA CMOS output buffer
00
01
10
11
low
medium
high
very high
Table 32. LVDS DDR output register 1 (address 0021h) bit description
Default values are highlighted.
Bit
7 to 6
5
Symbol
Access
Value
00
Description
not used
-
RESERVED
0
reserved
ADC1212D_SER
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ADC1212D series
NXP Semiconductors
CMOS or LVDS DDR digital outputs
Table 32. LVDS DDR output register 1 (address 0021h) bit description …continued
Default values are highlighted.
Bit
Symbol
Access
Value
Description
4 to 3
DAVI[1:0]
R/W
LVDS current for DAV LVDS buffer
00
01
10
11
0
3.5 mA
4.5 mA
1.25 mA
2.5 mA
2
RESERVED
DATAI[1:0]
reserved
1 to 0
R/W
LVDS current for DATA LVDS buffer
00
01
10
11
3.5 mA
4.5 mA
1.25 mA
2.5 mA
Table 33. LVDS DDR output register 2 (address 0022h) bit description
Default values are highlighted.
Bit
7 to 4
3
Symbol
Access
Value
Description
-
0000
not used
BIT_BYTE_WISE
R/W
DDR mode for LVDS output
0
bit wise (even data bits output on DAV rising
edge / odd data bits output on DAV falling edge)
1
byte wise (MSB data bits output on DAV rising
edge / LSB data bits output on DAV falling edge)
2 to 0
LVDS_INT_TER[2:0]
R/W
internal termination for LVDS buffer (DAV and
DATA)
000
001
010
011
100
101
110
111
no internal termination
300 Ω
180 Ω
110 Ω
150 Ω
100 Ω
81 Ω
60 Ω
ADC1212D_SER
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ADC1212D series
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CMOS or LVDS DDR digital outputs
12. Package outline
HVQFN64: plastic thermal enhanced very thin quad flat package; no leads;
64 terminals; body 9 x 9 x 0.85 mm
SOT804-3
D
B
A
terminal 1
index area
A
1
E
A
c
detail X
e
1
1/2 e
C
v
w
C
C
A
B
e
b
L
y
1
y
C
17
32
33
16
e
E
h
e
2
1/2 e
1
48
terminal 1
index area
64
49
X
D
h
0
2.5
5 mm
scale
Dimensions
Unit
(1)
(1)
E
A
A
1
b
c
D
D
h
E
h
e
e
e
2
L
v
w
y
y
1
1
max 1.00 0.05 0.30
9.1 7.25 9.1 7.25
0.5
mm nom 0.85 0.02 0.21 0.2 9.0 7.10 9.0 7.10 0.5 7.5 7.5 0.4 0.1 0.05 0.05 0.1
min 0.80 0.00 0.18 8.9 6.95 8.9 6.95 0.3
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
sot804-3_po
References
Outline
version
European
projection
Issue date
IEC
- - -
JEDEC
- - -
JEITA
- - -
09-02-24
10-08-06
SOT804-3
Fig 27. Package outline SOT804-3 (HVQFN64)
ADC1212D_SER
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Preliminary data sheet
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NXP Semiconductors
CMOS or LVDS DDR digital outputs
13. Revision history
Table 34. Revision history
Document ID
Release date
Data sheet status
Change Supersedes
notice
ADC1212D_SER v.1
20100806
Preliminary data sheet -
-
ADC1212D_SER
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ADC1212D series
NXP Semiconductors
CMOS or LVDS DDR digital outputs
14. Legal information
14.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of an NXP Semiconductors product can reasonably be expected
14.2 Definitions
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
14.3 Disclaimers
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
ADC1212D_SER
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 01 — 6 August 2010
36 of 38
ADC1212D series
NXP Semiconductors
CMOS or LVDS DDR digital outputs
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
14.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
15. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
ADC1212D_SER
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 01 — 6 August 2010
37 of 38
ADC1212D series
NXP Semiconductors
CMOS or LVDS DDR digital outputs
16. Contents
1
2
3
4
5
General description. . . . . . . . . . . . . . . . . . . . . . 1
11.5.7
11.6
11.6.1
11.6.2
11.6.3
Output codes versus input voltage. . . . . . . . . 25
Serial Peripheral Interface (SPI) . . . . . . . . . . 25
Register description . . . . . . . . . . . . . . . . . . . . 25
Default modes at start-up. . . . . . . . . . . . . . . . 26
Register allocation map . . . . . . . . . . . . . . . . . 28
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2
12
13
Package outline. . . . . . . . . . . . . . . . . . . . . . . . 34
Revision history . . . . . . . . . . . . . . . . . . . . . . . 35
6
6.1
6.1.1
6.1.2
6.2
6.2.1
6.2.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
CMOS outputs selected . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
LVDS/DDR outputs selected. . . . . . . . . . . . . . . 5
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6
14
Legal information . . . . . . . . . . . . . . . . . . . . . . 36
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 36
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 37
14.1
14.2
14.3
14.4
15
16
Contact information . . . . . . . . . . . . . . . . . . . . 37
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7
8
9
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal characteristics . . . . . . . . . . . . . . . . . . 7
Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
10
Dynamic characteristics . . . . . . . . . . . . . . . . . 10
Dynamic characteristics . . . . . . . . . . . . . . . . . 10
Clock and digital output timing . . . . . . . . . . . . 11
SPI timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
10.1
10.2
10.3
11
11.1
Application information. . . . . . . . . . . . . . . . . . 14
Device control. . . . . . . . . . . . . . . . . . . . . . . . . 14
SPI and Pin control modes. . . . . . . . . . . . . . . 14
Operating mode selection. . . . . . . . . . . . . . . . 15
Selecting the output data standard. . . . . . . . . 15
Selecting the output data format. . . . . . . . . . . 15
Analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . 15
Input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Anti-kickback circuitry . . . . . . . . . . . . . . . . . . . 16
Transformer . . . . . . . . . . . . . . . . . . . . . . . . . . 17
System reference and power management . . 18
Internal/external references . . . . . . . . . . . . . . 18
Reference gain control . . . . . . . . . . . . . . . . . . 19
Common-mode output voltage (VO(cm)) . . . . . 19
Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Drive modes . . . . . . . . . . . . . . . . . . . . . . . . . 20
Equivalent input circuit . . . . . . . . . . . . . . . . . . 21
Duty cycle stabilizer . . . . . . . . . . . . . . . . . . . . 22
Clock input divider . . . . . . . . . . . . . . . . . . . . . 22
Digital outputs. . . . . . . . . . . . . . . . . . . . . . . . . 22
Digital output buffers: CMOS mode . . . . . . . . 22
Digital output buffers: LVDS DDR mode. . . . . 23
DAta Valid (DAV) output clock . . . . . . . . . . . . 24
OuT-of-Range (OTR) . . . . . . . . . . . . . . . . . . . 24
Digital offset . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Test patterns . . . . . . . . . . . . . . . . . . . . . . . . . . 25
11.1.1
11.1.2
11.1.3
11.1.4
11.2
11.2.1
11.2.2
11.2.3
11.3
11.3.1
11.3.2
11.3.3
11.3.4
11.4
11.4.1
11.4.2
11.4.3
11.4.4
11.5
11.5.1
11.5.2
11.5.3
11.5.4
11.5.5
11.5.6
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 6 August 2010
Document identifier: ADC1212D_SER
ADC1212D065HN/C1 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| ADC1212D080HN | NXP | Dual 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; CMOS or LVDS DDR digital outputs | 获取价格 |
|
| ADC1212D080HN-C1 | IDT | Dual 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; CMOS or LVDS DDR digital outputs | 获取价格 |
|
| ADC1212D080HN/C1 | NXP | PROPRIETARY METHOD ADC, PQCC64, 9 X 9 MM, 0.85 MM HEIGHT, PLASTIC, SOT804-3, VQFN-64 | 获取价格 |
|
| ADC1212D105HN | NXP | Dual 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; CMOS or LVDS DDR digital outputs | 获取价格 |
|
| ADC1212D105HN-C1 | IDT | Dual 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; CMOS or LVDS DDR digital outputs | 获取价格 |
|
| ADC1212D105HN/C1 | IDT | PROPRIETARY METHOD ADC, PQCC64, 9 X 9 MM, 0.85 MM HEIGHT, PLASTIC, SOT804-3, VQFN-64 | 获取价格 |
|
| ADC1212D125HN | NXP | Dual 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; CMOS or LVDS DDR digital outputs | 获取价格 |
|
| ADC1212D125HN-C1 | IDT | Dual 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; CMOS or LVDS DDR digital outputs | 获取价格 |
|
| ADC1212D125HN/C1 | IDT | PROPRIETARY METHOD ADC, PQCC64, 9 X 9 MM, 0.85 MM HEIGHT, PLASTIC, SOT804-3, VQFN-64 | 获取价格 |
|
| ADC12130 | NSC | Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold | 获取价格 |
|
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