CV149PA8 [IDT]
Processor Specific Clock Generator, 400MHz, PDSO56, TSSOP-56;型号: | CV149PA8 |
厂家: | INTEGRATED DEVICE TECHNOLOGY |
描述: | Processor Specific Clock Generator, 400MHz, PDSO56, TSSOP-56 时钟 光电二极管 外围集成电路 晶体 |
文件: | 总17页 (文件大小:427K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
IDTCV149
PROGRAMMABLE FLEXPC™
CLOCK FOR AMD K8
PROCESSOR ATI RS480
DESCRIPTION:
FEATURES:
IDTCV149is a 56pinclockdevice forAMDadvance K8processors. The
CPUoutputbufferisdesignedtosupportupto400MHzprocessor. Thisdevice
alsoimplementsBand-gapreferencedIREFtoreducetheimpactofVDDvariation
ondifferentialoutputs,whichcanprovidemorerobustsystemperformance.
EachCPU/SRCclockhasitsownSpreadSpectrumselection,whichallows
forisolatedchangesinsteadofaffecting otherclockgroups.
• One high precision N and SSC programmable PLL for CPU
• One high precision N and SSC programmable PLL for SRC[2:1]
• One high precision N and SSC programmable PLL for SRC0
[7:3] (PCI Express)
• One high precision PLL for 48MHz
• Band-gap circuit for differential outputs
• Support multiple spread spectrum modulation, down and
center
• Support SMBus block read/write, index read/write
• Selectable output strength for REF, PCI, 48MHz, HTT66
• Available in SSOP and TSSOP packages
KEYSPECIFICATION:
• CPU CLK cycle to cycle jitter < 85ps
• SRC CLK cycle to cycle jitter < 100ps
• Static PLL frequency divide error = 0 ppm
FUNCTIONALBLOCKDIAGRAM
SRC
SSC
N Programming
SRC[7:3], 0
PCI0
SRC
PCI/
SRC PLL
SSC
N Programming
14.318MHz
Osc
SRC/
Host/
SRC[2:1]
CLKREQ0#
CLKREQ1#
CPU PLL
SSC
N Programming
CPU[1:0]
HTT66
TURBO1#
USB48
Fixed PLL
No SSC
48MHz/
24_48MHz
REF[2:0]
Reset#
OUTPUTTABLE
CPU
CLKREQ
SRC
HTT66
PCI
TURBO
USB48
24_48
REF
RESET#
2
2
8
1
1
1
1
1
3
1
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
COMMERCIAL TEMPERATURE RANGE
MAY 2004
1
© 2004 Integrated Device Technology, Inc.
DSC - 6497/2
IDTCV149
PROGRAMMABLEFLEXPC™CLOCKFORAMDK8PROCESSORATIRS480
COMMERCIALTEMPERATURERANGE
PINCONFIGURATION
CPU AND SRC SPREAD SPECTRUM
MAGNITUDECONTROL
SMC[2:0]
000
%
XIN
XOUT
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VDD_REF
VSS_REF
REF0
OFF
2
001
-0.25
- 0.5
VDD_48
3
010
REF1
USB_48
4
011
-0.75
±0.125
±0.25
±0.375
±0.5
5
VSS_48
REF2
100
(1)CLK_STOP
SCL
6
VDD_PC1
PCI0
101
7
110
8
SDA
(1) SEL24/24_48#
VSS_PCI
VDD_HTT
HTT66
111
9
CLKREQ0#
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
CLKREQ1#
SRCT7
VSS_HTT
CPUT0
CPUC0
VDD_CPU
SESIGNALSTRENGTHSELECTION
SRCC7
Str[1:0]
Strength
0.6x
VDD_SRC
(2)
00
01
10
11
RESET#
VSS_CPU
0.8x
SRCT6
SRCC6
SRCT5
CPUT1
CPUC1
1 x
1.2x
VDDA
VSSA
IREF
SRCC5
VSS_SRC
VDD_SRC
SRCT4
VSS_SRC
VDD_SRC
SRCT0
PCI (BASED ON SRC = 100MHz)
SRCC4
SRCT3
PCIS[1:0]
PCI
33.33
36.36
40
SRCC0
VDD_SRC
VSS_SRC
SRCT1
00
01
10
11
SRCC3
(2) TURBO1
30.77
SRCT2
SRCC2
SRCC1
NOTES:
1. Internal 130KΩ pull-down resistor.
2. Tristate at power on to be compatible with ATI pin definition.
SSOP/ TSSOP
TOP VIEW
2
IDTCV149
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPC™CLOCKFORAMDK8PROCESSORATIRS480
PINDESCRIPTION
Pin Name
XIN
Type
IN
Pin #
Description
XTALin
1
XOUT
PCI0
OUT
OUT
OUT
OUT
I N
2
XTALout
50
PCI clock
HTT66
USB48
Turbo1
47
66.66 MHz
48MHz
4
26
Turbofrequencyselect
Differentialclock
CPUC[1:0]
CPUT[1:0]
OUT
40, 41, 44, 45
SRCC[7:0]
SRCT[7:0]
OUT
12, 13, 16, 17, 18, 19,
22, 23, 24, 25, 27, 28,
Differentialclock
29, 30, 33, 34
IREF
REF[1:0]
REF2
OUT
OUT
OUT
IN
37
53,54
52
10
11
8
Differentialclockreferencecurrent
14.318MHz
14.318MHz
CLKREQ0#
CLKREQ1#
SDA
SRC OE control, see bytes 3, 4
SRC OE control, see bytes 3, 4
SMBus data
IN
I/O
IN
SCL
7
SMBus clock
SEL24/24_48#
CLK_STOP
RESET#
IN
9
Latched select input for 24 or 48MHz output. 1 = 24MHz, 0 = 48MHz.
Active HIGH, drives all clocks to LOW (except CPU clocks)
Resetoutputsignal,OpenDrain
IN
6
OUT,
OD
15
3
IDTCV149
PROGRAMMABLEFLEXPC™CLOCKFORAMDK8PROCESSORATIRS480
COMMERCIALTEMPERATURERANGE
SMPROTOCOL
INDEXBLOCK WRITEPROTOCOL
INDEXBLOCKREADPROTOCOL
Mastercanstopreadinganytimebyissuingthestopbitwithoutwaiting
untilNthbyte(bytecountbit30-37).
Bit
1
# of bits
From
Master
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Description
1
8
1
8
1
8
1
8
1
8
1
Start
D2h
2-9
Bit
1
# of bits
From
Master
Master
Slave
Master
Slave
Master
Master
Slave
Slave
Description
10
Ack (Acknowledge)
Registeroffsetbyte(startingbyte)
Ack (Acknowledge)
Byte count, N (0 is not valid)
Ack (Acknowledge)
firstdatabyte(Offsetdatabyte)
Ack (Acknowledge)
2nddatabyte
1
8
1
8
1
1
8
1
8
Start
D2h
11-18
19
2-9
10
Ack (Acknowledge)
Registeroffsetbyte(startingbyte)
Ack (Acknowledge)
RepeatedStart
20-27
28
11-18
19
29-36
37
20
21-28
29
D3h
38-45
46
Ack (Acknowledge)
Ack (Acknowledge)
:
30-37
Byte count, N (block read back of N
bytes), power on is 8
38
1
8
1
8
Master
Slave
Master
Slave
Ack (Acknowledge)
firstdatabyte(Offsetdatabyte)
Ack (Acknowledge)
2nddatabyte
Master
Slave
Nthdatabyte
39-46
47
Acknowledge
Master
Stop
48-55
Ack (Acknowledge)
:
Master
Slave
Ack (Acknowledge)
Nthdatabyte
Notacknowledge
Stop
Master
INDEX BYTE READ
INDEX BYTE WRITE
Setting bit[11:18] = starting address. After reading back the first data byte,
masterissuesStopbit.
Settingbit[11:18]=startingaddress,bit[20:27]=01h.
4
IDTCV149
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPC™CLOCKFORAMDK8PROCESSORATIRS480
BYTE 0
Bit
Output(s)Affected
Description/Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
SRCT7, SRCC7
SRCT6, SRCC6
SRCT5, SRCC5
SRCT4, SRCC4
SRCT3, SRCC3
SRCT2, SRCC2
SRCT1, SRCC1
SRCT0, SRCT0
Outputenable
Outputenable
Outputenable
Outputenable
Outputenable
Outputenable
Outputenable
Outputenable
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
RW
RW
RW
RW
RW
RW
RW
RW
1
1
1
1
1
1
1
1
BYTE 1
Bit
Output(s)Affected
Description/Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
USB48
REF2
Outputenable
Outputenable
Outputenable
Outputenable
Outputenable
Outputenable
Outputenable
Outputenable
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
RW
RW
RW
RW
RW
RW
RW
RW
1
1
1
1
1
1
1
1
REF1
REF0
24_48MHz
CPUT1, CPUC1
CPUT0, CPUC0
HTT66
BYTE 2
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
PCI0
Reserved
PCI0 SEL1
PCI0 SEL0
Reserved
SRCs
Outputenable
Tristate
Enable
RW
RW
RW
RW
RW
RW
RW
RW
1
0
0
0
0
0
0
0
see PCI select table
SRCT PWRDWN drive mode
CPUT1 PWRDWN drive mode
CPUT0 PWRDWN drive mode
Driven in power down
Driven in power down
Driven in power down
Tristateinpowerdown
Tristateinpowerdown
Tristateinpowerdown
CPUT1
CPUT0
BYTE 3
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
SRC7
SRC6
CLKREQ0#
CLKREQ0#
CLKREQ0#
CLKREQ0#
CLKREQ0#
CLKREQ1#
CLKREQ1#
CLKREQ1#
CLKREQ1#
CLKREQ1#
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
0
SRC5
Controlled by CLKREQB#
or CLKREQA#
SRC4
SRC3
Reserved
Reserved
SRC0
Controlled by CLKREQB#
or CLKREQA#
CLKREQ0#
CLKREQ1#
5
IDTCV149
PROGRAMMABLEFLEXPC™CLOCKFORAMDK8PROCESSORATIRS480
COMMERCIALTEMPERATURERANGE
BYTE 4
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
SRC7
SRC6
NotControlled
NotControlled
NotControlled
NotControlled
NotControlled
Controlled
Controlled
Controlled
Controlled
Controlled
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
0
SRC5
When CLKREQ is HIGH,
OutputisHi-Z
SRC4
SRC3
Reserved
Reserved
SRC0
When CLKREQ is HIGH,
OutputisHi-Z
NotControlled
Controlled
BYTE 5
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
HTT66
HTT66
HTT66strengthselection
RW
RW
RW
RW
RW
RW
RW
RW
1
0
1
0
1
0
1
0
PCIStrC1
PCIStrC0
REFStr1
REFStr0
48MHStr1
48MHzStr0
PCIstrengthselection
REFstrengthselection
USB48MHzstrengthselection
BYTE 6
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
Reserve
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
0
SRC0, SR[7:3], SMC2
SRC0, SR[7:3], SMC1
SRC0, SR[7:3], SMC0
Reserved
SRC0, SRC[7:3] SSC control
(see SMC table)
SRC[2:1], SMC2
SRC[2:1], SMC1
SRC[2:1], SMC0
SRC[2:1] control (see SMC table)
BYTE 7
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
Revision ID
Revision ID
Revision ID
Revision ID
Vendor ID
Vendor ID
Vendor ID
Vendor ID
R
R
R
R
R
R
R
R
0
0
0
0
0
1
0
1
6
IDTCV149
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPC™CLOCKFORAMDK8PROCESSORATIRS480
BYTE 8 (INDEX BLOCK READ BYTE COUNT)
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
1
0
1
1
0
BYTE 9
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
Reserved
Reserved
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
CPU SMC2
CPU SMC1
CPU SMC0
CPU PLL SSC control
(see SMC table)
BYTE10
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
WD_1_Timer7
WD_1_Timer6
WD_1_Timer5
WD_1_Timer4
WD_1_Timer3
WD_1_Timer2
WD_1_Timer1
WD_1_Timer0
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
1
0
1
1
WatchDog_1_Alarm timer
Defaultis11*290ms
BYTE11
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
7
6
5
4
3
CPU_N8
Reserved
Reserved
Reserved
WDRB
RW
RW
RW
RW
R
0
0
0
0
0
Alarmreadback,
Alarm
reset by WD disable
2
1
0
RESET#(1)
Reserved
ResetEnable
Disable
Disable
ResetEnable
RW
RW
RW
0
0
0
WatchDogEnable
WatchDogEnable
Enable
7
IDTCV149
PROGRAMMABLEFLEXPC™CLOCKFORAMDK8PROCESSORATIRS480
COMMERCIALTEMPERATURERANGE
BYTE12
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
CPU_N7
CPU_N6
RW
RW
RW
RW
RW
RW
RW
RW
1
0
0
1
0
1
1
0
CPU_N5
CPU_N4
CPU CLK = N*Resolution
Resolution=1.3333
CPU_N3
CPU_N2
CPU_N1
CPU_N0, LSB
BYTE13
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
SRC1_N7, MSB
SRC1_N6
RW
RW
RW
RW
RW
RW
RW
RW
1
0
0
1
0
1
1
0
SRC1_N5
SRC2, SRC1
SRC1_N4
SRC CLK = N*Resolution
Resolution=0.66667
SRC1_N3
SRC1_N2
SRC1_N1
SRC1_N0, LSB
BYTE14
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
SRC0_N7, MSB
SRC0_N6
RW
RW
RW
RW
RW
RW
RW
RW
1
0
0
1
0
1
1
0
SRC0_N5
SRC0_N4
SRC[7:3], SRC0
SRC CLK = N*Resolution
Resolution=0.66667
SRC0_N3
SRC0_N2
SRC0_N1
SRC0_N0, LSB
BYTE15
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
Disable
Disable
Enable
Enable
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
0
CPU N programming enable
SRC1, SRC2 N Programming enable
Disable
Enable
SRC0, SRC[7:3] N Programming enable
Disable
Enable
Turbo1enable
Turbo
Disable
Enable
TurboActiveSelection
Active HIGH
Active LOW
Reserved
T1CN8
8
IDTCV149
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPC™CLOCKFORAMDK8PROCESSORATIRS480
BYTE16
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
T1CN7
T1CN6
T1CN5
T1CN4
T1CN3
T1CN2
T1CN1
T1CN0
RW
RW
RW
RW
RW
RW
RW
RW
1
0
0
1
0
1
1
0
Turbo1 CPU PLL N setting
CLK = N*Resolution
Resolution=1.3333
BYTE17
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
TSRC1_N7, MSB
TSRC1_N6
RW
RW
RW
RW
RW
RW
RW
RW
1
0
0
1
0
1
1
0
TSRC1_N5
Turbo1
TSRC1_N4
SRC2, SRC1
TSRC1_N3
SRC CLK = N*Resolution
Resolution=0.66667
TSRC1_N2
TSRC1_N1
TSRC1_N0, LSB
BYTE 18 (RESERVED FOR USER)
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
0
BYTE 19 (RESERVED FOR USER)
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
0
9
IDTCV149
PROGRAMMABLEFLEXPC™CLOCKFORAMDK8PROCESSORATIRS480
COMMERCIALTEMPERATURERANGE
BYTE 20 (RESERVED FOR USER)
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
0
BYTE21
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
7
6
5
4
3
2
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Test_scl
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
On chiptestmodeenable
CLKoutputsenable
Normal
Normal
SCLK = 1, CLK outputs = 1
SCLK = 0, CLK outputs = 0
CLKoutputs=Tristate
0
Test_hiz
RW
0
BYTE 62 = 70h
BYTE 63 = 13h
ABSOLUTEMAXIMUMRATINGS(1)
Symbol
VDDA
VDD
Description
3.3V Core Supply Voltage
3.3V I/O Supply Voltage
3.3V Input HIGH
Min
Max
4.6
4.6
4.6
Unit
V
V
VIH
V
VID
3.3V Input LOW
–0.5
–65
V
TS
Storage Temperature
+150
°C
V
ESD Prot Input ESD Protection
Human Body Model
NOTE:
2000
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
10
IDTCV149
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPC™CLOCKFORAMDK8PROCESSORATIRS480
ELECTRICAL CHARACTERISTICS - INPUT / SUPPLY / COMMON OUTPUT
PARAMETERS
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%
Symbol
VIH
Parameter
Input HIGH Voltage
Input LOW Voltage
Test Conditions
Min.
Typ.
—
Max.
Unit
V
3.3V ± 5%
3.3V ± 5%
VDD
2
VSS - 0.3
0.7
VDD + 0.3
VIL
—
0.8
V
VIH_FS
VIL_FS
IIH
3.3V Input HIGH Voltage
3.3V Input LOW Voltage
Input HIGH Current
Input LOW Current
—
VDD + 0.3
V
VSS - 0.3
–5
—
0.35
5
V
VIN = VDD
—
µA
µA
µA
mA
MHz
nH
IIL1
VIN = 0V, inputs with no pull-up resistors
VIN = 0V, inputs with pull-up resistors
Full active, CL = full load
–5
—
—
—
400
—
7
IIL2
Input LOW Current
–200
—
—
IDD3.3OP
FI
Operating Supply Current
Input Frequency(1)
—
VDD = 3.3V
—
14.31818
—
LPIN
Pin Inductance(2)
—
CIN
Logic inputs
—
—
5
COUT
CINX
TSTAB
Input Capacitance(2)
Output pin capacitance
X1 and X2 pins
—
—
6
pF
—
—
5
Clock Stabilization(2,3)
From VDD power-up
Triangular modulation
—
—
1.8
33
ms
Modulation Frequency(2)
30
—
KHz
NOTES:
1. Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs.
2. This parameter is guaranteed by design, but not 100% production tested.
3. See TIMING DIAGRAMS for timing requirements.
11
IDTCV149
PROGRAMMABLEFLEXPC™CLOCKFORAMDK8PROCESSORATIRS480
COMMERCIALTEMPERATURERANGE
ELECTRICALCHARACTERISTICS-SRC0.7CURRENTMODEDIFFERENTIALPAIR
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 2pF
Symbol
ZO
Parameter
Test Conditions
Min.
3000
2.4
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max.
—
Unit
Ω
Current Source Output Impedance(1) VO = VX
VOH3
VOL3
Output HIGH Voltage
Output LOW Voltage
Voltage HIGH(1)
Voltage LOW(1)
IOH = -1mA
IOL = 1mA
—
V
—
0.4
V
VHIGH
VLOW
VOVS
Statistical measurement on single-ended signal using
oscilloscope math function
660
–300
—
1150
150
1150
—
mV
Max Voltage(1)
Measurement on single-ended signal using absolute value
mV
VUDS
Min Voltage(1)
–300
250
—
VCROSS(ABS) Crossing Voltage (abs)(1)
550
140
300
10.003
—
mV
mV
ppm
ns
d - VCROSS
Crossing Voltage (var)(1)
Long Accuracy(1,2)
Average Period(2)
Absolute Min Period(1,2)
Rise Time(1)
Variation of crossing over all edges
See TPERIOD Min. - Max. values
100MHz nominal
ppm
–300
9.997
9.912
175
175
—
TPERIOD
TABSMIN
100MHz nominal
ns
tR
tF
VOL = 0.175V, VOH = 0.525V
VOL = 0.175V, VOH = 0.525V
700
700
125
125
55
ps
Fall Time(1)
ps
d-tR
Rise Time Variation(1)
Fall Time Variation(1)
Duty Cycle(1)
ps
d-tF
—
ps
dT3
Measurement from differential waveform
Measurement from differential waveform
45
%
tJCYC-CYC
SKEW
Jitter, Cycle to Cycle(1)
Pin-to-Pin Skew(1)
TSU_SRC(1,3)
—
125
ps
VT = 50%
—
—
—
—
—
—
250
60
ps
ns
ns
SRC STOP response to CLKREQ#
SRC START response to CLKREQ#
TDRIVE_SRC(1,3)
60
NOTES:
1. This parameter is guaranteed by design, but not 100% production tested.
2. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz.
3. See TIMING DIAGRAMS for timing requirements.
12
IDTCV149
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPC™CLOCKFORAMDK8PROCESSORATIRS480
ELECTRICALCHARACTERISTICS-CPUDIFFERENTIALPAIR(SSCENABLEAND
DISABLE)
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 2pF
Symbol
tR
Parameter(1)
Rise Edge Rate
Test Conditions
Min.
2
Typ.
—
Max.
10
Unit
V/ns
V/ns
V
tF
Fall Edge Rate
2
—
10
VDIFF
∆VDIFF
Differential Voltage (single end)
Change in VDIFF_DC Magnitude
Common Mode Voltage
Change in Common Mode Voltage
Jitter, Cycle to Cycle
0.4
–150
1.05
–200
—
1.25
—
2.3
+150
1.45
+200
200
mV
V
VCM
∆VCM
1.25
—
mV
ps
tCCJITTER
—
tJA
tFS
Jitter Accumulated
Frequency Stabilization from
Power-Up
–1000
—
—
—
+1000
3
ps
ms
RON
Output Impedance
15
47
35
50
—
55
53
Ω
%
Duty Cycle Duty Cycle
ppm
Long Accuracy(2)
Average Period(2)
See TPERIOD Min. - Max. values
–300
+300
ppm
TPERIOD
200MHz nominal
250MHz nominal
4.9985
3.9988
—
—
5.0015
4.0012
ns
NOTES:
1. Parameters guaranteed by design, but not 100% production tested.
2. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz.
13
IDTCV149
PROGRAMMABLEFLEXPC™CLOCKFORAMDK8PROCESSORATIRS480
COMMERCIALTEMPERATURERANGE
ELECTRICAL CHARACTERISTICS - PCICLK / PCICLK_F, HTT66
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 10 - 30pF
Symbol
Parameter
Test Conditions
See Tperiod Min. - Max. values
33.33MHzoutputnominal
33.33MHzoutputspread
IOH = -1mA
Min.
—
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max.
300
30.009
30.1598
—
Unit
ppm
ns
ppm
LongAccuracy(1,2)
ClockPeriod(2)
TPERIOD
29.991
29.991
2.4
—
VOH
VOL
IOH
Output HIGH Voltage
OutputLOWVoltage
Output HIGH Current
V
V
IOL = 1mA
0.55
—
VOH at Min. = 1V
VOH at Max. = 3.135V
VOL at Min. = 1.95V
VOL at Max. = 0.4V
Risingedgerate
-33
—
mA
-33
IOL
OutputLOWCurrent
30
—
mA
—
38
EdgeRate(1)
1
4
V/ns
V/ns
ns
EdgeRate(1)
Fallingedgerate
1
4
tR1
tF1
Rise Time(1)
VOL = 0.8V, VOH = 2V
VOL = 0.8V, VOH = 2V
VT = 1.5V
0.3
0.3
45
1.2
Fall Time(1)
Duty Cycle(1)
Jitter, Cycle to Cycle(1)
1.2
ns
dT1
55
%
tJCYC-CYC
VT = 1.5V
—
500
ps
NOTES:
1. This parameter is guaranteed by design, but not 100% production tested.
2. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz.
ELECTRICALCHARACTERISTICS-24_48MHZ,48MHZ,USB
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 10 - 20pF
Symbol
Parameter
Test Conditions
See Tperiod Min. - Max. values
48MHzoutputnominal
IOH = -1mA
Min.
—
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max.
300
20.834
—
Unit
ppm
ns
ppm
LongAccuracy(1,2)
ClockPeriod(2)
TPERIOD
VOH
20.8257
2.4
—
Output HIGH Voltage
OutputLOWVoltage
Output HIGH Current
V
VOL
IOL = 1mA
0.55
—
V
IOH
VOH at Min. = 1V
VOH at Max. = 3.135V
VOL at Min. = 1.95V
VOL at Max. = 0.4V
Risingedgerate
-29
—
mA
-23
—
IOL
OutputLOWCurrent
29
mA
—
27
EdgeRate(1)
1
2
V/ns
V/ns
ns
EdgeRate(1)
Fallingedgerate
1
2
tR1
tF1
Rise Time(1)
VOL = 0.8V, VOH = 2V
VOL = 0.8V, VOH = 2V
VT = 1.5V
0.5
0.5
45
1.2
1.2
55
Fall Time(1)
Duty Cycle(1)
Jitter, Cycle to Cycle(1)
ns
dT1
%
tJCYC-CYC
VT = 1.5V
—
350
ps
NOTES:
1. This parameter is guaranteed by design, but not 100% production tested.
2. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz.
14
IDTCV149
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPC™CLOCKFORAMDK8PROCESSORATIRS480
ELECTRICALCHARACTERISTICS-REF-14.318MHZ
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 10 - 20pF
Symbol
Parameter
Test Conditions
See Tperiod Min. - Max. values
14.318MHzoutputnominal
IOH = -1mA
Min.
—
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max.
0
Unit
ppm
ns
ppm
LongAccuracy(1)
TPERIOD
VOH
Clock Period
69.827
2.4
—
69.855
—
OutputHIGHVoltage(1)
OutputLOWVoltage(1)
Output HIGH Current
V
VOL
IOL = 1mA
0.4
—
V
IOH
VOH at Min. = 1V
VOH at Max. = 3.135V
VOL at Min. = 1.95V
VOL at Max. = 0.4V
Risingedgerate
-33
—
mA
-33
—
IOL
OutputLOWCurrent
30
mA
—
38
EdgeRate(1)
1
4
V/ns
V/ns
ns
EdgeRate(1)
Fallingedgerate
1
4
tR1
tF1
Rise Time(1)
VOL = 0.8V, VOH = 2V
VOL = 0.8V, VOH = 2V
VT = 1.5V
0.3
0.3
45
1.2
1.2
55
Fall Time(1)
Duty Cycle(1)
Jitter, Cycle to Cycle(1)
ns
dT1
%
tJCYC-CYC
VT = 1.5V
—
1000
ps
NOTE:
1. This parameter is guaranteed by design, but not 100% production tested.
15
IDTCV149
PROGRAMMABLEFLEXPC™CLOCKFORAMDK8PROCESSORATIRS480
COMMERCIALTEMPERATURERANGE
CLKREQ#ASSERTION
TheclocksamplestheCLKREQ#signalonarisingedgeofSRCclock.AfterdetectingtheCLKREQ#assertionlow,allcontrolledSRCclockswillbetristate
ontheirnexthightolowtransition.
tSU_SRC
CLKREQ#
SRC
SRC#
CLKREQ#-DE-ASSERTION
Thede-assertionoftheCLKREQ#signalistobesampledontherisingedgeoftheSRCfreerunningclockdomain.AfterdetectingCLKREQ#de-assertion,
allcontrolledSRCclockswillresumeinaglitchfreemanner.
tDRIVE_SRC
CLKREQ#
SRC
SRC#
16
IDTCV149
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPC™CLOCKFORAMDK8PROCESSORATIRS480
ORDERINGINFORMATION
IDTCV XXX
Device Type
XX
Package
X
Grade
Blank Commercial Temperature Range
(0°C to +70°C)
Small Shrink Outline Package
Thin Shrink Small Outline Package
TSSOP - Green
PV
PA
PAG
Programmable FlexPC™ Clock for AMD K8
Processor ATI RS480
149
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17
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