ICS357G-XXT [IDT]
Clock Generator, 200MHz, CMOS, PDSO16, TSSOP-16;
| 型号： | ICS357G-XXT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, 200MHz, CMOS, PDSO16, TSSOP-16 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总6页 (文件大小：84K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY INFORMATION
ICS357
™
PECL/LVDS Spread Spectrum QTClock
Description
Features
• Packaged as 16 pin TSSOP and SOIC
• Quick turn frequency programming allows
samples as quickly as one day
The ICS357 quick turn (QTClock™) generates a high
quality, high frequency, spread spectrum differential
PECL/LVDS clock from a clock or crystal input. The
ICS357 contains a One-Time Programmable (OTP)
ROM which is factory programmed with PLL divider
values to output a broad range of frequencies up to
200 MHz. This allows customer requests for different
input and output frequencies to be shipped in one to
three days.
• Ideal for the High Speed Serial ATA applications
• Spread spectrum outputs
• Output frequencies up to 200 MHz at 3.3V
• Input crystal frequency of 5 - 27 MHz
• Input clock frequency of 2 - 50 MHz
• Duty cycle of 45/55
Using Phase-Locked-Loop (PLL) techniques, the
device runs from a standard fundamental mode,
inexpensive crystal, or clock. It can replace multiple
devices, saving board space and cost.
• Operating voltage of 3.3 V or 5 V
• Advanced, low power CMOS process
Block Diagram
VDD
RES
VDD
OTP
3
ROM
with PLL
Divider
Values
PLL with
Spread
Spectrum
PECL
S2:S0
Crystal
PECL
or clock
input
Resistors on PECL are
identical (but not shown)
X1/ICLK
Crystal
Oscillator
REFOUT
X2
PDTS (all outputs, oscillator, and PLL)
Capacitors are required with a crystal input
for accurate tuning of the clock.
MDS 357 B
1
Revision 032301
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose, CA, 95126 •(408) 295-9800tel• www.icst.com
PRELIMINARY INFORMATION
ICS357
™
PECL/LVDS Spread Spectrum QTClock
Pin Assignment
1
2
3
4
5
6
7
X1/ICLK
S0
X2
16
15
14
13
VDD
S1
PDTS
REFOUT
VDD
S2
12
11
10
9
VDD
GND
PECL
PECL
GND
NC
RES
8
16 pin TSSOP or SOIC
Pin Descriptions
Number Name Type Description
1
2
X1/ICLK
S0
XI Crystal connection. Connect to fundamental mode crystal or clock input.
I
I
Select pin 0 for frequency table/chip control. Internal pull-up resistor.
Select pin 1 for frequency table/chip control. Internal pull-up resistor.
Buffered crystal oscillator (or input reference clock) output. Note 1.
Connect to +3.3V or +5V. Must be same voltage as pins 12 and 15.
Connect to ground.
3
S1
4
REFOUT
VDD
GND
NC
O
P
P
-
5
6
7
No Connect. Do not connect anything to this pin.
8
RES
PECL
PECL
GND
VDD
S2
-
External resistor for setting common mode.
9
O
O
P
P
I
Differential clock output. Can be PECL or LVDS. See app note MAN09.
Differential clock output. Can be PECL or LVDS. See app note MAN09.
Connect to ground.
10
11
12
13
14
15
16
Connect to +3.3V or +5V. Must be same voltage as pins 5 and 15.
Select pin 2 for frequency table/chip control. Internal pull-up resistor.
All-chip Power Down when low. Internal pull-up resistor.
Connect to +3.3V or +5V. Must be same voltage as pins 5 and 12.
PDTS
VDD
X2
I
P
XO Crystal connection. Leave unconnected for clock input.
Key: XI, XO = crystal connections, I = Input, O = output, P = power supply connection
Note 1: This is a CMOS (rail-to-rail) output clock. For less noise on PECL clocks, program this output to the
off state.
MDS 357 B
2
Revision 032301
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose, CA, 95126 •(408) 295-9800tel• www.icst.com
PRELIMINARY INFORMATION
ICS357
™
PECL/LVDS Spread Spectrum QTClock
Device Configuration
The ICS357 QTClock can be programmed for up to 8 input/output frequency combinations, or spread amounts. All
chip functions are controlled from an OTP ROM which has 3 input control lines (S2, S1, S0). Each address location
gives control of the following:
1) Multiplier ratios can be selected.
2) The spread spectrum function can be enabled or disabled.
3) The spread amount can be selected.
The specification is complete when the ICS357 QTClock Order Form accompanies this data sheet. The order form
lists the input and CLK actual frequencies, as well as any other available options. This unique configuration is given
a two character alphanumeric programming code (ICS357-xx), which must be specified when referring to samples.
External Components / Crystal Selection
The ICS357 requires a 0.01µF decoupling capacitor to be connected between VDD and GND on pins 5 and 6, and
another between pins 12 and 11. These must be connected close to the ICS357 to minimize lead inductance. No
other external power supply filtering is required for this device, but a large tantalum capacitor of 2.2 to 10 µF will
reduce the output jitter in noisy environments. The outputs should be connected to a resistor divider network, as
indicated on the block diagram, and a resistor should be connected from pin RES to VDD. All of these resistor
values can be determined from our application note MAN09. For a crystal input, a parallel resonant, fundamental
mode crystal should be used. Crystal capacitors must be connected from each of the pins X1 and X2 to Ground.
The value (in pF) of these crystal caps should equal (C -6pf)*2, where C is the crystal load capacitance in pF. As an
L
L
example, for a crystal with 16 pF load capacitance, each crystal capacitor would be 20 pF [(16 - 6pf)*2 = 20].
For a clock input, connect to X1/ICLK and leave X2 unconnected (no capacitors on either X1 or X2).
MDS 357 B
3
Revision 032301
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose, CA, 95126 •(408) 295-9800tel• www.icst.com
PRELIMINARY INFORMATION
ICS357
™
PECL/LVDS Spread Spectrum QTClock
Electrical Specifications
Parameter
Conditions
Minimum Typical Maximum Units
ABSOLUTE MAXIMUM RATINGS (stresses beyond these can permanently damage the device)
Supply Voltage, VDD
Inputs
Referenced to GND
Referenced to GND
Referenced to GND
7
VDD+0.5
VDD+0.5
70
V
-0.5
-0.5
0
V
Clock Output
V
Ambient Operating Temperature
Soldering Temperature
Storage temperature
°C
°C
°C
Max of 10 seconds
260
-65
150
DC CHARACTERISTICS (VDD = 3.3V unless otherwise noted)
Operating Voltage, VDD
3.13
5.5
(VDD/2)-1
0.8
V
V
Input High Voltage, VIH, ICLK only
Input Low Voltage, VIL, ICLK only
Input High Voltage, VIH
ICLK (Pin 1)
ICLK (Pin 1)
PDTS, S0, S1, S2
PDTS, S0, S1, S2
Note 1
(VDD/2)+1
V
2
V
Input Low Voltage, VIL
V
Output High Voltage, VOH
Output Low Voltage, VOL
Settable
V
Note 1
Settable
V
IDD Operating Supply Current, 20 MHz crystal No Load, 100MHz
On-Chip Pull-up Resistor, Inputs
20
TBD
TBD
4
mA
kW
W
pF
On-Chip Pull-down Resistor, Outputs
Input Capacitance, Inputs
AC CHARACTERISTICS (VDD = 3.3V unless otherwise noted)
Input Frequency, Crystal Input
Input Frequency, Clock Input
Output Frequency
5
27
50
MHz
MHz
MHz
%
2
40
49
200
51
Output Clock Duty Cycle
Absolute Clock Period Jitter
One Sigma Clock Period Jitter
Power-up Time, PDTS goes high until CLK out
Spread Modulat ion Frequency
Deviation from mean
±TBD
TBD
8
ps
ps
20
ms
3 0 -3 3
kHz
Note 1: The VOH and VOL levels for the PECL/LVDS outputs are set by the external resistor values. Refer to
MAN09 for proper values.
MDS 357 B
4
Revision 032301
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose, CA, 95126 •(408) 295-9800tel• www.icst.com
PRELIMINARY INFORMATION
ICS357
™
PECL/LVDS Spread Spectrum QTClock
Package Outline and Package Dimensions
(For current dimensional specifications, see JEDEC Publication No. 95.)
16 pin TSSOP
Inches
Min
--
Millimeters
Symbol
Max
Min
--
Max
A
A1
b
0.047
1.20
0.15
0.30
0.20
5.10
E1
E
0.002 0.006 0.05
0.007 0.012 0.19
0.0035 0.008 0.09
0.193 0.201 4.90
c
D
e
INDEX
AREA
.0256 BSC
0.65 BSC
6.40 BSC
1
2
E
.252 BSC
E1
L
0.169 0.177 4.30
0.018 0.030 0.45
4.50
0.75
D
A
A1
c
b
L
e
16 pin SOIC narrow
Inches
Millimeters
Symbol
Min
Max
Min
Max
1.75
0.24
0.51
0.24
A
A1
B
0.0532 0.0688 1.35
0.0040 0.0098 0.10
0.0130 0.0200 0.33
0.0075 0.0098 0.19
E
H
INDEX
AREA
C
D
E
0.3859 0.3937 9.80 10.00
0.1497 0.1574 3.80
4.00
e
.050 BSC
1.27 BSC
1
H
h
0.2284 0.2440 5.80
0.0099 0.0195 0.25
0.0160 0.0500 0.41
6.20
0.50
1.27
h x 45°
D
L
A
A1
C
B
e
L
MDS 357 B
5
Revision 032301
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose, CA, 95126 •(408) 295-9800tel• www.icst.com
PRELIMINARY INFORMATION
ICS357
™
PECL/LVDS Spread Spectrum QTClock
Ordering Information
Part/Order Number
Marking
Package
Shipping
Tubes
Temperature
0 to 70 °C
0 to 70 °C
0 to 70 °C
0 to 70 °C
ICS357G-xx
ICS357G-xx
ICS357G-xx
ICS357M-xx
ICS357M-xx
16 pin TSSOP
16 pin TSSOP
16 pin SOIC
16 pin SOIC
ICS357G-xxT
ICS357M-xx
Tape and Reel
Tubes
ICS357M-xxT
Tape and Reel
xx represents a 2 character alphanumeric programming code assigned by the factory, which indicates the output
frequencies on all CLKs and other features. All samples are shipped with an ICS357 order form describing the
characteristics of the device.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Inc.
(ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which
would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other
extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to
change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support
devices or critical medical instruments.
QTClock is a trademark of ICS
MDS 357 B
6
Revision 032301
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose, CA, 95126 •(408) 295-9800tel• www.icst.com
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