ICS552R-01BILFT [IDT]
Low Skew Clock Driver, 552 Series, 4 True Output(s), 0 Inverted Output(s), CMOS, PDSO20, 0.150 INCH, SSOP-20;
| 型号： | ICS552R-01BILFT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew Clock Driver, 552 Series, 4 True Output(s), 0 Inverted Output(s), CMOS, PDSO20, 0.150 INCH, SSOP-20 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总6页 (文件大小：132K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS552-01B
Dual 1 to 4 High-Speed Clock Buffer
Description
Features
The ICS552-01B is a low cost, high-speed clock buffer
which includes two identical single input to four output
buffers. By combining the two buffers on one monolithic
device, the propagation delays are matched through
the device, maintaining any skew relationship present
on the inputs. It is also possible to connect the inputs
together, creating a one-to-eight buffer. See the
ICS551M for a single 1 to 4 buffer in an 8-pin SOIC. For
more than eight outputs, see the MK74CBxxx Buffalo™
series of clock drivers.
• Packaged as 20-pin (150 mil) SSOP (QSOP)
• Pb-free packaging available
• Up to 200 MHz clock input/output at 3.3 V
• Low skew of 250 ps maximum for any bank of four
• Inputs can be connected together for a 1 to 8 buffer
with 250 ps skew between any outputs
• 3.0 V to 5.5 V operating voltage
• Non-inverting
• Ideal for networking clocks
• Output Enable mode tri-states outputs
ICS also makes many PLL-based low-skew output
devices, as well as Zero Delay Buffers to synchronize
clocks. Contact ICS for all of your clocking needs.
• Full CMOS output swing with 25 mA output drive
capability at TTL levels
• Advanced, low power, sub-micron CMOS process
• Industrial temperature version available
Block Diagram
INA
QA1
QA2
QA3
QA4
QB1
QB2
QB3
QB4
S1
Control
Logic
S0
INB
MDS 552-01B E
1
Revision 012904
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS552-01B
Dual 1 to 4 High-Speed Clock Buffer
Clock Output Select Table
Pin Assignment
S1 S0
Mode
INA
DC
DC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
S0
0
0
1
1
0
1
0
1
QA1:4 and QB1:4 running
Test mode
INB
QB4
QB3
VDD
OE. All outputs in high impedance
QA1:4 only. QB1:4 stopped low
VDD
VDD
GND
QA1
QA2
QA3
QA4
VDD
GND
QB2
QB1
S1
20-pin (150 mil) SSOP (QSOP)
Pin Descriptions
Pin
Pin
Pin
Type
Pin Description
Number Name
1
2
INA
DC
CI
—
Input to buffer A. Outputs QA1:4 will be the same frequency. Internal pull-up resistor.
Do not connect.
3
DC
—
Do not connect.
4
VDD
VDD
GND
QA1
QA2
QA3
QA4
Power
Power
Power
Connect to +3.3 V or 5.0 V. Must be same as other VDDs.
Connect to +3.3 V or 5.0 V. Must be same as other VDDs.
5
6
Connect to ground.
7
Output Output 1 from buffer A.
Output Output 2 from buffer A.
Output Output 3 from buffer A.
Output Output 4 from buffer A.
8
9
10
Mode Select pin 1. Selects mode for outputs. Must be at GND for all clocks on. Internal
pull-up resistor.
11
S1
I
12
13
14
15
16
17
18
19
QB1
QB2
GND
VDD
VDD
QB3
QB4
INB
Output Output 1 from buffer B.
Output Output 2 from buffer B.
Power
Power
Power
Connect to ground.
Connect to +3.3 V or 5.0 V. Must be same as other VDDs.
Connect to +3.3 V or 5.0 V. Must be same as other VDDs.
Output Output 3 from buffer B.
Output Output 4 from buffer B.
Input to buffer B. Outputs QA1:4 will be the same frequency. Internal pull-up resistor.
CI
Mode Select pin 0. Selects mode for outputs. Must be at GND for all clocks on. Internal
pull-up resistor.
20
S0
I
KEY: CI = clock input with pull-up resistor; I = input with internal pull-up resistor
MDS 552-01B E
2
Revision 012904
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS552-01B
Dual 1 to 4 High-Speed Clock Buffer
PCB Layout Recommendations
External Components
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50Ω trace (a
commonly used trace impedance), place a 33Ω resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20Ω.
1) Each 0.01µF decoupling capacitor should be
mounted on the component side of the board as close
to the VDD pin as possible. No vias should be used
between decoupling capacitor and VDD pin. The PCB
trace to VDD pin should be kept as short as possible,
as should the PCB trace to the ground via.
Decoupling Capacitors
2) The external crystal should be mounted just next to
the device with short traces. The X1 and X2 traces
should not be routed next to each other with minimum
spaces, instead they should be separated and away
from other traces.
As with any high-performance mixed-signal IC, the
ICS552-01B must be isolated from system power
supply noise to perform optimally.
Decoupling capacitors of 0.01µF must be connected
between each VDD and GND on pins 4 and 6, and 16
and 14. Other VDDs and GNDs can be connected to
these pins or directly to their respective ground planes.
3) To minimize EMI, the 33Ω series termination resistor
(if needed) should be placed close to the clock output.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers.
MDS 552-01B E
3
Revision 012904
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS552-01B
Dual 1 to 4 High-Speed Clock Buffer
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS552-01B. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Parameter
Condition
Min.
Typ.
Max.
7
Units
V
Supply Voltage, VDD
Inputs
Referenced to GND
Referenced to GND
Referenced to GND
-0.5
-0.5
-65
VDD+0.5
VDD+0.5
150
V
Clock Outputs
V
Storage Temperature
Soldering Temperature
Junction Temperature
°C
°C
°C
Max 10 seconds
260
125
Recommended Operation Conditions
Parameter
Min.
0
Typ.
Max.
+70
Units
°C
Ambient Operating Temperature (ICS552R-01B)
Ambient Operating Temperature (ICS552R-01BI)
-40
+85
°C
DC Electrical Characteristics
Unless stated otherwise, VDD = 5 V, Ambient Temperature -40 to +85°C
Parameter
Operating Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Symbol
Conditions
Min.
Typ.
Max. Units
VDD
3.0
5.5
V
V
V
V
V
V
V
INA and INB
VDD/2+1 VDD/2
IH
V
X1 pin only
S1 and S0
S1 and S0
VDD = 5 V,
VDD/2 VDD/2-1
0.8
IL
V
2
IH
V
IL
V
2.4
OH
I
= -25 mA
OH
Output Low Voltage
Output High Voltage
Short Circuit Current
V
VDD = 5 V,
= 25 mA
0.4
V
V
OL
OH
OS
I
OL
V
CMOS level,
= -8 mA
VDD-0.4
I
OH
I
VDD = 3.3 V, each
output
50
mA
MDS 552-01B E
4
Revision 012904
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS552-01B
Dual 1 to 4 High-Speed Clock Buffer
Parameter
Symbol
Conditions
Min.
Typ.
Max. Units
Operating Supply Current
I
at 3.3 V, no load, all 135
MHz
35
mA
DD
Input Capacitance
All inputs
All inputs
4
pF
Internal Pull-up resistor
R
55
kΩ
PU
AC Electrical Characteristics
Unless stated otherwise, VDD = 5 V, Ambient Temperature -40 to +85° C
Parameter
Symbol
Conditions
Min.
Typ.
Max. Units
Input Frequency
F
0
200
200
180
135
1.5
MHz
MHz
MHz
MHz
ns
IN
Output Frequency
F
OUT
3.3 V, 10 pF load, note 3.
3.3 V, 15 pF load, note 3.
5 V, 15 pF load, note 3.
0.8 to 2.0 V
Output Rise Time
Output Fall Time
Propagation Delay
t
OR
t
2.0 to 0.8 V
1.5
ns
OF
at 3.3 V
4
3
ns
at 5 V
ns
Output-to-Output Skew
within bank of four
Rising edges at VDD/2
250
250
ps
Output-to-Output Skew
between banks
Note 1
ps
Notes:
1. When INA is connected to INB, all eight outputs are within 250 ps skew.
2. Duty cycle on outputs will match incoming clock duty cycle. Consult ICS for tight duty cycle clock
generators.
3. With external series resistor of 33Ω positioned close to each output pin.
Thermal Characteristics
Parameter
Symbol
Conditions
Min.
Typ. Max. Units
Thermal Resistance Junction to
Ambient
θ
θ
θ
Still air
135
93
°C/W
°C/W
°C/W
°C/W
JA
JA
JA
JC
1 m/s air flow
3 m/s air flow
78
Thermal Resistance Junction to Case
θ
60
MDS 552-01B E
5
Revision 012904
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS552-01B
Dual 1 to 4 High-Speed Clock Buffer
Package Outline and Package Dimensions (20-pin SSOP, 150 Mil. Wide Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters
Inches
20
Symbol
Min
Max
1.75
0.25
1.50
0.30
0.25
8.75
6.20
4.00
Min
Max
A
A1
A2
b
1.35
0.10
--
0.20
0.18
8.55
5.80
3.80
0.053
0.004
--
0.008
0.007
0.337
0.228
0.150
0.069
0.010
0.059
0.012
0.010
0.344
0.244
0.157
E1
E
INDEX
AREA
c
D
E
E1
e
1
2
.635 Basic
.025 Basic
D
L
0.40
0°
1.27
8°
0.016
0°
0.050
8°
α
aaa
--
0.10
--
0.004
A
A2
A1
c
- C -
e
SEATING
PLANE
b
L
aaa C
Ordering Information
Part / Order Number
Marking
Shipping
packaging
Package
Temperature
ICS552R-01B
ICS552R-01BT
ICS552R-01BLF
ICS552R-01BLFT
ICS552R-01BI
ICS552-01B
ICS552-01B
Tubes
20-pin SSOP
20-pin SSOP
20-pin SSOP
20-pin SSOP
20-pin SSOP
20-pin SSOP
0 to +70°C
0 to +70°C
0 to +70°C
0 to +70°C
-40 to +85°C
-40 to +85°C
Tape and Reel
Tubes
ICS552-01BLF
ICS552-01BLF
ICS552-01BI
ICS552-01BI
Tape and Reel
Tubes
ICS552R-01BIT
Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments.
MDS 552-01B E
6
Revision 012904
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
相关型号：
ICS552R-01BLFT
Low Skew Clock Driver, 552 Series, 4 True Output(s), 0 Inverted Output(s), CMOS, PDSO20, 0.150 INCH, LEAD FREE, SSOP-20
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ICS552R-01BT
Low Skew Clock Driver, 552 Series, 4 True Output(s), 0 Inverted Output(s), CMOS, PDSO20, 0.150 INCH, SSOP-20
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