ICS650GI-41T [IDT]
Processor Specific Clock Generator, 50MHz, CMOS, PDSO16, 0.173 INCH, TSSOP-16;
| 型号： | ICS650GI-41T |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Processor Specific Clock Generator, 50MHz, CMOS, PDSO16, 0.173 INCH, TSSOP-16 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总11页 (文件大小：223K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
SPREAD SPECTRUM CLOCK SYNTHESIZER
ICS650-41
Description
Features
The ICS650-41 is a spread spectrum clock synthesizer
intended for video projector applications. It generates an
EMI optimized 50 MHz clock signal (EMI peak reduction of
7 to 14 dB on 3rd through 19th harmonics) through the use
of Spread Spectrum techniques from a 25 MHz crystal or
clock input. For the 50 MHz output, the modulation rate is
50 kHz.
• Packaged in 16-pin TSSOP (173 mil)
• Supply voltages: VDD = 3.3 V, VDDO = 2.5 V
• Peak-to-peak jitter: 125 ps typ
• Output duty cycle 45/55% (worst case)
• Guarantees +85°C operational condition
• 25 MHz crystal or reference clock input
• Zero (0) ppm frequency error on all output clocks
In addition to the EMI optimized clock signal, the device
generates a 48 MHz clock for USB.
• Advanced, low-power CMOS process
• Industrial temperature range
Block Diagram
VDD
VDDO
25 MHz crystal
or clock input
3
X1/CLKIN
PLL1 with
Spread
Spectrum
Crystal
OSC
50M
X2
External capacitors are
required with a crystal
input.
FS3:0
Control
PLL2
48M
Logic
SS_EN
2
GND
PDTS
IDT™ / ICS™ SPREAD SPECTRUM CLOCK SYNTHESIZER
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SPREAD SPECTRUM CLOCK SYNTHESIZER
CLOCK SYNTHESIZER
Pin Assignment
Spread Spectrum and Output
Configuration Table
X1/CLKIN
FS0
X2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
FS3 FS2 FS1 FS0 Spread Type
SS Out
0.25
VDD
PDTS
FS2
VDD
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Center
Center
Center
Center
Center
Center
Center
Center
Down
Down
Down
Down
Down
Down
Down
Down
FS1
0.50
0.75
1.00
1.25
1.50
1.75
2.00
-0.5
SS_EN
VDD
GND
FS3
GND
VDDO
50M
48M
16-pin (173 mil) TSSOP
-0.75
-1.0
-1.25
-1.5
-1.75
-2.0
-2.25
IDT™ / ICS™ SPREAD SPECTRUM CLOCK SYNTHESIZER
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Pin Descriptions
Pin
Number
Pin
Type
Pin Name
Pin Description
1
X1/CLKIN
Input
Crystal input. Connect this pin to a 25 MHz crystal or external input
clock.
2
3
FS0
FS1
Input
Input
Input
Select pin 0. Internal pull-up resistor. See table on page 2.
Select pin 1. Internal pull-up resistor. See table on page 2.
Spread spectrum enable pin. Internal pull-up resistor. Enabled = high.
4
SS_EN
VDD
GND
FS3
5
Power Connect to +3.3 V.
Power Connect to ground.
6
7
Input
Select pin 3. Internal pull-up resistor. See table on page 2.
8
48M
Output Fixed 48 MHz output. Weak internal pull-down when tri-state.
Output Spread Spectrum output. Weak internal pull-down when tri-stated.
Power Connect to +2.5 V.
9
50M
10
11
12
13
14
VDDO
GND
VDD
FS2
Power Connect to ground.
Power Connect to +3.3 V.
Input
Input
Select pin 2. Internal pull-up resistor. See table on page 2.
PDTS
Powers down entire chip. Tri-states CLK outputs when low. Internal
pull-up.
15
16
VDD
X2
Power Connect to +3.3 V.
Output Crystal Output. Connect this pin to a 25 MHz crystal. Do not connect if
clock input is used.
External Components
small capacitors from X1 to ground and from X2 to ground.
These capacitors are used to adjust the stray capacitance of
Decoupling Capacitor
As with any high-performance mixed-signal IC, the
ICS650-41 must be isolated from system power supply
noise to perform optimally.
the board to match the nominally required crystal load
capacitance. Because load capacitance can only be
increased in this trimming process, it is important to keep
stray capacitance to a minimum by using very short PCB
traces (and no vias) between the crystal and device. Crystal
capacitors must be connected from each of the pins X1 and
X2 to ground.
A decoupling capacitor of 0.01µF must be connected
between each VDD and the PCB ground plane.
Series Termination Resistor
The value (in pF) of these crystal caps should equal (C -6
L
Clock output traces over one inch should use series
termination. To series terminate a 50Ω trace (a commonly
used trace impedance), place a 33Ω resistor in series with
the clock line, as close to the clock output pin as possible.
The nominal impedance of the clock output is 20Ω.
pF)*2. In this equation, C = crystal load capacitance in pF.
L
Example: For a crystal with a 16 pF load capacitance, each
crystal capacitor would be 20 pF [(16-6) x 2] = 20.
PCB Layout Recommendations
Crystal Load Capacitors
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
The device crystal connections should include pads for
IDT™ / ICS™ SPREAD SPECTRUM CLOCK SYNTHESIZER
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1) The 0.01µF decoupling capacitors should be mounted on
the component side of the board as close to the VDD pin as
possible. No vias should be used between the decoupling
capacitors and VDD pins. The PCB trace to VDD pins
should be kept as short as possible, as should the PCB
trace to the ground via.
3) To minimize EMI, the 33Ω series termination resistor (if
needed) should be placed close to the clock output.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers. Other signal traces should be routed away from the
ICS650-41. This includes signal traces just underneath the
device, or on layers adjacent to the ground plane layer used
by the device.
2) The external crystal should be mounted just next to the
device with short traces. The X1 and X2 traces should not
be routed next to each other with minimum spaces, instead
they should be separated and away from other traces.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS650-41. These ratings, which are
standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at
these or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Item
Rating
Supply Voltage, VDD
All Inputs and Outputs
7 V
-0.5 V to VDD+0.5 V
0 to +85°C
-65 to +150°C
125°C
Ambient Operating Temperature
Storage Temperature
Junction Temperature
Soldering Temperature (max. of 10 seconds)
260°C
Recommended Operation Conditions
Parameter
Min.
Typ.
–
Max.
+85
Units
°C
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
Power Supply Voltage (VDDO)
Power Supply Ramp Time, Figure 4
0
+3.135
+2.375
+3.3
+2.5
+3.465
+2.625
4
V
V
ms
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DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V ±±%, VDDO = 2.± V ±±% , Ambient Temperature 0 to +85°C
Parameter
Symbol
Conditions
Min.
Typ.
Max. Units
no load
27
mA
IDD
PDTS = 0, no load
no load
40
4
uA
mA
uA
V
Operating Supply Current
IDDO
PDTS = 0, no load
FS3:0, PDTS, SS_EN
FS3:0, PDTS, SS_EN
X1/CLKIN
1
Input High Voltage
Input Low Voltage
Input High Voltage
V
2
IH
V
0.8
V
V
IL
V
0.7 x
VDD
IH
Input Low Voltage
V
X1/CLKIN
0.3 x
VDD
V
IL
Output High Voltage
Output Low Voltage
Short Circuit Current
V
I
I
= -4 mA
= 4 mA
1.8
V
V
OH
OH
V
0.6
OL
OS
OL
I
50
20
mA
Ω
Nominal Output
Impedance
Z
O
Internal Pull-up Resistor
Input Leakage Current
R
FS3:0, PDTS, SS_EN
360
1
kΩ
PU
I
FS3:0, PDTS, SS_EN,
VIN=VDD
uA
I
Internal Pull-down
Resistor
R
CLK outputs
900
4
kΩ
PD
Input Capacitance
C
Inputs
pF
IN
IDT™ / ICS™ SPREAD SPECTRUM CLOCK SYNTHESIZER
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CLOCK SYNTHESIZER
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V ±±%, VDDO = 2.± V ±±%, Ambient Temperature 0 to +85° C
Parameter
Symbol
Conditions
Min.
Typ.
25
Max. Units
MHz
Input Frequency
F
Crystal or clock input
IN
Spread Spectrum Modulation
Frequency
50
kHz
Duty Cycle
t /t
at VDD/2, Note 1 and
Figures 1 and 2
45
50
1.5
1.5
55
%
ns
ns
2 1
Output Fall Time
Output Rise Time
t
t
80% to 20%, Note 1
and Figures 1 & 3
3
4
20% to 80%, Note 1
and Figures 1 & 3
One Sigma Clock Period Jitter
Absolute Jitter, Peak-to-Peak
Note 1
30
ps
ps
t
Deviation from mean,
SS_EN=0, Note1 &
Figures 1 and 6
125
ja
Output Enable Time
Output Disable Time
t
PDTS high to PLL
locked to within 1% of
final value, Figure 5
2.5
5
ms
EN
t
PDTS low to tri-state,
Figure 5
20
6
ns
DIS
t
PLL lock-time from
power-up to 1% of final
value, Figure 4
10
ms
P
Power-up Time
Note 1: Measured with 15 pF load.
IDT™ / ICS™ SPREAD SPECTRUM CLOCK SYNTHESIZER
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Thermal Characteristics
Parameter
Symbol
Conditions
Min.
Typ. Max. Units
Thermal Resistance Junction to
Ambient
θ
θ
θ
Still air
78
70
68
37
°C/W
°C/W
°C/W
°C/W
JA
JA
JA
JC
1 m/s air flow
3 m/s air flow
Thermal Resistance Junction to Case
θ
Marking Diagram
16
9
650GI41L
######
YYWW
1
8
Notes:
1. ###### is the lot number.
2. YYWW is the last two digits of the year and the week number that the part was assembled.
IDT™ / ICS™ SPREAD SPECTRUM CLOCK SYNTHESIZER
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Timing Diagrams
t1
VDDs
Outputs
t2
0.01µF
CLOAD
DUT
V D D O
5 0 % of V D D O
0 V
C lo ck
GND
Figure 1: Test and Measurement Setup
Figure 2: Duty Cycle Definitions
Power Up
Time
VCO Ramp
Time
PLL Locked
t4
VDD
t3
VDDO
80% of VDDO
0V
VDD
20% of VDDO
0V
Clock
Output
0V
0 ms
4 ms
10 ms
Figure 3: Rise and Fall Time Definitions
Figure 4: Power Up and PLL Lock Timing
PDTS
1.25 V
1%
1.25 V
t DIS
t EN
Mean value
VOH
0 V
CLK
Outputs
Absolute jitter
tJA
(p - p)
Figure 6: Short Term Jitter Definition
Figure ±: PDTS to Stable Clock Output Timing
IDT™ / ICS™ SPREAD SPECTRUM CLOCK SYNTHESIZER
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CLOCK SYNTHESIZER
Package Outline and Package Dimensions (16-pin TSSOP, 173 Mil. Narrow Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters
Min Max
Inches
Max
16
Symbol
Min
--
A
A1
A2
b
--
1.20
0.15
1.05
0.30
0.20
5.1
0.047
0.006
0.041
0.012
0.05
0.80
0.19
0.09
4.90
0.002
0.032
0.007
E1
E
INDEX
AREA
C
D
E
0.0035 0.008
0.193 0.201
0.252 BASIC
0.169 0.177
0.0256 Basic
6.40 BASIC
4.30 4.50
0.65 Basic
1
2
E1
e
L
D
0.45
0°
0.75
8°
0.018
0°
0.030
8°
α
aaa
--
0.10
--
0.004
A
A2
A1
c
- C -
e
SEATING
PLANE
b
L
aaa C
Ordering Information
Part / Order Number
ICS650GI-41LF
Marking
650GI41L
650GI41L
Shipping Packaging
Tubes
Package
16-pin TSSOP
16-pin TSSOP
Temperature
0 to +85° C
ICS650GI-41LFT
Tape and Reel
0 to +85° C
Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no
responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No
other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications
such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS
does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
IDT™ / ICS™ SPREAD SPECTRUM CLOCK SYNTHESIZER
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Revision History
Rev. Originator
Date
Description of Change
B
P.Griffith
10/07/04 Changed the input frequency from 14.31818 to 25 MHz; changed Short Circuit Current
from 70 to 50; added separate Pull-up resistor spec for SS_EN; added “I” to part
ordering number
C
P. Griffith
11/15/04 Changed AC and DC parameters to reflect measured char values: IDD, IDDO, VIH, VIL,
RPU, II, RPD, t1,.t2, t3, t4, tja, tEN, tDIS, tP. Added Figures for key parameters.
D
E
P. Griffith
P. Griffith
12/06/04 Changed jitter spec to +/-150 ps and duty cycle to 45% min, 55% max.
1/17/05 Renamed pin 1 to X1/CLKin on page2, improved jitter spec to +/-125 ps on front page and
in electrical tables, changed rise and fall time to 1.5 ns typical to reflect balanced drive,
changed typical ID spec to 4 ma, updated graphs on page 8 to reflect separate VDDO and
correct bypass capacitor value, updated marking diagram and ordering table to reflect
Pb-free device.
IDT™ / ICS™ SPREAD SPECTRUM CLOCK SYNTHESIZER
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ICS650-41
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ICS650-41
SPREAD SPECTRUM CLOCK SYNTHESIZER
CLOCK SYNTHESIZER
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www.IDT.com
For Sales
800-345-7015
408-284-8200
Fax: 408-284-2775
For Tech Support
<product line email>
<product line phone>
Corporate Headquarters
Integrated Device Technology, Inc.
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San Jose, CA 95138
Asia Pacific and Japan
Integrated Device Technology
Singapore (1997) Pte. Ltd.
Reg. No. 199707558G
435 Orchard Road
Europe
IDT Europe, Limited
Prime House
Barnett Wood Lane
Leatherhead, Surrey
United Kingdom KT22 7DE
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United States
800 345 7015
#20-03 Wisma Atria
+408 284 8200 (outside U.S.)
Singapore 238877
+65 6 887 5505
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
Printed in USA
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