ICS660GILFTR [IDT]
Video Clock Generator, 125MHz, PDSO16, 4.40 MM, 0.65 MM PITCH, LEAD FREE, MO-153, TSSOP-16;
| 型号： | ICS660GILFTR |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Video Clock Generator, 125MHz, PDSO16, 4.40 MM, 0.65 MM PITCH, LEAD FREE, MO-153, TSSOP-16 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总6页 (文件大小：127K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS660
Digital Video Clock Source
Description
Features
The ICS660 provides clock generation and conversion
for clock rates commonly needed in digital video
equipment, including rates for MPEG, NTSC, PAL, and
HDTV. The ICS660 uses the latest PLL technology to
provide excellent phase noise and long term jitter
performance for superior synchronization and S/N
ratio.
• Packaged in 16-pin TSSOP
• Available in Pb-free packaging
• Clock or crystal input
• Low phase noise
• Low jitter
• Exact (0 ppm) multiplication ratios
• Power-down control
• Reference clock output available
For audio sampling clocks generated from 27 MHz, use
the ICS661.
Please contact ICS if you have a requirement for an
input and output frequency not included here - we can
rapidly modify this product to meet special
requirements.
Block Diagram
VDD (P2)
VDD (P3)
VDDO
VDDR
X2
REF
Crystal
Oscillator
X1/REFIN
SELIN
PLL Clock
CLK
Synthesis
S3:0
4
GND (P13)
GND (P6) GND (P5)
MDS 660 E
1
Revision 040104
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS660
Digital Video Clock Source
Pin Assignment
Output Clock Selection Table
Input
Frequency
Output
Frequency
(MHz)
S3
S2
S1
S0
X1/REFIN
VDD
VDD
S0
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
X2
(MHz)
REF
VDDR
GND
SELIN
VDDO
S1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
13.5
13.5
74.25
74.175824
74.25
27
27
74.175824
Input Freq
74.175824
74.25
GND
GND
S3
Pass thru
74.25
74.175824
Power down
S2
CLK
16.9344
125
27
106.25
27
14.3181818
106.25
27.027
27
16-pin 4.40 mil body, 0.65 mm pitch TSSOP
125
27
27.027
14.3181818
17.73447205
27
1
27
1 - 0.16 ppm compared to PAL specification
Pin Descriptions
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
2
X1/REFIN
VDD
VDD
S0
Input
Connect this pin to a crystal or clock input
Power Power supply for crystal oscillator.
Power Power supply for PLL.
3
4
Input
Output frequency selection. Determines output frequency per table above. On chip pull-up.
5
GND
GND
S3
Power Ground for output stage.
Power Ground for PLL.
6
7
Input
Input
Output frequency selection. Determines output frequency per table above. On chip pull-up.
Output frequency selection. Determines output frequency per table above. On chip pull-up.
8
S2
9
CLK
S1
Output Clock output.
10
11
12
13
14
15
16
Input
Output frequency selection. Determines output frequency per table above. On chip pull-up.
VDDO
SEL
GND
VDDR
REF
X2
Power Power supply for output stage.
Input
Low for clock input, high for crystal. On chip pull-up.
Power Connect to ground.
Power Power supply for reference output. Ground to turn off REF.
Output Reference clock output.
Input
Connect this pin to a crystal. Leave open if using a clock input.
MDS 660 E
2
Revision 040104
Integrated Circuit Systems, Inc.● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS660
Digital Video Clock Source
Application Information
and from X2 to ground. These capacitors are used to
adjust the stray capacitance of the board to match the
nominally required crystal load capacitance. To reduce
possible noise pickup, use very short PCB traces (and
no vias) been the crystal and device.
Series Termination Resistor
Clock output traces should use series termination. To
series terminate a 50Ω trace (a commonly used trace
impedance), place a 33Ω resistor in series with the
clock line, as close to the clock output pin as possible.
The nominal impedance of the clock output is 20Ω.
The value of the load capacitors can be roughly
determined by the formula C = 2(C - 6) where C is the
L
Decoupling Capacitors
load capacitor connected to X1 and X2, and C is the
specified value of the load capacitance for the crystal.
A typical crystal C is 18 pF, so C = 2(18 - 6) = 24 pF.
Because these capacitors adjust the stray capacitance
of the PCB, check the output frequency using your final
layout to see if the value of C should be changed.
L
As with any high-performance mixed-signal IC, the
ICS660 must be isolated from system power supply
noise to perform optimally.
L
Decoupling capacitors of 0.01µF must be connected
between each VDD and the PCB ground plane. To
further guard against interfering system supply noise,
the ICS660 should use one common connection to the
PCB power plane as shown in the diagram on the next
page. The ferrite bead and bulk capacitor help reduce
lower frequency noise in the supply that can lead to
output clock phase modulation.
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1) Each 0.01µF decoupling capacitor should be
mounted on the component side of the board as close
to the VDD pin as possible. No vias should be used
between decoupling capacitor and VDD pin. The PCB
trace to VDD pin should be kept as short as possible,
as should the PCB trace to the ground via. Distance of
the ferrite bead and bulk decoupling from the device is
less critical.
Recommended Power Supply Connection for
Optimal Device Performance
VDD Pin
Ferrite
Bead
Connection to 3.3V
VDD Pin
Power Plane
2) The external crystal should be mounted next to the
device with short traces. The X1 and X2 traces should
not be routed next to each other with minimum spaces,
instead they should be separated and away from other
traces.
Bulk Decoupling Capacitor
(such as 1 F Tantalum)
VDD Pin
3) To minimize EMI, and obtain the best signal integrity,
the 33Ω series termination resistor should be placed
close to the clock output.
0.01 F Decoupling Capacitors
All power supply pins must be connected to the same
voltage, except VDDR and VDDO, which may be
connected to a lower voltage in order to change the
output level. If the reference output is not used, ground
VDDR.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers (the ferrite bead and bulk decoupling
capacitor can be mounted on the back). Other signal
traces should be routed away from the ICS660. This
includes signal traces just underneath the device, or on
layers adjacent to the ground plane layer used by the
device.
Crystal Load Capacitors
If a crystal is used, the device crystal connections
should include pads for capacitors from X1 to ground
MDS 660 E
3
Revision 040104
Integrated Circuit Systems, Inc.● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS660
Digital Video Clock Source
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS660. These ratings, which
are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the
device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Rating
Supply Voltage, VDD
All Inputs and Outputs
5.5 V
-0.5 V to VDD+0.5 V
-40 to +85° C
-65 to +150° C
125° C
Ambient Operating Temperature
Storage Temperature
Junction Temperature
Soldering Temperature
260° C
Recommended Operation Conditions
Parameter
Min.
Typ.
Max.
+85
Units
°C
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
-40
+3.0
+3.6
V
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 10%, Ambient Temperature -40 to +85° C
Parameter
Symbol
VDD
Conditions
Min.
3.0
Typ.
Max. Units
3.6
V
V
Operating Voltage
VDDO
VDDR
IDD
2.5
VDD
VDD
2.5
V
Supply Current
No Load
25
75
mA
µA
V
Standby Supply Current
Input High Voltage
IDDPD
V
2
IH
Input Low Voltage
V
0.8
0.4
V
IL
Output High Voltage
Output High Voltage
Output Low Voltage
Short Circuit Current
Nominal Output Impedance
Input Capacitance
V
V
I
I
I
= -4 mA
= -20 mA
= 20 mA
VDD-0.4
2.4
V
OH
OH
OH
OH
OL
V
V
V
OL
OS
I
Each output
65
20
mA
Ω
Z
OUT
C
input pins
7
pF
kΩ
IN
Internal Pull-up Resistor
R
120
PU
MDS 660 E
4
Revision 040104
Integrated Circuit Systems, Inc.● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS660
Digital Video Clock Source
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 10%, Ambient Temperature -40 to +85° C
Parameter
Crystal Frequency
Symbol
Conditions
Min.
Typ.
Max. Units
28
1.5
1.5
60
MHz
ns
Output Clock Rise Time
Output Clock Fall Time
Output Duty Cycle
t
20% to 80%, 15 pF load
80% to 20%, 15 pF load
at VDD/2, 15 pF load
OR
t
ns
OF
OD
t
40
49 to 51
%
inputs out of PD state to
clocks stable
Power up time
t
t
10
1
ms
PU
PD
inputs in PD state to
clocks off
Power down time
µs
Jitter, short term
Jitter, short term
Reference clock off
Reference clock on
100
125
ps p-p
ps p-p
Reference clock off; 10
us delay
Jitter, long term
300
300
ps p-p
ps p-p
dBc
Reference clock on; 10
us delay
Jitter, long term
Reference clock off; 10
kHz offset
Single sideband phase noise
Single sideband phase noise
-110
Reference clock on; 10
kHz offset
-110
0
dBc
Actual mean frequency error
versus target
Note 1
ppm
Note 1: Selection 1111 is 0.16 ppm lower than the PAL specified frequency
Thermal Characteristics
Parameter
Symbol
Conditions
Min.
Typ. Max. Units
Thermal Resistance Junction to
Ambient
θ
θ
θ
θ
Still air
78
70
68
37
°C/W
°C/W
°C/W
°C/W
JA
JA
JA
JC
1 m/s air flow
3 m/s air flow
Thermal Resistance Junction to Case
MDS 660 E
5
Revision 040104
Integrated Circuit Systems, Inc.● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS660
Digital Video Clock Source
Package Outline and Package Dimensions (16-pin TSSOP, 4.40 mm Body, 0.65 mm Pitch)
Package dimensions are kept current with JEDEC Publication No. 95, MO-153
Millimeters
Min Max
Inches
Max
16
Symbol
Min
--
A
A1
A2
b
--
1.20
0.15
1.05
0.30
0.20
5.1
0.047
0.006
0.041
0.012
0.05
0.80
0.19
0.09
4.90
0.002
0.032
0.007
E1
E
INDEX
AREA
C
D
E
0.0035 0.008
0.193 0.201
0.252 BASIC
0.169 0.177
0.0256 Basic
6.40 BASIC
4.30 4.50
0.65 Basic
1
2
E1
e
L
D
0.45
0°
0.75
8°
0.018
0°
0.030
8°
α
aaa
--
0.10
--
0.004
A
2
A
A
1
c
- C -
e
SEATING
PLANE
b
L
aaa
C
Ordering Information
Shipping
packaging
Part / Order Number
Marking
Package
Temperature
ICS660GI
ICS660GITR
ICS660GILF
ICS660GILFTR
ICS660GI
ICS660GI
660GILF
660GILF
Tubes
16-pin TSSOP
16-pin TSSOP
16-pin TSSOP
16-pin TSSOP
-40 to +85° C
-40 to +85° C
-40 to +85° C
-40 to +85° C
Tape and Reel
Tubes
Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments.
MDS 660 E
6
Revision 040104
Integrated Circuit Systems, Inc.● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
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