ICS664G-03LFT [IDT]
Video Clock Generator, 148.5MHz, PDSO16, 4.40 MM, 0.65 MM PITCH, LEAD FREE, MO-153, TSSOP-16;
| 型号： | ICS664G-03LFT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Video Clock Generator, 148.5MHz, PDSO16, 4.40 MM, 0.65 MM PITCH, LEAD FREE, MO-153, TSSOP-16 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总7页 (文件大小：136K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
DIGITAL VIDEO CLOCK SOURCE
ICS664-03
Description
Features
The ICS664-03 provides clock generation and conversion
for clock rates commonly needed in HDTV digital video
equipment. The ICS664-03 uses the latest PLL technology
to provide excellent phase noise and long term jitter
performance for superior synchronization and S/N ratio.
• Packaged in 16-pin TSSOP
• Pb (lead) free package, RoHS compliant
• Clock or crystal input provides flexibility
• Low phase noise supports enhanced SNR
• Lowest jitter in class at 100 ps
• Exact (0 ppm) multiplication ratios
• Power-down mode lowers power consumption
• Improved phase noise over ICS660
The ICS664-03 is suitable for Digital Video STB and DTV
applications. For Transmitter application use ICS664-01 or
ICS664-02.
For audio sampling clocks generated from 27 MHz, use the
ICS661.
• Provides High definition Video clocks for 720p, 1080i and
1080p YUV standards
Please contact IDT if you have a requirement for an input
and output frequency not included in this document. IDT
can rapidly modify this product to meet special
requirements.
Block Diagram
VDD (P2)
VDD (P3)
VDDO
VDD (P14)
X2
Crystal
Oscillator
X1/REFIN
SELIN
PLL Clock
Synthesis
CLK
S3:0
4
GND (P6)
GND (P5)
GND (P13)
IDT™ / ICS™ DIGITAL VIDEO CLOCK SOURCE
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CLOCK SYNTHESIZER
Pin Assignment
Output Clock Selection Table
Input
Frequency
(MHz)
Output
Frequency
(MHz)
S3
S2
S1
S0
X1/REFIN
VDD
VDD
S0
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
X2
N/C
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Power down
27 (passthrough)
74.25
VDD
GND
SELIN
VDDO
S1
27
27
27
74.175824
74.25
GND
GND
S3
13.5
13.5
27
74.175824
148.5000
148.351648
54
27
S2
74.25
74.175824
74.25
74.175824
54
CLK
54
27
16-pin TSSOP
27
74.25
54
74.175824
13.5
54
27
13.5
Pin Descriptions
Pin
Number
Pin
Name
Pin
Type
Pin Description
Connect this pin to a crystal or clock input
1
2
X1/REFIN
VDD
VDD
S0
Input
Power Power supply for crystal oscillator.
Power Power supply for PLL.
3
4
Input
Output frequency selection. Determines output frequency per table above. Internal pull-up.
5
GND
GND
S3
Power Ground for PLL.
6
Power Ground for PLL for Crystal Osillator.
7
Input
Input
Output frequency selection. Determines output frequency per table above. Internal pull-up.
Output frequency selection. Determines output frequency per table above. Internal pull-up.
8
S2
9
CLK
S1
Output Clock output.
10
11
12
13
14
15
16
Input
Output frequency selection. Determines output frequency per table above. Internal pull-up.
VDDO
SEL
GND
VDD
NC
Power Power supply for output stage.
Input
Low for clock input, high for crystal. Internal pull-up.
Power Ground for Output.
Power Power supply.
—
No connect. Do not connect to anything.
Connect this pin to a crystal. Leave open if using a clock input.
X2
Input
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Application Information
Series Termination Resistor
Crystal Load Capacitors
Clock output traces should use series termination. To series
terminate a 50Ωtrace (a commonly used trace impedance),
place a 33Ωresistor in series with the clock line, as close to
the clock output pin as possible. The nominal impedance of
the clock output is 20Ω.
If a crystal is used, the device crystal connections should
include pads for capacitors from X1 to ground and from X2
to ground. These capacitors are used to adjust the stray
capacitance of the board to match the nominally required
crystal load capacitance. To reduce possible noise pickup,
use very short PCB traces (and no vias) been the crystal
and device.
Decoupling Capacitors
As with any high-performance mixed-signal IC, the
ICS664-03 must be isolated from system power supply
noise to perform optimally.
The value of the load capacitors can be roughly determined
by the formula C = 2(C - 6) where C is the load capacitor
L
connected to X1 and X2, and C is the specified value of the
L
load capacitance for the crystal. A typical crystal C is 18 pF,
L
Decoupling capacitors of 0.01µF must be connected
between each VDD and the PCB ground plane. To further
guard against interfering system supply noise, the
ICS664-03 should use one common connection to the PCB
power plane as shown in the diagram on the next page. The
ferrite bead and bulk capacitor help reduce lower frequency
noise in the supply that can lead to output clock phase
modulation.
so C = 2(18 - 6) = 24 pF. Because these capacitors adjust
the stray capacitance of the PCB, check the output
frequency using your final layout to see if the value of C
should be changed.
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
Recommended Power Supply Connection for
Optimal Device Performance
1) Each 0.01µF decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible. No vias should be used between decoupling
capacitor and VDD pin. The PCB trace to VDD pin should
be kept as short as possible, as should the PCB trace to the
ground via. Distance of the ferrite bead and bulk decoupling
from the device is less critical.
VDD Pin
Ferrite
Bead
Connection to 3.3V
VDD Pin
Power Plane
Bulk Decoupling Capacitor
(such as 1 F Tantalum)
VDD Pin
2) The external crystal should be mounted next to the device
with short traces. The X1 and X2 traces should not be
routed next to each other with minimum spaces, instead
they should be separated and away from other traces.
0.01 F Decoupling Capacitors
3) To minimize EMI and obtain the best signal integrity, the
33Ω series termination resistor should be placed close to
the clock output.
All power supply pins must be connected to the same
voltage, except VDDO, which may be connected to a lower
voltage in order to change the output level.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers (the ferrite bead and bulk decoupling capacitor can be
mounted on the back). Other signal traces should be routed
away from the ICS664-03. This includes signal traces just
underneath the device, or on layers adjacent to the ground
plane layer used by the device.
To achieve the absolute minimum jitter, power the part with
a dedicated LDO regulator, which will provide high isolation
from power supply noise. Many companies produce very
small, inexpensive regulators; an example is the National
Semiconductor LP2985.
IDT™ / ICS™ DIGITAL VIDEO CLOCK SOURCE
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CLOCK SYNTHESIZER
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS664-03. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these
or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Item
Rating
Supply Voltage, VDD
All Inputs and Outputs
5.5 V
-0.5 V to VDD+0.5 V
0 to +70° C
-65 to +150° C
125°C
Ambient Operating Temperature
Storage Temperature
Junction Temperature
Soldering Temperature
260°C
Recommended Operation Conditions
Parameter
Min.
Typ.
Max.
+70
Units
° C
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
0
+3.0
+3.6
V
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 10%, Ambient Temperature 0 to +70° C
Parameter
Symbol
VDD
Conditions
Min.
3.0
Typ.
Max. Units
3.6
V
V
Operating Voltage
VDDO
IDD
2.5
VDD
Supply Current
No Load
35
mA
V
Input High Voltage
Input Low Voltage
V
2
IH
V
0.8
0.4
V
IL
Output High Voltage
Output High Voltage
Output Low Voltage
Short Circuit Current
Nominal Output Impedance
Input Capacitance
V
V
I
I
I
= -4 mA
= -20 mA
= 20 mA
VDD-0.4
2.4
V
OH
OH
OH
OH
OL
V
V
V
OL
I
Each output
65
20
mA
Ω
OS
Z
OUT
C
Input pins
7
pF
kΩ
IN
Internal Pull-up Resistor
R
120
PU
IDT™ / ICS™ DIGITAL VIDEO CLOCK SOURCE
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AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 10%, Ambient Temperature 0 to +70° C
Parameter
Crystal Frequency
Symbol
Conditions
Min.
Typ.
Max. Units
28
1.5
1.5
60
MHz
ns
Output Clock Rise Time
Output Clock Fall Time
Output Duty Cycle
t
20% to 80%, 15 pF load
80% to 20%, 15 pF load
at VDD/2, 15 pF load
OR
t
ns
OF
t
40
49 to 51
1
%
OD
Valid power on to valid
output
Power-up Time
t
t
ms
µs
PU
PD
Power off to clock
disable
Power-down Time
10
Jitter, short term
Jitter, long term
100
200
ps p-p
ps p-p
10 µs delay
Single Sideband Phase
Noise
10 kHz offset
-120
0
dBc
Actual Mean Frequency
Error versus Target
ppm
Thermal Characteristics
Parameter
Symbol
Conditions
Min.
Typ. Max. Units
Thermal Resistance Junction to
Ambient
θ
θ
θ
θ
Still air
78
70
68
37
° C/W
° C/W
° C/W
° C/W
JA
JA
JA
JC
1 m/s air flow
3 m/s air flow
Thermal Resistance Junction to Case
IDT™ / ICS™ DIGITAL VIDEO CLOCK SOURCE
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CLOCK SYNTHESIZER
Package Outline and Package Dimensions (16-pin TSSOP, 4.40 mm Body, 0.65 mm Pitch)
Package dimensions are kept current with JEDEC Publication No. 95, MO-153
Millimeters
Min Max
Inches
Max
16
Symbol
Min
--
A
A1
A2
b
--
1.20
0.15
1.05
0.30
0.20
5.1
0.047
0.006
0.041
0.012
0.05
0.80
0.19
0.09
4.90
0.002
0.032
0.007
E1
E
INDEX
AREA
C
D
E
0.0035 0.008
0.193 0.201
0.252 BASIC
0.169 0.177
0.0256 Basic
6.40 BASIC
4.30 4.50
0.65 Basic
1
2
E1
e
L
D
0.45
0.75
0.018
0.030
α
0°
8°
0°
8°
aaa
--
0.10
--
0.004
A
2
A
A
1
c
- C -
e
SEATING
PLANE
b
L
aaa
C
Ordering Information
Part / Order Number
Marking
664G03LF
664G03LF
Shipping Packaging
Tubes
Package
16-pin TSSOP
16-pin TSSOP
Temperature
0 to +70° C
0 to +70° C
664G-03LF
664G-03LFT
Tape and Reel
“LF” denotes Pb (lead) free package.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes
no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No
other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications
such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT
does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT™ / ICS™ DIGITAL VIDEO CLOCK SOURCE
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DIGITAL VIDEO CLOCK SOURCE
CLOCK SYNTHESIZER
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
800-345-7015
408-284-8200
Fax: 408-284-2775
For Tech Support
www.idt.com/go/clockhelp
Corporate Headquarters
Integrated Device Technology, Inc.
www.idt.com
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
Printed in USA
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