ICS673-01MLF [IDT]
PLL Based Clock Driver, 2 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 0.150 INCH, SOIC-16;
| 型号： | ICS673-01MLF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PLL Based Clock Driver, 2 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 0.150 INCH, SOIC-16 光电二极管 |
| 文件： | 总8页 (文件大小：104K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS673-01
PLL BUILDING BLOCK
Description
Features
The ICS673-01 is a low cost, high performance Phase
Locked Loop (PLL) designed for clock synthesis and
synchronization. Included on the chip are the phase
detector, charge pump, Voltage Controlled Oscillator
(VCO), and two output buffers. One output buffer is a
divide by two of the other. Through the use of external
reference and VCO dividers (easily implemented with
the ICS674-01), the user can customize the clock to
lock to a wide variety of input frequencies.
• Packaged in 16 pin SOIC
• Access to VCO input and feedback paths of PLL
• VCO operating range up to 135 MHz (5V)
• Able to lock MHz range outputs to kHz range inputs
through the use of external dividers
• Output Enable tri-states outputs
• Low skew output clocks
• Power Down turns off chip
The ICS673-01 also has an output enable function that
puts both outputs into a high-impedance state. The
chip also has a power down feature which turns off the
entire device.
• VCO predivide of 1 or 4
• 25 mA output drive capability at TTL levels
• Advanced, low power, sub-micron CMOS process
• +3.3 V +5 V +10% operating voltage
• Industrial temperature range available
• Forms a complete PLL, using the ICS674-01
For applications that require low jitter or jitter
attenuations, see the MK2069. For a smaller package,
see the ICS663.
Block Diagram
CHCP VCOIN
VDD
2
VDD
Icp
UP
REFIN
FBIN
CLK1
Clock Input
Phase/
Frequency
Detector
1
MUX
0
VCO
2
CLK2
DOWN
4
Icp
PD
(entire chip)
3
CAP
OE (both
outputs)
SEL
GND
External Feedback Divider
(such as the ICS674-01)
MDS 673-01 F
1
Revision 040102
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 295-9800 ● www.icst.com
ICS673-01
PLL BUILDING BLOCK
VCO Predivide Select Table
Pin Assignment
SEL
VCO Postdivide
FBIN
VDD
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
REFIN
NC
0
1
4
1
VDD
CLK1
CLK2
PD
0 = connect pin directly to ground
1 = connect pin directly to VDD
GND
GND
GND
SEL
O E
CHG P
VCO IN
CAP
16 pin narrow (150 m il) SO IC
Pin Descriptions
Pin
Pin
Pin
Pin Description
Number
Name
Type
1
FBIN
Input
Feedback clock input. Connect the feedback clock to this pin. Falling
edge triggered.
2
3
VDD
VDD
GND
GND
GND
CHGP
VCOIN
CAP
OE
Power Connect to +3.3 V or +5 V and to VDD on pin 3.
Power Connect to VDD on pin 2.
4
Power Connect to ground.
5
Power Connect to ground.
6
Power Connect to ground.
7
Output Charge pump output. Connect to VCOIN under normal operation.
8
Input
Input
Input
Input
Input
Input to internal VCO.
9
Loop filter return.
10
11
12
13
14
15
16
Output enable. Active when high. Tri-states both outputs when low.
Select pin fro VCO predivide per table above.
Power down. Turns off entire chip when pin is low. Outputs stop low.
SEL
PD
CLK2
CLK1
NC
Output Clock output 2. Low skew divide by two version of CLK1.
Output Clock output 1.
-
No connect. Nothing is connected internally to this pin.
REFIN
Input
Reference input. Connect reference clock to this pin. Falling edge is
triggered.
MDS 673-01 F
2
Revision 040102
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 295-9800 ● www.icst.com
ICS673-01
PLL BUILDING BLOCK
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS673-01. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Rating
Supply Voltage, VDD
All Inputs and Outputs
7V
-0.5V to VDD+0.5V
0 to +70°C
Ambient Operating Temperature
Industrial Temperature
Storage Temperature
-40 to +85°C
-65 to +150°C
260°C
Soldering Temperature
Recommended Operation Conditions
Parameter
Min.
Typ.
Max.
+70
Units
°C
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
0
+3.13
+5.25
V
DC Electrical Characteristics
VDD=3.3V ±5% or 5.0V ±10%, Ambient temperature -40 to +85°C, unless stated otherwise
Parameter
Operating Voltage
Symbol
VDD
Conditions
Min.
3.13
2
Typ.
Max.
Units
5.50
V
V
Logic Input High Voltage
VIH
REFIN, FBIN,
SEL
Logic Input Low Voltage
VIL
REFIN, FBIN,
SEL
0.8
V
LF Input Voltage Range
Output High Voltage
Output Low Voltage
VI
0
VDD
V
V
V
VOH
VOL
VOH
IOH = -25 mA
IOL = 25mA
IOH = -8 mA
2.4
0.4
Output High Voltage, CMOS
level
VDD-0.4
Operating Supply Current
IDD
VDD = 5.0 V,
15
mA
No load, 40 MHz
Short Circuit Current
IOS
CLK
±100
5
mA
pF
Input Capacitance
CI
SEL
MDS 673-01 F
3
Revision 040102
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 295-9800 ● www.icst.com
ICS673-01
PLL BUILDING BLOCK
AC Electrical Characteristics
VDD = 3.3V ±5%, Ambient Temperature -40 to +85°C, CLOAD at CLK = 15 pF, unless stated otherwise
Parameter
Symbol
Conditions
SEL = 1
Min.
1
Typ. Max. Units
Output Clock Frequency
(from pin CLK)
fCLK
100
25
8
MHz
MHz
MHz
SEL = 0
0.25
Note 1
Input Clock Frequency
fREF
(into pins REFIN or FBIN)
Output Rise Time
tOR
tOF
tDC
tJ
0.8 to 2.0V
2.0 to 0.8V
At VDD/2
1.2
0.75
50
2
ns
ns
Output Fall Time
1.5
60
Output Clock Duty Cycle
Jitter, Absolute peak-to-peak
VCO Gain
40
%
250
TBD
2.5
ps
KO
Icp
MHz/V
µA
Charge Pump Current
VDD = 5.0V ±10%, Ambient Temperature -40 to +85°C, CLOAD at CLK = 15 pF, unless stated otherwise
Parameter
Symbol
Conditions
SEL = 1
Min.
1
Typ. Max. Units
Output Clock Frequency
(from pin CLK)
fCLK
120
30
8
MHz
MHz
MHz
SEL = 0
0.25
Note 1
Input Clock Frequency
fREF
(into pins REFIN or FBIN)
Output Rise Time
tOR
tOF
tDC
tJ
0.8 to 2.0V
2.0 to 0.8V
At VDD/2
0.5
0.5
50
1
1
ns
ns
Output Fall Time
Output Clock Duty Cycle
Jitter, Absolute peak-to-peak
VCO Gain
45
55
%
150
200
2.5
ps
KO
Icp
MHz/V
µA
Charge Pump Current
Note 1: Minimum input frequency is limited by loop filter design. 1 kHz is a practical minimum limit.
External Components
The ICS673-01 requires a minimum number of external
components for proper operation. A decoupling
capacitor of 0.01µF should be connected between
VDD and GND as close to the ICS673-01 as possible.
A series termination resistor of 33 Ω may be used at
the clock output.
1) The loop capacitors should be a low-leakage type to
avoid leakage-induced phase noise. For this reason,
DO NOT use any type of polarized or electrolytic
capacitors.
2) Microphonics (mechanical board vibration) can also
induce output phase noise when the loop bandwidth is
less than 1kHz. For this reason, ceramic capacitors
should have C0G or NP0 dielectric. Avoid high-K
dielectrics like Z5U and X7R. These and some other
Special considerations must be made in choosing loop
components C1 and C2:
MDS 673-01 F
4
Revision 040102
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 295-9800 ● www.icst.com
ICS673-01
PLL BUILDING BLOCK
ceramics have piezoelectric properties that convert
mechanical vibration into voltage noise that interferes
with VCXO operation.
2. If no power good signal is available, a simple
power-on reset circuit can be attached to the PD pin, as
shown in Figure 4. When the power supply ramps up,
this circuit holds PD asserted (device powered down)
until the capacitor charges.
For larger loop capacitor values such as 0.1 µF or 1 µF,
PPS film types made by Panasonic, or metal poly types
made by Murata or Cornell Dubilier are recommended.
For questions or changes regarding loop filter
characteristics, please contact your sales area FAE, or
ICS MicroClock Applications.
VDD
R1
ICS673-01
Avoiding PLL Lockup
PD
In some applications, the ICS673-01 can “lock up” at
the maximum VCO frequency. This is usually caused
by power supply glitches or a very slow power supply
ramp. This situation also occurs if the external divider
starts to fall at high input frequencies. The usual failure
mode of a divider circuit is that the output of the divider
begins to miss clock edges. The phase detector
interprets this as a too low output frequency and
increases the VCO frequency. The feedback divider
begis to miss even more clock edges and the VCO
frequency is continually increased until it is running at
the maximum. Whether caused by power supply issues
or by the existing divider, the loop can only recover by
powering down the circuit, asserting PD, or shorterning
the loop filter to ground.
C3
A. Basic Circuit
VDD
R1
D1
ICS673-01
PD
C3
The simplest way to avoid this problem is to use an
external divider that always operates correctly
regardless of the VCO speed. Figures 2 and 3 show
that the VCO is capable of high speeds. By using the
internal divide-by-four and/or the CLK2 output, the
maximum VCO frequency can be divided by 2, 4, or 8
and a slower counter can be used. Using the ICS673
internal dividers in this manner does reduce the
number of frequencies that can be exactly synthesized
by forcing the total VCO divide to change in increments
of 2, 4, or 8.
B. Faster Discharge
The circuit of Figure 4A is adequate in most cases, but
the discharge rate of capacitor C3 when VDD goes low
is limited by R1. As this discharge rate determines the
minimum reset time, the circuit of Figure 4B may be
used when a faster reset time is desired. The values of
R1 and C3 should be selected to ensure that PD stays
below 1.0 V until the power supply is stable.
3. A comparator circuit may be used to monitor the loop
filter voltage, as shown in Figure 5. This circuit will
dump the charge off the loop filter by asserting PD if the
VCO begins to run too fast and the PLL can recover. A
good choice for thie comparator is the National
Semiconductor LMC7211BIM5X. It is low power, ver
small (SOT-23), low cost, and has high input
impedance.
If this lockup problem occurs, there are several
solutions; three of which are described below.
1. If the system has a reset or power good signal, this
should be applied to the PD pin, forcing the chip to stay
powered down until the power supply voltage has
stabilized
The trigger voltage of the comparator is set by the
voltage divider formed by R2 and R3. The voltage
MDS 673-01 F
5
Revision 040102
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 295-9800 ● www.icst.com
ICS673-01
PLL BUILDING BLOCK
should be set to a vlue higher than the VCO input is
expected to run during normal operation. Typically, this
might be 0.5 V below VDD. Hysteresis should be
added to the circuit by connecting R4.
components which through proper configuration allow
for low input clock reference frequencies, such as a
15.7 kHz Hsync input.
The phase/frequency detector compares the falling
edges of the clocks inputted to FBIN and REFIN. It then
generates an error signal to the charge pump, which
produces a charge proportional to this error. The
external loop filter integrates this charge, producing a
voltage that then controls the frequency of the VCO.
This process continues until the edges of FBIN are
aligned with the edges of the REFIN clock, at which
point the output frequency will be locked to the input
frequency.
The CLK output frequency may be up to 2x the
maximum Output Clock Frequency listed in the AC
Electrical Characteristics above when the device is in
an unlocked condition. Make sure that the external
divider can operate up to this frequency.
Explanation of Operation
The ICS673-01 is a PLL building block circuit that
includes an integrated VCO with a wide operating
range. The device uses external PLL loop filter
Figure 1. Example Configuration -- Generating a 20 MHz clock from a 200 kHz reference.
+3.3 or 5 V
C2
0.01µF
C1
RZ
SEL OE PD VDD
REFIN
CAP
VCOIN
200 kHz
40 MHz
20 MHz
CLK1
CLK2
ICS673-01
FBIN
GND
200 kHz
100
Digital Divider
such as ICS674-01
MDS 673-01 F
6
Revision 040102
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 295-9800 ● www.icst.com
ICS673-01
PLL BUILDING BLOCK
Choosing a damping factor of 0.7 (a minimal damping
factor than can be used to ensure fast lock time),
damping factor equation becomes:
Determining the Loop Filter Values
The loop filter components consist of C1, C2, and RZ.
Calculating these values is best illustrated by an
example. Using the example in Figure 1, we can
synthesize 20 MHz from a 200 kHz input.
200 2.5 C1
--------------------------------
200
25, 000
-----------------
0.7 =
2
The phase locked loop may be approximately
described by the following equations:
and C1 = 1.25 nF (1.2 nF is the nearest standard
value).
The capacitor C2 is used to damp transients from the
charge pump and should be approximately 1/20th the
size of C1, i.e.,
Kv
•
Ic
Bandwidth wn= ---------------
N
•
C1
RZ
------
2
KO ICP C1
------------------------------
N
C2 C1 ⁄ 20
Damping factor, ζ=
Therefore, C2 = 60 pF (56 pF nearest standard value).
where:
To summarize, the loop filter components are:
KO = VCO gain (MHz/Volt)
C1 = 1.2 nf
C2 = 56 pf
Rz = 25 kΩ
Icp = Charge pump current (µA)
N = Total feedback divide from VCO,
including the internal VCO post divider
C1 = Loop filter capacitor (Farads)
RZ = Loop filter resistor (Ohms)
When choosing either CLK1 or CLK2 to drive the
feedback divider, CLK2 should be used whenever
possible.
As a general rule, the bandwidth should be at least 20
times less than the reference frequency, i.e.,
BW ≤ (REFIN) ⁄ 20
In this example, using the above equation, bandwidth
should be less than or equal to 10 kHz. By setting the
bandwith to 10kHz and using the first equation, RZ can
be determined since all other variables are known. In
the example of Figure 1, N = 200, comprising the divide
by 2 on the chip (VCO post divider) and the external
divide by 100. Therefore, the bandwidth equation
becomes:
RZ 200 2.5
-------------------------------
10,000 =
2π 200
and RZ = 25 kΩ
MDS 673-01 F
7
Revision 040102
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 295-9800 ● www.icst.com
ICS673-01
PLL BUILDING BLOCK
Package Outline and Package Dimensions (16 pin SOIC, 150 Mil. Narrow Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters
Inches
Min Max
Symbol
Min
Max
1.75
0.25
0.51
0.25
5.00
4.00
A
A1
B
C
D
E
e
1.35
1.10
0.33
0.19
4.80
3.80
0.0532 0.0688
0.0040 0.0098
0.013
0.0075 0.0098
.1890 .1968
0.020
0.1497 0.1574
0.050 Basic
In de x
A re a
1.27 Basic
E
H
H
h
5.80
0.25
0.40
0°
6.20
0.50
1.27
8°
0.2284 0.2440
0.010
0.016
0°
0.020
0.050
8°
L
a
P in 1
D
h x 4 5 0
A
Q
c
e
b
Ordering Information
Part / Order Number
Marking
Shipping
packaging
Tubes
Package
Temperature
ICS673-01M
ICS673-01M
ICS673-01M
8 pin SOIC
8 pin SOIC
0 to +70° C
0 to +70° C
ICS673-01MT
Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments.
MDS 673-01 F
8
Revision 040102
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 295-9800 ● www.icst.com
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