ICS810252AYI-03 [IDT]
Clock Generator, 156.25MHz, PQFP32, 7 X 7 MM, 1 MM HEIGHT, MS-026ABA-HD, TQFP-32;
| 型号： | ICS810252AYI-03 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, 156.25MHz, PQFP32, 7 X 7 MM, 1 MM HEIGHT, MS-026ABA-HD, TQFP-32 |
| 文件： | 总19页 (文件大小：385K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
VCXO JITTER ATTENUATOR &
FEMTOCLOCK™ MULTIPLIER
ICS810252I-03
GENERAL DESCRIPTION
FEATURES
• Two LVCMOS/LVTTL outputs, 15Ω impedance
Each output supports independent frequency selection at
25MHz, 62.5MHz, 125MHz, and 156.25MHz
The ICS810252I-03 is
a member of the
ICS
HiperClockS™family of high performance clock
solutions from IDT. The ICS810252I-03 is a PLL
based synchronous multiplier that is optimized for
PDH or SONET to Ethernet clock jitter attenuation
HiPerClockS™
• Two differential inputs support the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
and frequency translation. The device contains two internal
frequency multiplication stages that are cascaded in series.
The first stage is a VCXO PLL that is optimized to provide
reference clock jitter attenuation. The second stage is a
FemtoClock™ frequency multiplier that provides the low jitter,
high frequency Ethernet output clock that easily meets Gigabit
and 10 Gigabit Ethernet jitter requirements. Pre-divider and
output divider multiplication ratios are selected using device
selection control pins. The multiplication ratios are optimized
to support most common clock rates used in PDH, SONET
and Ethernet applications. The VCXO requires the use of an
external, inexpensive pullable crystal. The VCXO uses external
passive loop filter components which allows configuration of
the PLL loop bandwidth and damping characteristics. The
device is packaged in a space-saving 32-VFQFN package and
supports industrial temperature range.
• Accepts input frequencies from 8kHz to 155.52MHz including
8kHz, 1.544MHz, 2.048MHz, 19.44MHz, 25MHz, 77.76MHz,
125MHz and 155.52MHz
• Attenuates the phase jitter of the input clock by using a low-
cost pullable funamental mode VCXO crystal
• VCXO PLL bandwidth can be optimized for jitter attenuation
and reference tracking using external loop filter connection
• FemtoClock frequency multiplier provides low jitter, high
frequency output
• Absolute pull range: 50ppm
• FemtoClock VCO frequency: 625MHz
• RMS phase jitter @ 125MHz, using a 25MHz crystal
(12kHz - 20MHz): 1.5ps (typical)
• 3.3V supply voltage
• -40°C to 85°C ambient operating temperature
PIN ASSIGNMENT
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
32 31 30 29 28 27 26 25
1
2
3
4
5
6
LF1
LF0
24
23
22
21
20
19
18
17
GND
VDDO_QB
QB
ISET
GND
GND
ICS810252I-03
CLK_SEL
VDD
VDDO_QA
QA
RESERVED
GND
7
8
GND
ODASEL_0
9 10 11 12 13 14 15 16
32-Lead VFQFN
5mm x 5mm x 0.925 package body
K Package
Top View
32-Lead TQFP, E-Pad
7mm x 7mm x 1.0mm package body
Y package
Top View
The Preliminary Information presented herein represents a product in pre-production.The noted characteristics are based on initial product characterization
and/or qualification.Integrated DeviceTechnology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER
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ICS810252AKI-03 REV. B OCTOBER 24, 2007
ICS810252I-03
VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
PRELIMINARY
BLOCK DIAGRAM
Loop
Filter
Pullup
Output
Divider
PDSEL_[2:0]
QA
00 = 25
01 = 5
10 = 4
VCXO Input
Pre-Divider
25MHz
11 = 10
CLK0
Phase
Detector
000 = 1
0
1
nCLK0
2
001 = 193
010 = 256
011 = 2430
100 = 3125
101 = 9720
110 = 15625
111 = 19440
ODASEL_[1:0]
FemtoClock PLL
625MHz
VCXO
Charge
Pump
CLK1
nCLK1
Output
Divider
VCXO Feedback Divider
÷3125
Pulldown
CLK_SEL
QB
00 = 25
01 = 5
VCXO Jitter Attenuation PLL
10 = 4
11 = 10
2
ODBSEL_[1:0]
IDT™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER
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VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
PRELIMINARY
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Analog
Input/Output
Description
1, 2
LF1, LF0
Loop filter connection node pins.
Analog
Input/Output
3
ISET
GND
Charge pump current setting pin.
4, 8, 18,
21, 24
Power
Input
Power supply ground.
Input clock select. When HIGH selects CLK1/nCLK1.
When LOW, selects CLK0/nCLK0. LVCMOS/LVTTL interface levels.
5
CLK_SEL
Pulldown
Pullup
6, 12, 27
7
VDD
Power
Core power supply pins.
RESERVED
Reserved
Reserved pin. Do not connect.
9,
10,
11
PDSEL_2,
PDSEL_1,
PDSEL_0
Pre-divider select pins. LVCMOS/LVTTL interface levels.
See Table 3A.
Input
13
VDDA
Power
Input
Analog supply pin.
14,
15
16,
17
ODBSEL_1,
ODBSEL_0
ODASEL_1,
ODASEL_0
Frequency select pins for Bank B output. See Table 3B.
LVCMOS/LVTTL interface levels.
Frequency select pins for Bank A output. See Table 3B.
LVCMOS/LVTTL interface levels.
Pulldown
Pulldown
Input
Bank A single-ended clock output. LVCMOS/LVTTL interface levels.
15Ω output impedance.
19
20
QA
Output
Power
VDDO_QA
Output power supply pin for QA clock output.
Bank B single-ended clock output. LVCMOS/LVTTL interface levels.
15Ω output impedance.
22
23
25
26
28
29
QB
Output
Power
Input
VDDO_QB
nCLK1
CLK1
Output power supply pin for QB clock output.
Pullup/
Pulldown
Inverting differential clock input. VDD/2 bias voltage when left floating.
Input
Pulldown Non-inverting differential clock input.
Pullup/
nCLK0
Input
Inverting differential clock input. VDD/2 bias voltage when left floating.
Pulldown
CLK0
Input
Pulldown Non-inverting differential clock input.
30,
31
XTAL_OUT,
XTAL_IN
Crystal oscillator interface. XTAL_IN is the input.
XTAL_OUT is the output.
Input
32
VDDX
Power
Power supply pin for VCXO charge pump.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
CIN
Input Capacitance
4
pF
Power Dissipation Capacitance
(per output)
CPD
VDD, VDDX, VDDO_QA, VDDO_QB = 3.465V
TBD
pF
RPULLUP
Input Pullup Resistor
51
51
15
kΩ
kΩ
Ω
RPULLDOWN Input Pulldown Resistor
ROUT Output Impedance
IDT™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER
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ICS810252AKI-03 REV. B OCTOBER 24, 2007
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VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
PRELIMINARY
TABLE 3A. PRE-DIVIDER FUNCTION TABLE
Inputs
Pre-Divider Value
PDSEL_2
PDSEL_1 PDSEL_0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
193
256
2430
3125
9720
15625
19440 (default)
TABLE 3B. OUTPUT DIVIDER FUNCTION TABLE
Inputs
Output Divider Value
ODxSEL_1
ODxSEL_0
0
0
1
1
0
1
0
1
25 (default)
5
4
10
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VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
PRELIMINARY
TABLE 3C. FREQUENCY FUNCTION TABLE
Input
Frequency
(MHz)
VCXO
FemtoClock
Femtoclock
Pre-Divider
Value
Output Divider Output Frequency
Frequency Feedback Divider VCO Frequency
Value
(MHz)
(MHz)
Value
(MHz)
0.008
0.008
0.008
0.008
1.544
1.544
1.544
1.544
2.048
2.048
2.048
2.048
19.44
19.44
19.44
19.44
25
1
25
25
625
25
5
25
125
1
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
625
625
625
625
625
625
625
625
625
625
625
625
625
625
625
625
625
625
625
625
625
625
625
625
625
625
625
625
625
625
625
1
4
156.25
62.5
25
1
10
25
5
193
193
125
193
4
156.25
62.5
25
193
10
25
5
256
256
125
256
4
156.25
62.5
25
256
10
25
5
2430
2430
2430
2430
3125
3125
3125
3125
9720
9720
9720
9720
15625
15625
15625
15625
19440
19440
19440
19440
125
4
156.25
62.5
25
10
25
5
25
125
25
4
156.25
62.5
25
25
10
25
5
77.76
77.76
77.76
77.76
125
125
4
156.25
62.5
25
10
25
5
125
125
125
4
156.25
62.5
25
125
10
25
5
155.52
155.52
155.52
155.52
125
4
156.25
62.5
10
IDT™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER
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ICS810252I-03
VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
Inputs, V
-0.5V to VDD + 0.5V
-0.5V to VDDO + 0.5V
I
Outputs, VO
Package Thermal Impedance, θ
32 Lead VFQFN
32 Lead TQFP
JA
37°C/W (0 mps)
32.2°C/W (0 mps)
Storage Temperature, T
-65°C to 150°C
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO_QA = VDDO_QB = VDDX = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol
VDD
Parameter
Test Conditions
Minimum Typical Maximum Units
Core Supply Voltage
Analog Supply Voltage
3.135
3.3
3.3
3.465
VDD
V
V
VDDA
VDD – 0.11
VDDO_QA,
VDDO_QB
Output Supply Voltage
3.135
3.135
3.3
3.465
3.465
V
VDDX
Charge Pump Supply Voltage
3.3
V
Power and Charge Pump
Supply Current
IDD + IDDX
IDDA
158
mA
Analog Supply Current
11
1
mA
mA
IDDO_QA + IDDO_QB Output Supply Current
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDO_QA = VDDO_QB = VDDX = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
Input High Voltage
Input Low Voltage
CLK_SEL,
2
VDD + 0.3
V
VIL
-0.3
0.8
V
ODASEL_[0:1],
ODBSEL_[0:1]
VDD = VIN = 3.465V
VDD = VIN = 3.465V
150
5
µA
µA
µA
Input
High Current
IIH
PDSEL{0:2]
CLK_SEL,
ODASEL_[0:1],
ODBSEL_[0:1]
VDD = 3.465V, VIN = 0V
-5
Input
Low Current
IIL
PDSEL{0:2]
VDD = 3.465V, VIN = 0V
-150
2.6
µA
VOH
VOL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
V
V
0.5
NOTE 1: Outputs terminated with 50Ω to VDDO_QA,_QB/2.
IDT™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER
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ICS810252AKI-03 REV. B OCTOBER 24, 2007
ICS810252I-03
VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
PRELIMINARY
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDO_QA = VDDO_QB = VDDX = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
IIH Input High Current
Test Conditions
VIN = VDD = 3.465V
VIN = 0V, VDD = 3.465V
Minimum Typical Maximum Units
CLK0/nCLK0,
CLK1/nCLK1
150
µA
CLK0, CLK1
-5
-150
µA
µA
V
IIL
Input Low Current
nCLK0, nCLK1
VIN = 0V, VDD = 3.465V
VPP
Peak-to-Peak Input Voltage; NOTE 1
0.15
1.3
VCMR
Common Mode Input Voltage; NOTE 1, 2
GND + 0.5
VDD - 0.85
V
NOTE 1: VIL should not be less than -0.3V.
NOTE 2: Common mode voltage is defined as VIH.
TABLE 5. AC CHARACTERISTICS, VDD = VDDO_QA = VDDO_QB = VDDX = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fIN
Input Frequency
0.008
25
155.52
156.25
MHz
MHz
fOUT
Output Frequency
125MHz, 25MHz crystal
Integration Range:
12kHz - 20MHz
RMS Phase Jitter (Random);
NOTE 1
tjit(Ø)
1.5
ps
tsk(o)
odc
Output Skew; NOTE 2, 3
Output Duty Cycle
Output Rise/Fall Time
PLL Lock Time
60
50
ps
ꢀ
tR / tF
tLOCK
20ꢀ to 80ꢀ
400
100
ps
ms
NOTE 1: Please refer to the Phase Noise Plot.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load condtions.
Measured at the output differential cross points.
IDT™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER
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ICS810252I-03
VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
PRELIMINARY
PARAMETER MEASUREMENT INFORMATION
1.65V 5ꢀ
1.65V 5ꢀ
VDD
SCOPE
,
VDD
VDDO_QA,
VDDO_QB,
VDDX
nCLK0,
nCLK1
VDDA
Qx
VPP
VCMR
Cross Points
LVCMOS
CLK0,
CLK1
GND
GND
-1.65V 5ꢀ
DIFFERENTIAL INPUT LEVEL
3.3V OUTPUT LOAD AC TEST CIRCUIT
Phase Noise Plot
VDDO
FOUTx
FOUTy
2
VDDO
2
Phase Noise Mask
tsk(o)
Offset Frequency
f1
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
PHASE JITTER
OUTPUT SKEW
VDDO
2
80ꢀ
tF
80ꢀ
tR
QA, QB
tPW
20ꢀ
20ꢀ
tPERIOD
Clock
Outputs
tPW
x 100ꢀ
odc =
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/tPERIOD
OUTPUT RISE/FALL TIME
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VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
PRELIMINARY
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS810252I-03 provides
separate power supplies to isolate any high switching noise
from the outputs to the internal PLL. VDD, VDDX, VDDA, VDDO_QA
and VDDO_QB should be individually connected to the power sup-
ply plane through vias, and bypass capacitors should be used
for each pin. To achieve optimum jitter performance, power
supply isolation is required. Figure 1 illustrates how a 10Ω re-
sistor along with a 10mF and a .01mF bypass capacitor should
be connected to each VDDA pin.
3.3V
VDD
VDDX
VDDA
.01µF
.01µF
10Ω
10Ω
10µF
.01µF
10µF
FIGURE 1. POWER SUPPLY FILTERING
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
CRYSTAL INPUTS
LVCMOS OUTPUTS
For applications not requiring the use of the crystal oscillator
input, both XTAL_IN and XTAL_OUT can be left floating. Though
not required, but for additional protection, a 1kΩ resistor can be
tied from XTAL_IN to ground.
All unused LVCMOS output can be left floating. There should be
no trace attached.
CLK/nCLK INPUT
For applications not requiring the use of the differential input,
both CLK and nCLK can be left floating. Though not required, but
for additional protection, a 1kΩ resistor can be tied from CLK to
ground.
LVCMOS CONTROL PINS
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
IDT™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER
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ICS810252I-03
VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
PRELIMINARY
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF ~ V /2 is
generated by the bias resistors R1, R2 and C1. This bias DcDircuit
should be located as close as possible to the input pin. The ratio
clock swing is only 2.5V and V = 3.3V, V_REF should be 1.25V
DD
and R2/R1 = 0.609.
VDD
R1
1K
Single Ended Clock Input
V_REF
CLK
nCLK
C1
0.1u
R2
1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
IDT™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER
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ICS810252I-03
VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
PRELIMINARY
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both signals must meet the VPP
and VCMR input requirements. Figures 3A to 3F show interface
examples for the HiPerClockS CLK/nCLK input driven by the
most common driver types. The input interfaces suggested here
are examples only. Please consult with the vendor of the driver
component to confirm the driver termination requirements. For
example in Figure 3A, the input termination applies for IDT
HiPerClockS open emitter LVHSTL drivers. If you are using an
LVHSTL driver from another vendor, use their termination
recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
HiPerClockS
LVPECL
Input
nCLK
HiPerClockS
LVHSTL
Input
R1
50
R2
50
ICS
R1
50
R2
50
HiPerClockS
LVHSTL Driver
R3
50
FIGURE 3A. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY AN IDT OPEN EMITTER
FIGURE 3B. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY A 3.3V LVPECL DRIVER
HIPERCLOCKS LVHSTL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
3.3V
R3
125
R4
125
LVDS_Driver
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
R1
100
nCLK
Receiv er
nCLK
HiPerClockS
Input
Zo = 50 Ohm
LVPECL
R1
84
R2
84
FIGURE 3C. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY A 3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY A 3.3V LVDS DRIVER
2.5V
2.5V
3.3V
3.3V
2.5V
R3
R4
120
120
Zo = 50Ω
Zo = 50Ω
*R3
*R4
33
33
Zo = 60Ω
Zo = 60Ω
CLK
CLK
nCLK
nCLK
HiPerClockS
HiPerClockS
Input
SSTL
HCSL
R1
50
R2
50
R1
120
R2
120
*Optional – R3 and R4 can be 0Ω
FIGURE 3F. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY A 2.5V SSTL DRIVER
FIGURE 3E. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY A 3.3V HCSL DRIVER
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VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
PRELIMINARY
VFQFN EPADTHERMAL RELEASE PATH
In order to maximize both the removal of heat from the package
and the electrical performance, a land pattern must be
incorporated on the Printed Circuit Board (PCB) within the footprint
of the package corresponding to the exposed metal pad or
exposed heat slug on the package, as shown in Figure 4. The
solderable area on the PCB, as defined by the solder mask, should
be at least the same size/shape as the exposed pad/slug area on
the package to maximize the thermal/electrical performance.
Sufficient clearance should be designed on the PCB between the
outer edges of the land pattern and the inner edges of pad pattern
for the leads to avoid any shorts.
are application specific and dependent upon the package power
dissipation as well as electrical conductivity requirements. Thus,
thermal and electrical analysis and/or testing are recommended
to determine the minimum number needed. Maximum thermal
and electrical performance is achieved when an array of vias is
incorporated in the land pattern. It is recommended to use as
many vias connected to ground as possible. It is also
recommended that the via diameter should be 12 to 13mils (0.30
to 0.33mm) with 1oz copper via barrel plating. This is desirable to
avoid any solder wicking inside the via during the soldering process
which may result in voids in solder between the exposed pad/
slug and the thermal land. Precautions should be taken to
eliminate any solder voids between the exposed heat slug and
the land pattern. Note: These recommendations are to be used
as a guideline only. For further information, refer to the Application
Note on the Surface Mount Assembly of Amkor’s Thermally/
Electrically Enhance Leadfame Base Package, Amkor Technology.
While the land pattern on the PCB provides a means of heat
transfer and electrical grounding from the package to the board
through a solder joint, thermal vias are necessary to effectively
conduct from the surface of the PCB to the ground plane(s). The
land pattern must be connected to ground through these vias.
The vias act as “heat pipes”.The number of vias (i.e. “heat pipes”)
SOLDER
SOLDER
PIN
PIN
EXPOSED HEAT SLUG
PIN PAD
GROUND PLANE
LAND PATTERN
(GROUND PAD)
PIN PAD
THERMAL VIA
FIGURE 4. P.C.ASSEMBLY FOR EXPOSED PAD THERMAL RELEASE PATH –SIDE VIEW (DRAWING NOT TO SCALE)
TQFPTHERMAL RELEASE PATH
The expose metal pad provides heat transfer from the device to
the P.C. board. The expose metal pad is ground pad connected
to ground plane through thermal via. The exposed pad on the
device to the exposed metal pad on the PCB is contacted through
solder as shown in Figure 5. For further information, please refer
to the Application Note on Surface Mount Assembly of Amkor’s
Thermally /Electrically Enhance Leadframe Base Package,
Amkor Technology.
EXPOSED PAD
SOLDER
SOLDER MASK
SIGNAL
TRACE
SIGNAL
TRACE
GROUND PLANE
Expose Metal Pad
(GROUND PAD)
THERMAL VIA
FIGURE 5. P.C. BOARD FOR EXPOSED PAD THERMAL RELEASE PATH EXAMPLE
IDT™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER
12
ICS810252AKI-03 REV. B OCTOBER 24, 2007
ICS810252I-03
VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
PRELIMINARY
LAYOUT GUIDELINE
Figure 6 shows an example of the 810252I-03 application
The decoupling capacitors should be located as close as possible
to the power pin. The input is driven by a 3.3V LVPECL driver.
schematic. In this example, the device is operated at V = 3.3V.
DD
FIGURE 6. SCHEMATIC OF RECOMMENDED LAYOUT
IDT™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER
13
ICS810252AKI-03 REV. B OCTOBER 24, 2007
ICS810252I-03
VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
PRELIMINARY
VCXO-PLL EXTERNAL COMPONENTS
Choosing the correct external components and having a proper
printed circuit board (PCB) layout is a key task for quality
operation of the VCXO-PLL. In choosing a crystal, special
precaution must be taken with the package and load
the crystal specification. In either case, the absolute tuning
range is reduced. The correct value of C is dependant on the
L
characteristics of the VCXO. The recommended C in the
L
Crystal Parameter Table balances the tuning range by
capacitance (C ). In addition, frequency, accuracy and
centering the tuning curve.
L
temperature range must also be considered. Since the pulling
range of a crystal also varies with the package, it is
recommended that a metal-canned package like HC49 be
used. Generally, a metal-canned package has a larger pulling
range than a surface mounted device (SMD). For crystal
selection information, refer to the VCXO Crystal Selection
Application Note.
The VCXO-PLL Loop Bandwidth Selection Table shows R , C
S
S
and C values for recommended high, mid and low loop
P
bandwidth configurations. The device has been characterized
using these parameters. For other configurations, refer to the
Loop Filter Component Selection for VCXO Based PLLs
Application Note.
LF0
LF1
ISET
The crystal and external loop
filter components should be
kept as close as possible to
The crystal’s load capacitance C characteristic determines its
L
resonating frequency and is closely related to the VCXO tuning
range. The total external capacitance seen by the crystal when
installed on a board is the sum of the stray board capacitance,
IC package lead capacitance, internal varactor capacitance and
RS RSET
the device. Loop filter and
CP CS
crystal traces should be kept
short and separated from
any installed tuning capacitors (C ).
TUNE
each other. Other signal
traces should be kept
XTAL_IN
If the crystal C is greater than the total external capacitance,
CTUNE
L
the VCXO will oscillate at a higher frequency than the crystal
separate and not run
underneath the device, loop
filter or crystal components.
25MHz
specification. If the crystal C is lower than the total external
XTAL_OUT
L
CTUNE
capacitance, the VCXO will oscillate at a lower frequency than
VCXO CHARACTERISTICS TABLE
Symbol Parameter
Typical
8000
8
Unit
Hz/V
pF
kVCXO
VCXO Gain
CV_LOW
CV_HIGH
Low Varactor Capacitance
High Varactor Capacitance
17
pF
VCXO-PLL LOOP BANDWIDTH SELECTION TABLE
Bandwidth
50Hz (Low)
50Hz (Mid)
150Hz (High)
Crystal Frequency (MHz)
RS (kΩ)
CS (µF)
1.0
CP (µF)
0.01
RSET (kΩ)
8.8
25MHz
25MHz
25MHz
120
221
680
0.1
0.001
0.0001
2.21
0.1
2.21
CRYSTAL CHARACTERISTICS
Symbol Parameter
Mode of Operation
Minimum Typical
Maximum
Units
Fundamental
fN
fT
fS
Frequency
25
MHz
ppm
ppm
°C
Frequency Tolerance
Frequency Stability
Operating Temperature Range
Load Capacitance
Shunt Capacitance
Pullability Ratio
20
20
-40
85
CL
10
4
pF
CO
pF
CO/C1
ESR
220
240
Equivalent Series Resistance
Drive Level
20
1
mW
ppm
Aging @ 25°C
3 per year
IDT™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER
14
ICS810252AKI-03 REV. B OCTOBER 24, 2007
ICS810252I-03
VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
PRELIMINARY
RELIABILITY INFORMATION
TABLE 6A. θ VS. AIR FLOW TABLE FOR 32 LEAD VFQFN
JA
θ vs. 0 Air Flow (Meters per Second)
JA
0
1
2.5
29.0°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
37.0°C/W
32.4°C/W
TABLE 6B. θ VS. AIR FLOW TABLE FOR 32 LEAD TQFP, E-PAD
JA
θ by Velocity (Meters per Second)
JA
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
32.2°C/W
26.3°C/W
24.7°C/W
TRANSISTOR COUNT
The transistor count for ICS810252I-03 is: 6597
IDT™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER
15
ICS810252AKI-03 REV. B OCTOBER 24, 2007
ICS810252I-03
VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
PRELIMINARY
PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD TQFP, E-PAD
-HD VERSION
EXPOSED PAD DOWN
TABLE 7A. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
ABA-HD
SYMBOL
MINIMUM
NOMINAL
32
MAXIMUM
N
A
--
--
1.20
0.15
1.05
0.40
0.20
A1
0.05
0.95
0.30
0.09
0.10
A2
1.0
b
0.35
c
D, E
D1, E1
D2, E2
e
--
9.00 BASIC
7.00 BASIC
5.60 Ref.
0.80 BASIC
L
0.45
0.75
θ
--
--
0
°
7°
ccc
--
3.0
0.10
4.0
D3 & D3
3.5
Reference Document: JEDEC Publication 95, MS-026
IDT™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER
16
ICS810252AKI-03 REV. B OCTOBER 24, 2007
ICS810252I-03
VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
PRELIMINARY
PACKAGE OUTLINE AND DIMENSIONS - K SUFFIX FOR 32 LEAD VFQFN
NOTE: The following package mechanical drawing is a generic
drawing that applies to any pin count VFQFN package.This draw-
ing is not intended to convey the actual pin count or pin layout of
this device.The pin count and pinout are shown on the front page.
The package dimensions are in Table 7B below.
TABLE 7B. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
VHHD-2
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
--
0.80
0
1.00
0.05
A1
A3
b
--
0.25 Ref.
0.25
0.18
0.30
8
ND
NE
D
8
5.00 BASIC
2.25
D2
E
1.25
1.25
0.30
3.25
3.25
0.50
5.00 BASIC
2.25
E2
e
0.50 BASIC
0.40
L
Reference Document: JEDEC Publication 95, MO-220
IDT™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER
17
ICS810252AKI-03 REV. B OCTOBER 24, 2007
ICS810252I-03
VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
PRELIMINARY
TABLE 8. ORDERING INFORMATION
Part/Order Number
810252AKI-03
Marking
ICS0252AI03
ICS0252AI03
ICS252AI03L
ICS252AI03L
TBD
Package
Shipping Packaging
tray
Temperature
32 Lead VFQFN
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
810252AKI-03T
810252AKI-03LF
810252AKI-03LFT
810252AYI-03
32 Lead VFQFN
2500 tape & reel
tray
32 Lead "Lead-Free" VFQFN
32 Lead "Lead-Free" VFQFN
32 lead TQFP, E-Pad
2500 tape & reel
tray
810252AYI-03T
810252AYI-03LF
810252AYI-03LFT
TBD
32 lead TQFP, E-Pad
1000 tape & reel
tray
ICS0252AI03L
ICS0252AI03L
32 lead "Lead-Free" TQFP, E-Pad
32 lead "Lead-Free" TQFP, E-Pad
1000 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and
industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT
reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER
18
ICS810252AKI-03 REV. B OCTOBER 24, 2007
ICS810252I-03
VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
PRELIMINARY
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
800-345-7015
408-284-8200
Fax: 408-284-2775
For Tech Support
netcom@idt.com
480-763-2056
Corporate Headquarters
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
Asia Pacific and Japan
Integrated Device Technology
Singapore (1997) Pte. Ltd.
Reg. No. 199707558G
435 Orchard Road
Europe
IDT Europe, Limited
321 Kingston Road
Leatherhead, Surrey
KT22 7TU
United States
800 345 7015
#20-03 Wisma Atria
England
+408 284 8200 (outside U.S.)
Singapore 238877
+44 (0) 1372 363 339
Fax: +44 (0) 1372 378851
+65 6 887 5505
© 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks
of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be
trademarks or registered trademarks used to identify products or services of their respective owners.
Printed in USA
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