ICS8304M-01 [IDT]
Low Skew Clock Driver, 0 True Output(s), 4 Inverted Output(s), PDSO8, 3.80 X 4.80 MM, 1.47 MM HEIGHT, MS-012, SOIC-8;
| 型号： | ICS8304M-01 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew Clock Driver, 0 True Output(s), 4 Inverted Output(s), PDSO8, 3.80 X 4.80 MM, 1.47 MM HEIGHT, MS-012, SOIC-8 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总11页 (文件大小：106K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS8304-01
LOW SKEW, 1-TO-4
LVCMOS / LVTTL INVERTING FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
GENERAL DESCRIPTION
FEATURES
The ICS8304-01 is a low skew, 1-to-4 Invert- • 4 LVCMOS / LVTTL outputs
,&6
ing Fanout Buffer and a member of the
HiPerClockS™ family of High Performance
Clock Solutions from ICS. The ICS8304-01
is characterized at full 3.3V for input VDD, and
• LVCMOS clock input
HiPerClockS™
• Output frequency: 166MHz
• Output skew: 50ps (maximum)
mixed 3.3V and 2.5V for output operating supply modes
(VDDO). Guaranteed output and part-to-part skew char-
acteristics make the ICS8304-01 ideal for those clock
distribution applications demanding well defined per-
formance and repeatability.
• Part-to-part skew: 600ps (maximum)
• Small 8 lead SOIC package saves board space
• 3.3V input, outputs may be either 3.3V or 2.5V supply modes
• 0°C to 70°C ambient operating temperature
BLOCK DIAGRAM
PIN ASSIGNMENT
nQ0
VDDO
VDD
nQ3
nQ2
nQ1
nQ0
1
2
3
4
8
7
6
5
CLK
GND
nQ1
CLK
nQ2
ICS8304-01
8-Lead SOIC
3.8mm x 4.8mm x 1.47mm package body
nQ3
M Package
Top View
8304AM-01
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REV. C JUNE 17, 2002
1
ICS8304-01
LOW SKEW, 1-TO-4
LVCMOS / LVTTL INVERTING FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
TABLE 1. PIN DESCRIPTIONS
Number
Name
VDDO
VDD
Type
Description
1
2
3
4
5
6
7
8
Power
Power
Input
Output supply pin.
Positive supply pin.
CLK
GND
nQ0
nQ1
nQ2
nQ3
Pulldown LVCMOS / LVTTL clock input.
Power supply ground.
Power
Output
Output
Output
Output
Inverted version of clock input. LVCMOS / LVTTL interface levels.
Inverted version of clock input. LVCMOS / LVTTL interface levels.
Inverted version of clock input. LVCMOS / LVTTL interface levels.
Inverted version of clock input. LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum Units
CIN
Input Capacitance
4
pF
pF
Power Dissipation Capacitance
(per output)
CPD
VDD, VDDO = 3.465V
15
RPULLUP
Input Pullup Resistor
51
51
7
KΩ
KΩ
Ω
RPULLDOWN Input Pulldown Resistor
ROUT
Output Impedance
8304AM-01
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REV. C JUNE 17, 2002
2
ICS8304-01
LOW SKEW, 1-TO-4
LVCMOS / LVTTL INVERTING FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDDx
Inputs, VI
4.6V
-0.5V to VDD+ 0.5V
-0.5V to VDDO + 0.5V
Outputs, VO
Package Thermal Impedance, θJA
Storage Temperature, TSTG
112.7°C/W (0 lfpm)
-65°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended peri-
ods may affect product reliability.
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
VDD
Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
Power Supply Voltage
Output Power Supply Voltage
Power Supply Current
Output Supply Current
3.465
3.465
15
V
VDDO
IDD
3.135
3.3
V
mA
mA
IDDO
8
TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VIH
VIL
IIH
Input High Voltage
2
VDD + 0.3
1.3
V
V
Input Low Voltage
-0.3
Input High Current
VDD = VIN = 3.465V
150
µA
µA
V
IIL
Input Low Current
VDD = 3.465V, VIN = 0V
-5
VOH
VOL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
2.6
0.5
V
NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement Information Section",
"3.3V Output Load Test Circuit".
TABLE 4A. AC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
fMAX Output Frequency
tPD
Test Conditions
Minimum
Typical
Maximum
166
Units
MHz
ns
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Output Rise Time
IJ 166MHz
2.3
3.5
tsk(o)
tsk(pp)
tR
50
ps
600
ps
30% to 70%
30% to 70%
f ≤ 166MHz
250
250
40
500
ps
tF
Output Fall Time
500
ps
odc
Output Duty Cycle
60
%
All parameters measured at 166MHz unless noted otherwise.
NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. Measured from the rising edge of
the input to the falling edge of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDDO/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at VDDO/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
8304AM-01
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REV. C JUNE 17, 2002
3
ICS8304-01
LOW SKEW, 1-TO-4
LVCMOS / LVTTL INVERTING FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
TABLE 3C. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VDD
VDDO
IDD
Positive Supply Voltage
3.465
2.625
15
V
Output Supply Voltage
Power Supply Current
Output Supply Current
2.375
2.5
V
mA
mA
IDDO
8
TABLE 3D. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VIH
VIL
IIH
Input High Voltage
2
VDD + 0.3
1.3
V
V
Input Low Voltage
-0.3
Input High Current
VDD = VIN = 3.465V
150
µA
µA
V
IIL
Input Low Current
VDD = 3.465V, VIN = 0V
-5
VOH
VOL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
2.1
0.5
V
NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement Information Section,
"3.3V/2.5V Output Load Test Circuit".
TABLE 4B. AC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C TO 70°C
Symbol Parameter
fMAX Maximum Output Frequency
tPD
Test Conditions
Minimum Typical Maximum Units
166
3.6
50
MHz
ns
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Output Rise Time
IJ 166MHz
2.5
tsk(o)
tsk(pp)
tR
ps
600
500
500
60
ps
30% to 70%
30% to 70%
f ≤ 166MHz
250
250
40
ps
tF
Output Fall Time
ps
odc
Output Duty Cycle
%
All parameters measured at 166MHz unless noted otherwise.
NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. Measured from the rising edge of
the input to the falling edge of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDDO/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at VDDO/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
8304AM-01
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REV. C JUNE 17, 2002
4
ICS8304-01
LOW SKEW, 1-TO-4
LVCMOS / LVTTL INVERTING FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
PARAMETER MEASUREMENT INFORMATION
1.65V±5%
SCOPE
VDD,
VDDO
Qx
LVCMOS
GND
VDDO
2
-1.65V±5%
3.3V OUTPUT LOAD TEST CIRCUIT
1.25V±5%
2.05V±5%
SCOPE
VDD
VDDO
Qx
LVCMOS
GND
VDDO
2
-1.25V±5%
3.3V/2.5V OUTPUT LOAD TEST CIRCUIT
8304AM-01
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REV. C JUNE 17, 2002
5
ICS8304-01
LOW SKEW, 1-TO-4
LVCMOS / LVTTL INVERTING FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
nQx
VDDO
2
nQy
VDDO
2
tsk(o)
OUTPUT SKEW
nQx
VDDO
2
PART 1
nQy
VDDO
PART 2
2
tsk(pp)
PART-TO-PART SKEW
70%
70%
30%
30%
Clock Inputs
and Outputs
tR
tF
INPUT AND OUTPUT RISE AND FALL TIME
8304AM-01
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REV. C JUNE 17, 2002
6
ICS8304-01
LOW SKEW, 1-TO-4
LVCMOS / LVTTL INVERTING FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
VDD
2
CLK
nQ0:nQ3
VDDO
2
tPD
PROPAGATION DELAY
nQx
VDDO
2
Pulse Width
tPERIOD
odc & tPERIOD
8304AM-01
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REV. C JUNE 17, 2002
7
ICS8304-01
LOW SKEW, 1-TO-4
LVCMOS / LVTTL INVERTING FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
TABLE 5. θJAVS. AIR FLOW TABLE
qJA by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
153.3°C/W
128.5°C/W
115.5°C/W
112.7°C/W
103.3°C/W
97.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8304-01 is: 416
8304AM-01
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REV. C JUNE 17, 2002
8
ICS8304-01
LOW SKEW, 1-TO-4
LVCMOS / LVTTL INVERTING FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
PACKAGE OUTLINE - SUFFIX M
TABLE 6. PACKAGE DIMENSIONS - SUFFIX M
Millimeters
MINIMUN MAXIMUM
SYMBOL
N
A
A1
B
C
D
E
e
8
1.35
0.10
0.33
0.19
4.80
3.80
1.75
0.25
0.51
0.25
5.00
4.00
1.27 BASIC
H
h
5.80
0.25
0.40
0°
6.20
0.50
1.27
8°
L
α
Reference Document: JEDEC Publication 95, MS-012
8304AM-01
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REV. C JUNE 17, 2002
9
ICS8304-01
LOW SKEW, 1-TO-4
LVCMOS / LVTTL INVERTING FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
TABLE 6. ORDERING INFORMATION
Part/Order Number
ICS8304M-01
Marking
8304AM01
8304AM01
Package
8 lead SOIC
Count
96 per tube
2500
Temperature
0°C to 70°C
0°C to 70°C
ICS8304M-01T
8 lead SOIC on Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
8304AM-01
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REV. C JUNE 17, 2002
10
ICS8304-01
LOW SKEW, 1-TO-4
LVCMOS / LVTTL INVERTING FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
REVISION HISTORY SHEET
Description of Change
Rev
Table
Page
Date
4A
3
AC Characteristics Table - revised tpLH row to tPD and revised NOTE 1.
Deleted tpHL row.
B
4B
4
4/9/02
AC Characteristics Table - revised tpLH row to tPD and revised NOTE 1.
Deleted tpHL row.
Updated Figures.
6 & 7
AC Characteristics Table - changed tsk(pp) Part-to-Part Skew from 250ps Max.
to 600ps Max.
4A
4B
3
4
C
C
5/20/02
6/17/02
AC Characteristics Table - changed tsk(pp) Part-to-Part Skew from 250ps Max.
to 600ps Max.
6
10
Ordering Information, updated marking from 8304-01 to 8304AM01
8304AM-01
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REV. C JUNE 17, 2002
11
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