ICS843001BGI-23LF [IDT]
Clock Generator, 650MHz, PDSO24, 4.40 X 7.80 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-24;
| 型号： | ICS843001BGI-23LF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, 650MHz, PDSO24, 4.40 X 7.80 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-24 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总18页 (文件大小：328K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-
3.3V LVPECL/LVCMOS SYNTHESIZER
ICS843001I-23
GENERAL DESCRIPTION
FEATURES
The ICS843001I-23 is a highly versatile, low phase
• One 3.3V LVPECL output pair and
ICS
noise LVPECL/LVCMOS Synthesizer which can
generate low jitter reference clocks for a variety of
communication applications and is a member of
the HiPerClocksTM family of high performance clock
solutions from IDT. The dual crystal interface
one LVCMOS/LVTTL REF_OUT output
HiPerClockS™
• Selectable crystal oscillator interfaces
or LVCMOS/LVTTL single-ended input
• Crystal and CLK range: 17.5MHz - 29.54MHz
allows the synthesizer to support up to three communication
standards in a given application (i.e. SONET with a 19.44MHz
crystal, 1Gb/10Gb Ethernet and Fibre Channel using a 25MHz
crystal). The rms phase jitter performance is typically less than
1ps, thus making the device acceptable for use in demanding
applications such as OC48 SONET, GbE/10Gb Ethernet
and SAN applications. The ICS843001I-23 is packaged in
a small 24-pin TSSOP package.
• Able to generate GbE/10GbE/12GbE, Fibre Channel
(1Gb/4Gb/10Gb), PCI-E and SATA from a 25MHz crystal
• VCO range: 1.12GHz - 1.3GHz
• Supports the following applications:
SONET, Ethernet, Fibre Channel, Serial ATA, and HDTV
• RMS phase jitter @ 622.08MHz (12kHz - 20MHz):
0.9ps (typical) @ 3.3V
• Supply modes:
VCC/VCCO
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
BLOCK DIAGRAM
3
PIN ASSIGNMENT
N2:N0
Pulldown
SEL0
VCCO_LVCMOS
1
2
3
4
REF_OUT
VEE
OE_REF
M2
24
23
22
21
Pulldown
SEL1
N0
N1
N2
N
XTAL_IN0
000 ÷2
5
6
7
8
VCCO_LVPECL
20
19
18
17
16
15
14
13
M1
M0
MR
SEL1
001 ÷4
Q
nQ
VEE
OSC
00
01
11
010 ÷5
Q
011 ÷6
XTAL_OUT0
XTAL_IN1
VCCA
9
SEL0
10
01
00
nQ
100 ÷8 (default)
101 ÷10
110 ÷12
111 ÷16
Phase
Detector
10
11
12
CLK
VCO
VCC
XTAL_OUT1
XTAL_IN0
XTAL_OUT0
OSC
XTAL_IN1
XTAL_OUT1
CLK
M
ICS843001I-23
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
000 ÷44
10
11
Pulldown
001 ÷45
010 ÷48
011 ÷50
100 ÷51
G Package
Top View
111 ÷64 (default)
Pulldown
Pullup
MR
3
M2:M0
REF_OUT
Pulldown
OE_REF
The Preliminary Information presented herein represents a product in pre-production.The noted characteristics are based on initial product characterization
and/or qualification.Integrated DeviceTechnology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT™ / ICS™ 3.3V LVPECL/ LVCMOS FREQUENCY SYNTHESIZER
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ICS843001BGI-23 REV. B FEBRUARY 19, 2009
ICS843001I-23
FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-3.3V LVPECL/LVCMOS SYNTHESIZER
PRELIMINARY
TABLE 1. PIN DESCRIPTIONS
Number
Name
VCCO_CMOS
N0, N1
N2
Type
Description
1
2, 3
4
Power
Input
Output supply pin for LVCMOS/LVTTL REF_OUT output.
Pulldown
Output divider select pins. See Table 3C.
LVCMOS/LVTTL interface levels.
Input
Pullup
5
VCCO_LVPECL
Q, nQ
VEE
Power
Ouput
Power
Power
Power
Output supply pin for LVPECL output.
Differential output pair. LVPECL interface levels.
Negative supply pin.
6, 7
8, 23
9
VCCA
Analog supply pin.
10
VCC
Core supply pin.
11
12
13
14
XTAL_OUT1,
XTAL_IN1
XTAL_OUT0,
XTAL_IN0
Parallel resonant crystal interface. XTAL_OUT1 is the output,
XTAL_IN1 is the input.
Parallel resonant crystal interface. XTAL_OUT0 is the output,
XTAL_IN0 is the input.
Input
Input
15
CLK
Input
Input
Pulldown LVCMOS/LVTTL clock input.
16, 17
SEL0, SEL1
Pulldown Input MUX select pins. LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the true output Q to go low and the inverted output nQ to
go high. When logic LOW, the internal dividers and the outputs are
enabled. LVCMOS/LVTTL interface levels.
Feedback divider select pins. See Table 3B.
LVCMOS/LVTTL interface levels.
18
MR
Input
Input
Pulldown
19, 20 , 21 M0, M1, M2
Pullup
Reference clock output enable. Default Low. See Table 3E.
LVCMOS/LVTTL interface levels.
22
24
OE_REF
Input
Pulldown
REF_OUT
Output
Reference clock output. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum Units
CIN
Input Capacitance
4
pF
Power Dissipation
Capacitance
CPD
pF
RPULLDOWN Input Pulldown Resistor
51
51
20
kΩ
kΩ
Ω
RPULLUP
Rout
Input Pullup Resistor
Output Impedance
REF_OUT
IDT™ / ICS™ 3.3V LVPECL/ LVCMOS FREQUENCY SYNTHESIZER
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ICS843001BGI-23 REV. B FEBRUARY 19, 2009
ICS843001I-23
FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-3.3V LVPECL/LVCMOS SYNTHESIZER
PRELIMINARY
TABLE 3A. COMMON CONFIGURATIONS TABLE
Input
Feedback
Divider
Output Frequency
(MHz)
VCO (MHz)
N Divider Value
Application
XTAL Input (MHz)
27
24.75
19.44
19.44
19.44
25
44
48
64
64
64
50
50
50
50
50
45
48
48
48
51
51
51
1188
1188
16
16
8
74.25
74.25
155.52
622.08
311.04
125
HDTV
HDTV
1244.16
1244.16
1244.16
1250
SONET
2
SONET
4
SONET
10
8
GigE
25
1250
156.25
250
10 GigE
25
1250
5
GigE
25
1250
4
312.5
625
XGMII
25
1250
2
10 GigE
25
1125
6
187.5
100
12 GigE
25
1200
12
8
PCI Express
SATA
25
1200
150
25
1200
16
12
8
75
SATA
25
1275
106.25
159.375
212.5
Fibre Channel
10 Gig Fibre Channel
4 Gig Fibre Channel
25
1275
25
1275
6
TABLE 3C. PROGRAMMABLE N OUTPUT DIVIDER
FUNCTION TABLE
TABLE 3B. PROGRAMMABLE M OUTPUT DIVIDER
FUNCTION TABLE
Inputs
Inputs
Input Frequency
M Divider
Value
N Divide Value
N2
0
N1
0
N0
0
M2
0
M1
0
M0
0
Minimum Maximum
2
4
44
45
25.5
24.9
23.3
22.4
22.0
17.5
29.54
28.88
27.08
26.0
0
0
1
0
0
1
0
1
0
5
0
1
0
48
0
1
1
6
0
1
1
50
1
0
0
8
(default)
10
12
16
1
0
0
51
25.49
20.31
1
0
1
1
1
1
64 (default)
1
1
0
1
1
1
TABLE 3D. BYPASS MODE FUNCTION TABLE
Inputs
TABLE 3E. OE_REF OUTPUT FUNCTION TABLE
Inputs
Output
REF_OUT
Hi-Z
Reference Input
PLL Mode
SEL1 SEL0
OE_REF
0
0
1
1
0
1
0
1
XTAL0
XTAL1
CLK
Active
Active
Active
0
1
Active
CLK
Bypass
IDT™ / ICS™ 3.3V LVPECL/ LVCMOS FREQUENCY SYNTHESIZER
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ICS843001BGI-23 REV. B FEBRUARY 19, 2009
ICS843001I-23
FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-3.3V LVPECL/LVCMOS SYNTHESIZER
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
CC
Inputs, V
-0.5V to VCC + 0.5V
I
Outputs, IO (LVPECL)
Continuous Current
Surge Current
50mA
100mA
Outputs, VO (LVCMOS)
-0.5V to VCCO_LVCMOS + 0.5V
Package Thermal Impedance, θ
82.3°C/W (0 mps)
-65°C to 150°C
JA
Storage Temperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO_LVPECL, VCCO_LVCMOS = 3.3V 5ꢀ, VEE = 0V, TA = -40°C TO 85°C
Symbol
VCC
Parameter
Test Conditions
Minimum Typical
Maximum Units
Core Supply Voltage
Analog Supply Voltage
3.135
VCC – 0.05
3.135
3.3
3.3
3.3
3.3
105
5
3.465
VCC
V
V
VCCA
VCCO_LVPECL Output Supply Voltage
VCCO_LVCMOS Output Supply Voltage
3.465
3.465
V
3.135
V
IEE
Power Supply Current
Analog Supply Current
Output Supply Current
mA
mA
mA
ICCA
ICCO
5
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V 5ꢀ, VCCO_LVPECL, VCCO_LVCMOS = 2.5V 5ꢀ, VEE = 0V, TA = -40°C TO 85°C
Symbol
VCC
Parameter
Test Conditions
Minimum
3.135
Typical Maximum Units
Core Supply Voltage
Analog Supply Voltage
3.3
3.3
2.5
2.5
105
5
3.465
VCC
V
V
VCCA
VCC – 0.05
2.375
VCCO_LVPECL Output Supply Voltage
VCCO_LVCMOS Output Supply Voltage
2.625
2.625
V
2.375
V
IEE
Power Supply Current
Analog Supply Current
Output Supply Current
mA
mA
mA
ICCA
ICCO
5
TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO_LVPECL, VCCO_LVCMOS = 2.5V 5ꢀ, VEE = 0V, TA = -40°C TO 85°C
Symbol
VCC
Parameter
Test Conditions
Minimum
2.375
Typical Maximum Units
Core Supply Voltage
Analog Supply Voltage
2.5
2.5
2.5
2.5
100
5
2.625
VCC
V
V
VCCA
VCC – 0.05
2.375
VCCO_LVPECL Output Supply Voltage
VCCO_LVCMOS Output Supply Voltage
2.625
2.625
V
2.375
V
IEE
Power Supply Current
Analog Supply Current
Output Supply Current
mA
mA
mA
ICCA
ICCO
5
IDT™ / ICS™ 3.3V LVPECL/ LVCMOS FREQUENCY SYNTHESIZER
4
ICS843001BGI-23 REV. B FEBRUARY 19, 2009
ICS843001I-23
FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-3.3V LVPECL/LVCMOS SYNTHESIZER
PRELIMINARY
TABLE 4D. LVCMOS / LVTTL DC CHARACTERISTICS, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VCC = 3.3V
2
VCC + 0.3
VCC + 0.3
0.8
V
V
V
V
VIH
VIL
Input High Voltage
V
CC = 2.5V
1.7
-0.3
-0.3
VCC = 3.3V
VCC = 2.5V
Input Low Voltage
0.7
VCC = VIN = 3.465V
CLK, SEL0, SEL1,
OE_REF, MR, N0, N1
150
5
µA
µA
µA
or 2.625V
VCC = VIN = 3.465V
Input
High Current
IIH
N2, M0:M2
or 2.625V
VCC = 3.465V or 2.625V,
VIN = 0V
CLK, SEL0, SEL1,
OE_REF, MR, N0, N1
-5
Input
Low Current
IIL
V
CC = 3.465V or 2.625V,
IN = 0V
VCCO_LVCMOS = 3.465V
CCO_LVCMOS = 2.625V
N2, M0:M2
REF_OUT
REF_OUT
-150
µA
V
2.6
1.8
V
V
Output High
Voltage; NOTE 1
VOH
V
VCCO_LVCMOS = 3.465V
or 2.625V
Output Low
Voltage; NOTE 1
VOL
0.5
V
ΔV/ΔT
Input Edge Rate CLK
20ꢀ - 80ꢀ
TBD
V/ns
NOTE 1: Output terminated with 50Ω to VCCO _LVCMOS/2. See Parameter Measurement Information Section,
"Output Load Test Circuit Diagram" diagrams.
TABLE 4E. LVPECL DC CHARACTERISTICS, VCC = VCCO_LVPECL = 3.3V 5ꢀ, VEE = 0V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
VCCO_LVPECL - 1.4
VCCO_LVPECL - 2.0
0.6
Typical
Maximum
VCCO_LVPECL - 0.9
VCCO_LVPECL - 1.7
1.0
Units
VOH
Output High Voltage; NOTE 1
V
V
V
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50Ω to VCCO_LVPECL - 2V.
TABLE 4F. LVPECL DC CHARACTERISTICS, VCC = 3.3V±±5% o%ꢀ.±V±±5ꢁ%VCCO_LVPECL = 2.5V 5ꢀ, VEE = 0V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
VCCO_LVPECL - 1.4
VCCO_LVPECL - 2.0
0.4
Typical
Maximum
VCCO_LVPECL - 0.9
VCCO_LVPECL - 1.5
1.0
Units
VOH
Output High Voltage; NOTE 1
V
V
V
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50Ω to VCCO_LVPECL - 2V.
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Typical Maximum Units
Mode of Oscillation
Fundamental
MHz
MHz
Ω
Frequency
17.5
29.54
Equivalent Series Resistance (ESR)
Shunt Capacitance
50
7
pF
Drive Level
1
mW
NOTE: Characterized using an 18pF parallel resonant crystal.
IDT™ / ICS™ 3.3V LVPECL/ LVCMOS FREQUENCY SYNTHESIZER
5
ICS843001BGI-23 REV. B FEBRUARY 19, 2009
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FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-3.3V LVPECL/LVCMOS SYNTHESIZER
PRELIMINARY
TABLE 6A. AC CHARACTERISTICS, VCC = VCCO_LVPECL, VCCO_LVCMOS = 3.3V 5ꢀ, VEE = 0V, TA = -40°C TO 85°C
Symbol Parameter
fOUT Output Frequency
tPD
Test Conditions
Minimum Typical Maximum Units
56
650
MHz
Propagation
Delay, NOTE 1
CLK to
REF_OUT
2.5
0.9
ns
RMS Phase Jitter, (Random);
NOTE 2, 3
tjit(Ø)
622.08MHz (12kHz - 20MHz)
ps
fVCO
PLL VCO Lock Range
Select Time
1.12
1.3
GHz
ms
ms
ps
tL_SEL
tL_M
PLL Lock Time
Q/nQ
20ꢀ to 80ꢀ
20ꢀ to 80ꢀ
300
500
50
Output
tR / tF
odc
Rise/Fall Time
REF_OUT
Q/nQ
ps
ꢀ
Output Duty Cycle
REF_OUT
50
ꢀ
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established
when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet
specifications after thermal equilibrium has been reached under these conditions.
NOTE 1: Measured from the VCC/2 of the input to VCCO_LVCMOS/2 of the output.
NOTE 2: Phase jitter measured using a 19.44MHz quartz crystal.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 6B. AC CHARACTERISTICS, VCC = 3.3V 5ꢀ, VCCO_LVPECL, VCCO_LVCMOS = 2.5V 5ꢀ, VEE = 0V, TA = -40°C TO 85°C
Symbol Parameter
fOUT Output Frequency
tPD
Test Conditions
Minimum Typical Maximum Units
56
650
MHz
Propagation
Delay, NOTE 1
CLK to
REF_OUT
3.5
1
ns
RMS Phase Jitter, (Random);
NOTE 2, 3
tjit(Ø)
622.08MHz (12kHz - 20MHz)
ps
fVCO
PLL VCO Lock Range
Select Time
1.12
1.3
GHz
ms
ms
ps
tL_SEL
tL_M
PLL Lock Time
Q/nQ
20ꢀ to 80ꢀ
20ꢀ to 80ꢀ
300
500
50
Output
tR / tF
odc
Rise/Fall Time
REF_OUT
Q/nQ
ps
ꢀ
Output Duty Cycle
REF_OUT
50
ꢀ
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established
when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet
specifications after thermal equilibrium has been reached under these conditions.
NOTE 1: Measured from the VCC/2 of the input to VCCO_LVCMOS/2 of the output.
NOTE 2: Phase jitter measured using a 19.44MHz quartz crystal.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
IDT™ / ICS™ 3.3V LVPECL/ LVCMOS FREQUENCY SYNTHESIZER
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ICS843001BGI-23 REV. B FEBRUARY 19, 2009
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FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-3.3V LVPECL/LVCMOS SYNTHESIZER
PRELIMINARY
TABLE 6C. AC CHARACTERISTICS, VCC = VCCO_LVPECL, VCCO_LVCMOS = 2.5V 5ꢀ, VEE = 0V, TA = -40°C TO 85°C
Symbol Parameter
fOUT Output Frequency
tPD
Test Conditions
Minimum Typical Maximum Units
56
650
MHz
Propagation
Delay, NOTE 1
CLK to
REF_OUT
3
ns
RMS Phase Jitter, (Random);
NOTE 2, 3
tjit(Ø)
622.08MHz (12kHz - 20MHz)
1.1
ps
fVCO
PLL VCO Lock Range
Select Time
1.12
1.3
GHz
ms
ms
ps
tL_SEL
tL_M
PLL Lock Time
Q/nQ
20ꢀ to 80ꢀ
20ꢀ to 80ꢀ
300
500
50
Output
tR / tF
odc
Rise/Fall Time
REF_OUT
Q/nQ
ps
ꢀ
Output Duty Cycle
REF_OUT
50
ꢀ
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established
when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet
specifications after thermal equilibrium has been reached under these conditions.
NOTE 1: Measured from the VCC/2 of the input to VCCO_LVCMOS/2 of the output.
NOTE 2: Phase jitter measured using a 19.44MHz quartz crystal.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
IDT™ / ICS™ 3.3V LVPECL/ LVCMOS FREQUENCY SYNTHESIZER
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FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-3.3V LVPECL/LVCMOS SYNTHESIZER
PRELIMINARY
PARAMETER MEASUREMENT INFORMATION
1.65V 5ꢀ
2V
1.65V 5ꢀ
2V
SCOPE
,
VCC
SCOPE
VCCO_LVCMOS
,
VCC
VCCO_LVPECL
Qx
VCCA
Qx
VCCA
LVCMOS
GND
LVPECL
nQx
VEE
-1.65V 5ꢀ
-1.3V 0.165V
3.3V LVPECL OUTPUT LOAD AC TEST CIRCUIT
3.3V LVCMOS OUTPUT LOAD AC TEST CIRCUIT
2.8V 0.04V
2V
2.05V 5ꢀ
1.25V 5ꢀ
2.8V 0.04V
2.05V 5ꢀ
VCC
VCC
SCOPE
SCOPE
Qx
VCCO_LVPECL
VCCO_LVCMOS
VCCA
Qx
VCCA
LVCMOS
GND
LVPECL
nQx
VEE
-1.25V 5ꢀ
-0.5V 0.125V
3.3V CORE/2.5V LVPECL OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/2.5V LVCMOS OUTPUT LOAD AC TEST CIRCUIT
1.25V 5ꢀ
1.25V 5ꢀ
2V
2V
SCOPE
,
VCC
SCOPE
VCCO_LVCMOS
,
VCC
VCCO_LVPECL
Qx
VCCA
Qx
VCCA
LVCMOS
GND
LVPECL
nQx
VEE
-1.25V 5ꢀ
-0.5V 0.125V
2.5V LVPECL OUTPUT LOAD AC TEST CIRCUIT
2.5V LVCMOS OUTPUT LOAD AC TEST CIRCUIT
IDT™ / ICS™ 3.3V LVPECL/ LVCMOS FREQUENCY SYNTHESIZER
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FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-3.3V LVPECL/LVCMOS SYNTHESIZER
PRELIMINARY
Phase Noise Plot
nQ
Q
Phase Noise Mask
tPW
tPERIOD
tPW
Offset Frequency
f1
f2
odc =
x 100ꢀ
tPERIOD
RMS Jitter = Area Under the Masked Phase Noise Plot
LVPECL OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
RMS PHASE JITTER
nQ
VCCO_LVCMOS
2
80ꢀ
tF
80ꢀ
tR
REF_OUT
VSWING
20ꢀ
tPW
20ꢀ
tPERIOD
Q,
REF_OUT
tPW
odc =
x 100ꢀ
tPERIOD
OUTPUT RISE/FALL TIME
LVCMOS OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
VCC
2
CLK
VCCO_LVCMOS
REF_OUT
2
t
PD
PROPAGATION DELAY
IDT™ / ICS™ 3.3V LVPECL/ LVCMOS FREQUENCY SYNTHESIZER
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ICS843001BGI-23 REV. B FEBRUARY 19, 2009
ICS843001I-23
FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-3.3V LVPECL/LVCMOS SYNTHESIZER
PRELIMINARY
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter perfor-
mance, power supply isolation is required. The ICS843001I-23
provides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VCC, VCCA, and VCCO_X
should be individually connected to the power supply
plane through vias, and 0.01µF bypass capacitors should be used
for each pin. Figure 1 illustrates this for a generic VCC pin and
also shows that VCCA requires that an additional10Ω resistor
3.3V or 2.5V
VCC
.01μF
.01μF
10Ω
VCCA
10μF
FIGURE 1. POWER SUPPLY FILTERING
along with a 10µF bypass capacitor be connected to the VCCA pin.
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
LVCMOS OUTPUT
CRYSTAL INPUTS
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1kΩ resistor can be tied
from XTAL_IN to ground.
The unused LVCMOS output can be left floating. There should
be no trace attached.
LVPECL OUTPUT
The unused LVPECL output pair can be left floating. We
recommend that there is no trace attached. Both sides of the
differential output pair should either be left floating or terminated.
CLK INPUT
For applications not requiring the use of a clock input, it can be
left floating. Though not required, but for additional protection, a
1kΩ resistor can be tied from the CLK input to ground.
LVCMOS CONTROL PINS
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
IDT™ / ICS™ 3.3V LVPECL/ LVCMOS FREQUENCY SYNTHESIZER
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ICS843001BGI-23 REV. B FEBRUARY 19, 2009
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FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-3.3V LVPECL/LVCMOS SYNTHESIZER
PRELIMINARY
CRYSTAL INPUT INTERFACE
The ICS843001I-23 has been characterized with 18pF
parallel resonant crystals. The capacitor values shown in
Figure 2 below were determined using an 18pF parallel
resonant crystal and were chosen to minimize the ppm error.
XTAL_IN
C1
22p
X1
18pF Parallel Cry stal
XTAL_OUT
C2
22p
FIGURE 2. CRYSTAL INPUT INTERFACE
LVCMOS TO XTAL INTERFACE
series resistance (Rs) equals the transmission line impedance.
In addition, matched termination at the crystal input will
attenuate the signal in half. This can be done in one of two
ways. First, R1 and R2 in parallel should equal the transmission
line impedance. For most 50Ω applications, R1 and R2 can be
100Ω. This can also be accomplished by removing R1 and
making R2 50Ω.
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram
is shown in Figure 3. The XTAL_OUT pin can be left floating.
The input edge rate can be as slow as 10ns. For LVCMOS
signals, it is recommended that the amplitude be reduced from
full swing to half swing in order to prevent signal interference
with the power rail and to reduce noise. This configuration
requires that the output impedance of the driver (Ro) plus the
VDD
VDD
R1
.1uf
Ro
Rs
Zo = 50
XTAL_IN
R2
Zo = Ro + Rs
XTAL_OUT
FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
IDT™ / ICS™ 3.3V LVPECL/ LVCMOS FREQUENCY SYNTHESIZER
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ICS843001BGI-23 REV. B FEBRUARY 19, 2009
ICS843001I-23
FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-3.3V LVPECL/LVCMOS SYNTHESIZER
PRELIMINARY
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
drive 50Ω transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion. Figures 4A and 4B show two different layouts
which are recommended only as guidelines. Other suitable
clock layouts may exist and it would be recommended that the
board designers simulate to guarantee compatibility across all
printed circuit and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, termi-
nating resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
3.3V
Zo = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
((VOH + VOL) / (VCC – 2)) – 2
84Ω
84Ω
FIGURE 4A. LVPECL OUTPUT TERMINATION
FIGURE 4B. LVPECL OUTPUT TERMINATION
IDT™ / ICS™ 3.3V LVPECL/ LVCMOS FREQUENCY SYNTHESIZER
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ICS843001I-23
FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-3.3V LVPECL/LVCMOS SYNTHESIZER
PRELIMINARY
TERMINATION FOR 2.5V LVPECL OUTPUTS
Figure 5A and Figure 5B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminating
50Ω to V - 2V. For V = 2.5V, the V - 2V is very close to ground
level. The R3 in Figure 5B can be eliminated and the termination
is shown in Figure 5C.
CC
CC
CC
2.5V
VCC=2.5V
2.5V
2.5V
VCC=2.5V
Zo = 50 Ohm
R1
R3
250
250
+
Zo = 50 Ohm
Zo = 50 Ohm
+
-
Zo = 50 Ohm
-
2,5V LVPECL
Driv er
R1
50
R2
50
2,5V LVPECL
Driv er
R2
62.5
R4
62.5
R3
18
FIGURE 5A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 5B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V
VCC=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
-
2,5V LVPECL
Driv er
R1
50
R2
50
FIGURE 5C. 2.5V LVPECL TERMINATION EXAMPLE
IDT™ / ICS™ 3.3V LVPECL/ LVCMOS FREQUENCY SYNTHESIZER
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ICS843001BGI-23 REV. B FEBRUARY 19, 2009
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FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-3.3V LVPECL/LVCMOS SYNTHESIZER
PRELIMINARY
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843001I-23.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843001I-23 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V = 3.3V + 5ꢀ = 3.465V, which gives worst case results.
CC
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core) = V
* I
= 3.465V * 105mA = 363.8mW
EE_MAX
MAX
CC_MAX
Power (outputs) = 30mW/Loaded Output pair
MAX
Total Power
(3.465V, with all outputs switching) = 363.8mW + 30mW = 393.8mW
_MAX
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
TM
device. The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air
flow and a multi-layer board, the appropriate value is 82.3°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.394W * 82.3°C/W = 117.4°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (multi-layer).
TABLE 7. THERMAL RESISTANCE θ FOR 24-PIN TSSOP, FORCED CONVECTION
JA
θ by Velocity (Meters per Second)
JA
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
82.3°C/W
78.0°C/W
75.9°C/W
IDT™ / ICS™ 3.3V LVPECL/ LVCMOS FREQUENCY SYNTHESIZER
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ICS843001BGI-23 REV. B FEBRUARY 19, 2009
ICS843001I-23
FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-3.3V LVPECL/LVCMOS SYNTHESIZER
PRELIMINARY
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 6
VCCO
Q1
VOUT
RL
50
VCCO - 2V
FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CCO
•
•
For logic high, V = V
= V
– 0.9V
OUT
OH_MAX
CCO_MAX
)
= 0.9V
OH_MAX
(V
- V
CCO_MAX
For logic low, V = V
= V
– 1.7V
OUT
OL_MAX
CCO_MAX
)
= 1.7V
OL_MAX
(V
- V
CCO_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
- V
/R ] * (V
- V
) =
OH_MAX
CCO_MAX
CCO_MAX
OH_MAX
_MAX
OH_MAX
CCO_MAX
OH_MAX
L
CCO
L
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
/R ] * (V
- V
) =
OL_MAX
CCO_MAX
CCO_MAX
OL_MAX
_MAX
CCO
OL_MAX
CCO_MAX
OL_MAX
L
L
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
IDT™ / ICS™ 3.3V LVPECL/ LVCMOS FREQUENCY SYNTHESIZER
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ICS843001BGI-23 REV. B FEBRUARY 19, 2009
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FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-3.3V LVPECL/LVCMOS SYNTHESIZER
PRELIMINARY
RELIABILITY INFORMATION
TABLE 8. θ VS. AIR FLOW TABLE FOR 24 LEAD TSSOP
JA
θ by Velocity (Meters per Second)
JA
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
82.3°C/W
78.0°C/W
75.9°C/W
TRANSISTOR COUNT
The transistor count for ICS843001I-23 is: 4165
PACKAGE OUTLINE AND DIMENSIONS
PACKAGE OUTLINE - G SUFFIX FOR 24 LEAD TSSOP
TABLE 9. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum
Maximum
N
A
24
--
1.20
0.15
1.05
0.30
0.20
7.90
A1
A2
b
0.05
0.80
0.19
0.09
7.70
c
D
E
6.40 BASIC
E1
e
4.30
4.50
0.65 BASIC
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
IDT™ / ICS™ 3.3V LVPECL/ LVCMOS FREQUENCY SYNTHESIZER
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FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-3.3V LVPECL/LVCMOS SYNTHESIZER
PRELIMINARY
TABLE 10. ORDERING INFORMATION
Part/Order Number
843001BGI-23
Marking
Package
Shipping Packaging
tube
Temperature
ICS843001BI23
ICS843001BI23
ICS43001BI23L
ICS43001BI23L
24 Lead TSSOP
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
843001BGI-23T
843001BGI-23LF
843001BGI-23LFT
24 Lead TSSOP
2500 tape & reel
tube
24 Lead "Lead-Free" TSSOP
24 Lead "Lead-Free" TSSOP
2500 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and
industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT
reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT™ / ICS™ 3.3V LVPECL/ LVCMOS FREQUENCY SYNTHESIZER
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ICS843001BGI-23 REV. B FEBRUARY 19, 2009
ICS843001I-23
FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO-3.3V LVPECL/LVCMOS FANOUT BUFFER
PRELIMINARY
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800-345-7015 (inside USA)
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www.IDT.com/go/contactIDT
United States
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
© 2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks
of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be
trademarks or registered trademarks used to identify products or services of their respective owners.
Printed in USA
相关型号：
ICS843001BGI-23T
Clock Generator, 650MHz, PDSO24, 4.40 X 7.80 MM, 0.92 MM HEIGHT, MO-153, TSSOP-24
IDT
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