ICS8431AM-01LFT [IDT]
Clock Generator, 200MHz, PDSO28, SOIC-28;
| 型号： | ICS8431AM-01LFT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, 200MHz, PDSO28, SOIC-28 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总7页 (文件大小：96K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8431-01
CLOCK SYNTHESIZER
GENERAL DESCRIPTION
FEATURES
The ICS8431-01 is a general purpose clock • Fully integrated PLL
,&6
frequency synthesizer and a member of the
• Differential 3.3V LVPECLoutput
• 200MHz output frequency
HiPerClockS™ HiPerClockS™ family of High Performance
Clock Solutions from ICS. The ICS8431-01
consists of one independent low bandwidth PLL
• Crystal oscillator interface
timing channel. A 16.666MHz crystal is used as the input to
the on-chip oscillator. The M and N dividers are configured to
produce a fixed output frequency of 200MHz.
• Spread Spectrum Clocking (SSC) fixed at 1/2% modulation
for environments requiring ultra low EMI
Programmable features of the ICS8431-01 support four op-
erational modes. The four modes are spread spectrum clock-
ing (SSC), non-spread spectrum clock and two test modes
and are controlled by the Power Up Latch. After power up
the latch is disabled and the initial programmed values can
only be overwritten by removing all power to the device.
• LVTTL/ LVCMOS control inputs
• PLL bypass modes supporting in-circuit testing and on-chip
functional block characterization
• 28 lead SOIC
In SSC mode the output clock is modulated in order to achieve
a reduction in EMI. In one of the PLL bypass test modes the
PLL is disconnected as the source to the differential output
allowing an external source to be connnected to the
TEST_I/O pin. This is useful for in-circuit testing and allows
the differential output to be driven at a lower frequency
throughout the system clock tree. In the other PLL bypass
mode the oscillator divider is used as the source to both the
M and N dividers. In this configuration the frequency at FOUT,
nFOUT equals the crystal frequency divide by 16 divided by
N. The frequency at TEST I/O equals the crystal frequency
divide by 16 divided by M. This is useful for characterizing
the oscillator and internal dividers.
BLOCK DIAGRAM
PIN ASSIGNMENT
XTAL1
OSC
XTAL2
nc
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
nc
nc
nc
nc
nc
nc
2
3
4
5
6
7
VDDI
XTAL2
XTAL1
nc
nc
VDDA
nc
nc
nc
VDDO
FOUT
nFOUT
GND
÷ 16
PLL
nc
PHASE
DETECTOR
nc
nc
8
9
VCO
SSC_CTL0
SSC_CTL1
GNDT
TEST_I/O
VDDT
10
11
12
13
14
÷ N
FOUT
nFOUT
÷ M
TEST_I/O
ICS8431-01
SSC_CTL0
SSC_CTL1
Power
Up
Latch
28-Lead SOIC
M Package
Top View
Configuration Logic
8431-01
www.icst.com
SEPTEMBER 13, 2000
1
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8431-01
CLOCK SYNTHESIZER
CONFIGURATION PROGRAMMING INTERFACE
Programming the Spread Spectrum Clocking (SSC) feature is accomplished by configuring the internal PUL register. The input to
this register is encoded by the SSC_CTL[1:0] pins which define all functional states after power is applied. Figure 1 shows the timing
relationship of the latched SSC_CTL[1:0] in relationship to the PLL power-on condition.
VDD = 0V
VDD = 3.3V
VDD Power On
SSC_CTL[1:0]
t = 100µs
Data Valid
TPUL_SU
TPUL_HD
FIGURE 1. POWER-UP CONFIGURATION TIMING
After power is applied, the control bits SSC_CTL0 and SSC_CTL1 are latched after approximately 100µs. TPUL_SU is the time
during which the data on the control bits is required to be valid before being latched. TPUL_HD is the time after the data is latched that
the control bits are required to remain valid. The configuration latch can only be overwritten by removing the power and applying data
to the inputs that meet the setup and hold time requirment during power-on, as defined in Figure 1. Table 3, Input Function Table
defined the valid commands for SSC_CTL[1:0] lines.
8431-01
www.icst.com
SEPTEMBER 13, 2000
2
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8431-01
CLOCK SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1 -9, 19,
20, 21, 23,
24, 28
nc
Unused
No connection.
These LVCMOS / LVTTL pins are sampled during power-up to configure the
SSC control. After power-up inputs have no effect on the latched configuration
register.
SSC CTL 0,
SSC CTL 1
10, 11
Input
Pullup
12
13
GNDT
Power
Ground pin for core and test output.
Input /
Output
TEST I/O
Programmed asdefined in Table 3, Function Table.
14
15
VDDT
GND
Power
Power
Power supply pin for test output.
Ground pin for output.
These differential outputs are main output drivers for the synthesizer. They are
compatible with terminated positive referenced LVPECL logic.
16, 17
nFOUT, FOUT
Output
18
22
27
VDDO
VDDA
VDDI
Power
Power
Power
Power supply pin for output.
PLL power supply pin.
Power supply pin for core.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum
Typical
51
Maximum Units
RPULLUP
Input Pullup Resistor
KΩ
KΩ
RPULLDOWN Input Pulldown Resistor
51
TABLE 3. FUNCTION TABLE
Inputs
Outputs
FOUT, nFOUT TEST_I/O
Disabled fXTAL ÷ 16 ÷ N fXTAL ÷ 16 ÷ M
TEST_I/O
Source
Operational Modes
SSC
SSC_CTL1 SSC_CTL0
PLL bypass; Oscillator, oscillator, M and N
dividers test mode. NOTE 1
0
0
Internal
0
1
1
1
0
1
PLL
External
PLL
Enabled
Disabled
Disabled
200MHz
Test Clk
200MHz
Hi-Z
Input
Hi-Z
Default SSC; Modulation Factor = ½ Percent
PLL Bypass Mode, (1MHz ≤ Test Clk ≤ 200MHz)
No SSC Modulation
NOTE 1: Used for in house debug and characterization.
8431-01
www.icst.com
SEPTEMBER 13, 2000
3
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8431-01
CLOCK SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
4.6V
Inputs
Outputs
-0.5V to VDD + 0.5V
-0.5V to VDDO + 0.5V
0°C to 70°C
Ambient Operating Temperature
Storage Temperature
-65°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only and functional operation of product at these condition or any conditions beyond those listed in the DC Electrical
Characteristics or AC Electrical Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect product reliability.
TABLE 4A. LVTTL, LVCMOS DC ELECTRICAL CHARACTERISTICS, VDDA, VDDI=VDDO=VDDT=3.3V±5%, TA=0°C TO 70°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum Units
VDDA, VDDI,
VDDO, VDDT
Power Supply Voltage
3.135
3.3
3.465
V
SSC_CTL0, SSC_CTL1
TEST_I/O
VDDI = 3.465V
VDDI = 3.465V
2
2
3.765
3.765
0.8
V
V
VIH
Input High Voltage
SSC_CTL0, SSC_CTL1
TEST_I/O
VDDI = 3.135V
-0.3
V
VIL
IIH
IIL
Input Low Voltage
Input High
VDDI = 3.135V
1.3
V
SSC_CTL0, SSC_CTL1
TEST_I/O
VDDI = VIN = 3.465V
VDDI = VIN = 3.465V
50
µA
µA
µA
µA
Current
50
SSC_CTL0, SSC_CTL1 VDDI = 3.465V, VIN = 0V
TEST_I/O VDDI = 3.465V, VIN = 0V
-150
-50
Input Low Current
TABLE 4B. LVPECL DC ELECTRICAL CHARACTERISTICS, VDDA, VDDI=VDDO=VDDT=3.3V±5%, TA=0°C TO 70°C
Symbol
VOH
Parameter
Test Conditions
VDDI = VDDO = 3.3V
VDDI = VDDO = 3.3V
Minimum
Typical
Maximum
Units
V
Output High Voltage; NOTE 1, 2
Output Low Voltage; NOTE 1, 2
Common Mode Voltage Range
Output High Current
2.1
1.4
600
16
2.2
1.5
800
18
VOL
V
VSWING
IOH
700
mV
mA
mA
IOL
Output Low Current
2
4
NOTE 1: These values are for VDDO equal to 3.3V. Output levels will vary 1:1 with VDDO.
NOTE 2: Output terminated with 50Ω to VDDO - 2V.
8431-01
www.icst.com
SEPTEMBER 13, 2000
4
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8431-01
CLOCK SYNTHESIZER
TABLE 5. AC ELECTRICAL CHARACTERISTICS, VDDI=VDDO=3.3V±5%, TA=0°C TO 70°C
Symbol
tPERIOD
tjit
Parameter
Test Conditions
fout = 200MHz
fout = 200MHz
fout = 200MHz
20% to 80%
Minimum
Typical
Maximum Units
Output Period; NOTE 1
Peak Jitter (Short Cycle); NOTE 1
Output Duty Cycle; NOTE 1
Output Rise Time
4995
5005
50
ps
ps
tDC
47
300
300
14
53
%
tR
800
800
18
ps
tF
Output Fall Time
20% to 80%
ps
Fxtal
Crystal Input Range
MHz
KHz
%
Fm
SSC Modulation Frequency
SSC Modulation Factor
Power-up to Stable Clock Output
Configuration Latch Setup Time
Configuration Latch Hold Time
30
33.33
Fmf
0.5
tSTABLE
tPUL_SU
tPUL_HD
TBD
µs
10
0
ns
ns
NOTE 1: Spread spectrum clocking enabled
8431-01
www.icst.com
SEPTEMBER 13, 2000
5
Integrated
Circuit
Systems, Inc.
ICS8431-01
CLOCK SYNTHESIZER
PACKAGE OUTLINE AND DIMENSIONS - M SUFFIX
8431-01
www.icst.com
SEPTEMBER 13, 2000
6
Integrated
Circuit
Systems, Inc.
ICS8431-01
CLOCK SYNTHESIZER
ORDERING INFORMATION
Part/Order Number
Marking
Package
28 Lead SOIC
Count
Temperature
0°C to 70°C
0°C to 70°C
ICS8431AM-01
ICS8431AM-01
ICS8431AM-01
ICS8431AM-01T
28 LeadSOIC on Tape and Reel
8431-01
www.icst.com
SEPTEMBER 13, 2000
7
相关型号：
ICS8431CM-01LFT
Clock Generator, 200MHz, PDSO28, 7.5 X 18.05 MM, 2.25 MM HEIGHT, MS-013, MO-119, SOIC-28
IDT
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