ICS843251AGI-04 [IDT]
Clock Generator, 187.5MHz, PDSO8, 4.40 X 3 MM, 0.925 MM HEIGHT, MO-153, TSSOP-8;
| 型号： | ICS843251AGI-04 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, 187.5MHz, PDSO8, 4.40 X 3 MM, 0.925 MM HEIGHT, MO-153, TSSOP-8 光电二极管 |
| 文件： | 总11页 (文件大小：575K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
FEMTOCLOCKS™ CRYSTAL-TO-
3.3V LVPECL CLOCK GENERATOR
ICS843251I-04
GENERAL DESCRIPTION
FEATURES
The ICS843251I-04 is a 10Gb/12Gb Ethernet Clock
• One differential 3.3V LVPECL output
ICS
HiPerClockS™
Generator and a member of the HiPerClocksTM family
of high performance devices from IDT. The
ICS843251I-04 can synthesize 10 Gigabit Ethernet
and 12 Gigabit Ethernet with a 25MHz crystal. It
• Crystal oscillator interface designed for
18pF parallel resonant crystals
• Crystal input frequency range: 19.33MHz - 30MHz
• Output frequency range: 145MHz - 187.5MHz
• VCO frequency range: 580MHz - 750MHz
can also generate SATA and 10Gb Fibre Channel reference
clock frequencies with the appropriate choice of crystals. The
ICS843251I-04 has excellent phase jitter performance and is
packaged in a small 8-pin TSSOP, making it ideal for use in
systems with limited board space.
• RMS phase jitter at 156.25MHz (1.875MHz - 20MHz):
0.39ps (typical)
• 3.3V operating supply
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
CONFIGURATION TABLE WITH 25MHZ CRYSTAL
Inputs
Output Frequency
Application
Crystal Frequency Feedback VCO Frequency
(MHz)
N Output Divide
(MHz)
Divide
(MHz)
25
30
750
4
4
187.5
12 Gigabit Ethernet
10 Gigabit Ethernet
25
25
625
156.25
CONFIGURATION TABLE WITH SELECTABLE CRYSTALS
Inputs
Output Frequency
(MHz)
Application
Crystal Frequency Feedback VCO Frequency
N Output Divide
(MHz)
Divide
(MHz)
20
30
600
4
4
4
4
4
150
159.375
150
SATA
21.25
24
30
637.5
600
10 Gigabit Fibre Channel
SATA
25
25.5
30
25
637.5
750
159.375
187.5
10 Gigabit Fibre Channel
12 Gigabit Ethernet
25
BLOCK DIAGRAM
PIN ASSIGNMENT
VCCA
VCC
1
2
3
4
8
7
6
5
XTAL_IN
OSC
XTAL_OUT
DIV. N
÷4
nQ
Q
VEE
Q
Phase
Detector
VCO
580MHz-750MHz
XTAL_OUT
XTAL_IN
nQ
FREQ_SEL
0 = ÷25 (default)
1 = ÷30
ICS843251I-04
8-Lead TSSOP
4.40mm x 3.0mm x 0.925mm
package body
Pulldown
FREQ_SEL
G Package
Top View
The Preliminary Information presented herein represents a product in pre-production.The noted characteristics are based on initial product characterization
and/or qualification.Integrated DeviceTechnology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT™ / ICS™ 3.3V LVPECL CLOCK GENERATOR
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843251AGI-04 REV A OCTOBER 23, 2006
ICS843251I-04
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
PRELIMINARY
TABLE 1. PIN DESCRIPTIONS
Number
Name
VCCA
VEE
Type
Description
1
2
Power
Power
Analog supply pin.
Negative supply pin.
3,
4
XTAL_OUT,
XTAL_IN
Crystal oscillator interface. XTAL_IN is the input,
XTAL_OUT is the output.
Input
5
6, 7
8
FREQ_SEL
nQ, Q
Input
Output
Power
Pulldown Frequency select pin. LVCMOS/LVTTL interface levels.
Differential clock outputs. LVPECL interface levels.
Core supply pin.
VCC
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characterristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum Units
Input Capacitance
Input Pulldown Resistor
4
pF
RPULLDOWN
51
kΩ
IDT™ / ICS™ 3.3V LVPECL CLOCK GENERATOR
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ICS843251I-04
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
CC
Inputs, V
-0.5V to VCC + 0.5V
I
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, θJA 101.7°C/W (0 mps)
Storage Temperature, T -65°C to 150°C
STG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VCC
VCCA
ICC
Core Supply Voltage
3.465
3.465
V
Analog Supply Voltage
Power Supply Current
Analog Supply Current
Power Supply Current
3.135
3.3
V
TBD
TBD
TBD
mA
mA
mA
ICCA
IEE
TABLE 3B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
VIL
IIH
Input High Voltage FREQ_SEL
2
VCC + 0.3
0.8
V
V
Input Low Voltage FREQ_SEL
Input High Current FREQ_SEL
Input Low Current FREQ_SEL
-0.3
VCC = VIN = 3.465V
150
µA
µA
IIL
VCC = 3.465V, VIN = 0V
-5
TABLE 3C. LVPECL DC CHARACTERISTICS, VCC = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VOH
Output High Voltage; NOTE 1
VCC - 1.4
VCC - 2.0
0.6
VCC - 0.9
VCC - 1.7
1.0
V
V
V
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
IDT™ / ICS™ 3.3V LVPECL CLOCK GENERATOR
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ICS843251I-04
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
PRELIMINARY
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Typical Maximum Units
Fundamental
Mode of Oscillation
Frequency
19.33
30
50
7
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
pF
1
mW
TABLE 5. AC CHARACTERISTICS, VCC = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fOUT
Output Frequency
145
187.5
MHz
156.25MHz @ Integration Range:
1.875MHz - 20MHz
159.375MHz @ Integration Range:
1.875MHz - 20MHz
187.5MHz @ Integration Range:
1.875MHz - 20MHz
0.39
TBD
0.48
ps
RMS Phase Jitter (Random);
NOTE 1
tjit(Ø)
ps
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ
340
50
ps
ꢀ
NOTE 1: Please refer to the Phase Noise Plots following this section.
IDT™ / ICS™ 3.3V LVPECL CLOCK GENERATOR
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ICS843251I-04
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
PRELIMINARY
PARAMETER MEASUREMENT INFORMATION
2V
Phase Noise Plot
SCOPE
VCC
Qx
Phase Noise Mask
LVPECL
nQx
VEE
Offset Frequency
f1
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
-1.3V 0.165V
3.3V OUTPUT LOAD AC TEST CIRCUIT
RMS PHASE JITTER
nQ
80ꢀ
tF
80ꢀ
tR
Q
VSWING
20ꢀ
tPW
Clock
Outputs
tPERIOD
20ꢀ
tPW
odc =
x 100ꢀ
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
OUTPUT RISE/FALL TIME
IDT™ / ICS™ 3.3V LVPECL CLOCK GENERATOR
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ICS843251I-04
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
PRELIMINARY
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS843251-04 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VCC, and VCCA should
be individually connected to the power supply plane through
vias, and bypass capacitors should be used for each pin. To
achieve optimum jitter performance, power supply isolation is
required. Figure 1 illustrates how a 10Ω resistor along with a
10µF and a .01µF bypass capacitor should be connected to
each VCCA pin.
3.3V
VCC
.01µF
.01µF
10Ω
VCCA
10µF
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS843251-04 has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 2 below were determined using a 25MHz, 18pF parallel
resonant crystal and were chosen to minimize the ppm error.
The optimum C1 and C2 values can be slightly adjusted for
different board layouts.
XTAL_OUT
XTAL_IN
C1
33p
X1
18pF Parallel Crystal
C2
27p
Figure 2. CRYSTAL INPUt INTERFACE
IDT™ / ICS™ 3.3V LVPECL CLOCK GENERATOR
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FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
PRELIMINARY
LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 3. The XTAL_OUT pin can be left floating. The
input edge rate can be as slow as 10ns. For LVCMOS inputs, it is
recommended that the amplitude be reduced from full swing to
half swing in order to prevent signal interference with the power
rail and to reduce noise.This configuration requires that the output
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination
at the crystal input will attenuate the signal in half. This can be
done in one of two ways. First, R1 and R2 in parallel should equal
the transmission line impedance. For most 50Ω applications, R1
and R2 can be 100Ω.This can also be accomplished by removing
R1 and making R2 50Ω.
VDD
VDD
R1
.1uf
Ro
Rs
Zo = 50
XTAL_IN
R2
Zo = Ro + Rs
XTAL_OUT
FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
drive 50Ω transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion. Figures 4A and 4B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, termi-
nating resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
3.3V
Z
o = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
84Ω
84Ω
((VOH + VOL) / (VCC – 2)) – 2
FIGURE 4A. LVPECL OUTPUT TERMINATION
FIGURE 4B. LVPECL OUTPUT TERMINATION
IDT™ / ICS™ 3.3V LVPECL CLOCK GENERATOR
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ICS843251I-04
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
PRELIMINARY
RELIABILITY INFORMATION
TABLE 6. θ VS. AIR FLOW TABLE FOR 8 LEAD TSSOP
JA
θ by Velocity (Meters per Second)
JA
0
1
2.5
89.8°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
101.7°C/W
90.5°C/W
TRANSISTOR COUNT
The transistor count for ICS843251-04 is: 1891
IDT™ / ICS™ 3.3V LVPECL CLOCK GENERATOR
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FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
PRELIMINARY
PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP
TABLE 7. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum
Maximum
N
A
8
--
1.20
0.15
1.05
0.30
0.20
3.10
A1
A2
b
0.05
0.80
0.19
0.09
2.90
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document:JEDEC Publication 95, MO-153
IDT™ / ICS™ 3.3V LVPECL CLOCK GENERATOR
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ICS843251I-04
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
PRELIMINARY
TABLE 8. ORDERING INFORMATION
Part/Order Number
ICS843251AGI-04
Marking
1AI04
1AI04
AI04L
AI04L
Package
Shipping Packaging
tube
Temperature
8 Lead TSSOP
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
ICS843251AGI-04T
ICS843251AGI-04LF
ICS843251AGI-04LFT
8 Lead TSSOP
2500 tape & reel
tube
8 Lead "Lead-Free" TSSOP
8 Lead "Lead-Free" TSSOP
2500 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and
industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT
reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT™ / ICS™ 3.3V LVPECL CLOCK GENERATOR
10
843251AGI-04 REV A OCTOBER 23, 2006
ICS843251I-04
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
PRELIMINARY
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www.IDT.com
For Sales
800-345-7015
408-284-8200
Fax: 408-284-2775
For Tech Support
netcom@idt.com
480-763-2056
Corporate Headquarters
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
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Integrated Device Technology
Singapore (1997) Pte. Ltd.
Reg. No. 199707558G
435 Orchard Road
Europe
IDT Europe, Limited
321 Kingston Road
Leatherhead, Surrey
KT22 7TU
United States
800 345 7015
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Singapore 238877
+44 (0) 1372 363 339
Fax: +44 (0) 1372 378851
+65 6 887 5505
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks
of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be
trademarks or registered trademarks used to identify products or services of their respective owners.
Printed in USA
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