ICS8432DY-01T [IDT]
Clock Generator, 700MHz, PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, LQFP-32;
| 型号： | ICS8432DY-01T |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, 700MHz, PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, LQFP-32 时钟 外围集成电路 晶体 |
| 文件： | 总18页 (文件大小：173K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS8432-01
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL
LVPECLFREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Incꢀ
GENERAL DESCRIPTION
FEATURES
The ICS8432-01 is a general purpose, dual output • Dual differential 3.3V LVPECLoutputs
Crystal-to-3.3V Differential LVPECL High Fre-
quency Synthesizer and a member of the
HiPerClockS™ family of High Performance Clock
Solutions from ICS. The ICS8432-01 has a select-
• Selectable crystal oscillator interface or
LVCMOSTEST_CLK
HiPerClockS™
• Output frequency range: 25MHz to 700MHz
• Crystal input frequency range: 14MHz to 25MHz
• VCO range: 200MHz to 700MHz
able TEST_CLK or crystal inputs. The VCO operates at a
frequency range of 200MHz to 700MHz. The VCO frequency
is programmed in steps equal to the value of the input refer-
ence or crystal frequency. The VCO and output frequency
can be programmed using the serial or parallel interfaces to
the configuration logic. The low phase noise characteristics
of the ICS8432-01 make it an ideal clock source for Gigabit
Ethernet, Fiber Channel 1 and 2, and Infiniband applications.
• Parallel or serial interface for programming counter
and output dividers
• RMS period jitter: 4ps (maximum)
• Cycle-to-cycle jitter: 25ps (maximum)
• 3.3V supply voltage
• 0°C to 70°C ambient operating temperature
BLOCK DIAGRAM
PIN ASSIGNMENT
VCO_SEL
XTAL_SEL
TEST_CLK
0
32 31 30 29 28 27 26 25
XTAL1
1
M5
OSC
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
XTAL1
XTAL2
M6
M7
M8
N0
N1
nc
TEST_CLK
XTAL_SEL
VCCA
ICS8432-01
S_LOAD
S_DATA
S_CLOCK
MR
PLL
PHASE DETECTOR
MR
0
1
VEE
VCO
FOUT0
nFOUT0
FOUT1
nFOUT1
÷ N
9
10 11 12 13 14 15 16
÷ M
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
CONFIGURATION
INTERFACE
LOGIC
TEST
32-Lead LQFP
7mm x 7mm x 1.4mm package body
M0:M8
N0:N1
Y Package
Top View
8432DY-01
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REV. B JUNE 18, 2002
1
ICS8432-01
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL
LVPECLFREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Incꢀ
FUNCTIONAL DESCRIPTION
NOTE: The functional description that follows describes operation using a 25MHz crystal. Valid PLL loop divider values for
different crystal or input frequencies are defined in the Input Frequency Characteristics, Table 5, NOTE 1.
The ICS8432-01 features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth.
A fundamental crystal is used as the input to the on-chip oscillator. The output of the oscillator is fed into the phase detector.
A 25MHz crystal provides a 25MHz phase detector reference frequency. The VCO of the PLL operates over a range of
200MHz to 700MHz. The output of the M divider is also applied to the phase detector.
The phase detector and the M divider force the VCO output frequency to be M times the reference frequency by adjusting the
VCO control voltage. Note that for some values of M (either too high or too low), the PLL will not achieve lock. The output of the
VCO is scaled by a divider prior to being sent to each of the LVPECL output buffers. The divider provides a 50% output duty cycle.
The programmable features of the ICS8432-01 support two input modes, programmable M divider and N output divider. The
two input operational modes are parallel and serial. Figure 1 shows the timing diagram for each mode. In parallel mode, the
nP_LOAD input is initially LOW. The data on inputs M0 through M8 and N0 and N1 is passed directly to the M divider and
N output divider. On the LOW-to-HIGH transition of the nP_LOAD input, the data is latched and the M divider remains loaded
until the next LOW transition on nP_LOAD or until a serial event occurs. As a result, the M and N bits can be hardwired to set
the M divider and N output divider to a specific default state that will automatically occur during power-up. The TEST output is
LOW when operating in the parallel input mode. The relationship between the VCO frequency, the crystal frequency and the
M divider is defined as follows:
fVCO = fxtal x M
The M value and the required values of M0 through M8 are shown in Table 3B, Programmable VCO Frequency Function Table.
Valid M values for which the PLL will achieve lock for a 25MHz reference are defined as 8 ≤ M ≤ 28. The frequency out is
defined as follows:
FOUT = fVCO = fxtal x M
N
N
Serial operation occurs when nP_LOAD is HIGH and S_LOAD is LOW. The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the shift register are loaded into the M divider and N output divider when
S_LOAD transitions from LOW-to-HIGH. The M divide and N output divide values are latched on the HIGH-to-LOW transition
of S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is passed directly to the M divider and N output divider on each
rising edge of S_CLOCK. The serial mode can be used to program the M and N bits and test bits T1 and T0. The internal
registers T0 and T1 determine the state of the TEST output as follows:
T1 T0
TEST Output
LOW
0
0
1
1
0
1
0
1
S_Data
Output of M divider
CMOS Fout
S
ERIAL LOADING
S_DATA
S_CLOCK
S_LOAD
T 1
t
T0
*
NULL N1
N0
M8
M7
M6
M5
M4 M3
M2
M1
M0
t
S
H
t
M0:M8, N0:N1
nP_LOAD
S
P
ARALLEL LOADING
M, N
t
t
H
Time
FIGURE 1 - PARALLEL & SERIAL LOAD OPERATIONS
S
*NOTE: The NULL timing slot must be observed.
8432DY-01
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REV. B JUNE 18, 2002
2
ICS8432-01
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL
LVPECLFREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Incꢀ
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Pullup
Description
1
M5
Input
Input
M divider inputs. Data latched on LOW-to-HIGH transition of
nP_LOAD input. LVCMOS / LVTTL interface levels.
2, 3, 4,
28, 29,
30, 31, 32
M6, M7, M8,
M0, M1,
M2, M3, M4
Pulldown
Pulldown
Determines output divider value as defined in Table 3C,
Function Table. LVCMOS / LVTTL interface levels.
5, 6
N0, N1
Input
7
nc
Unused
Power
No connect.
8, 16
VEE
Negative supply pins.
Test output which is ACTIVE in the serial mode of operation.
Output driven LOW in parallel mode. LVCMOS interface levels.
9
TEST
VCC
Output
Power
Output
Power
Output
10
Positive supply pin.
Differential output for the synthesizer.
3.3V LVPECL interface levels.
11, 12
13
FOUT1, nFOUT1
VCCO
Output supply pin.
Differential output for the synthesizer.
3.3V LVPECL interface levels.
14, 15
FOUT0, nFOUT0
Master reset. Forces outputs LOW, but does not effect loaded
M, N, and T values. LVCMOS / LVTTL interface levels.
Clocks in serial data present at S_DATA input into the shift register
on the rising edge of S_CLOCK.
Shift register serial input. Data sampled on the rising edge of
S_CLOCK.
17
18
19
MR
Input
Input
Input
Pulldown
Pulldown
Pulldown
Pulldown
S_CLOCK
S_DATA
Controls transition of data from shift register into the dividers.
LVCMOS / LVTTL interface levels.
20
21
S_LOAD
VCCA
Input
Power
Analog supply pin.
Selects between crystal or test inputs as the PLL reference
source. LVCMOS / LVTTL interface levels. Selects XTAL inputs
when HIGH. Selects TEST_CLK when LOW.
22
XTAL_SEL
Input
Pullup
23
TEST_CLK
Input
Input
Pulldown Test clock input. LVCMOS / LVTTL interface levels.
Crystal oscillator inputs.
24, 25
XTAL1, XTAL2
Parallel load input. Determines when data present at M8:M0 is
Pulldown loaded into M divider, and when data present at N1:N0 sets the
N output divider value. LVCMOS / LVTTL interface levels.
26
27
nP_LOAD
VCO_SEL
Input
Input
Determines whether synthesizer is in PLL or bypass mode.
Pullup
LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum Typical Maximum Units
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
4
pF
KΩ
KΩ
RPULLUP
RPULLDOWN
51
51
8432DY-01
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REV. B JUNE 18, 2002
3
ICS8432-01
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL
LVPECLFREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Incꢀ
TABLE 3A. PARALLEL AND SERIAL MODE FUNCTION TABLE
Inputs
Conditions
MR nP_LOAD
M
N
S_LOAD S_CLOCK S_DATA
H
X
X
X
X
X
X
Reset. Forces outputs LOW.
Data on M and N inputs passed directly to the M
divider and N output divider. TEST output forced LOW.
L
L
Data Data
Data Data
X
X
X
Data is latched into input registers and remains loaded
until next LOW transition or until a serial event occurs.
Serial input mode. Shift register is loaded with data on
S_DATA on each rising edge of S_CLOCK.
Contents of the shift register are passed to the
M divider and N output divider.
L
L
L
↑
L
L
↑
X
↑
X
H
H
X
X
X
X
Data
Data
L
L
L
L
H
H
H
X
X
X
X
X
X
↓
L
L
X
↑
Data
X
M divider and N output divider values are latched.
Parallel or serial input do not affect shift registers.
S_DATA passed directly to M divider as it is clocked.
H
Data
NOTE: L = LOW
H = HIGH
X = Don't care
↑ = Rising edge transition
↓ = Falling edge transition
TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE
256
M8
0
128
M7
0
64
M6
0
32
M5
0
16
M4
0
8
M3
1
4
M2
0
2
M1
0
1
M0
0
VCO Frequency
(MHz)
M Divide
200
225
250
275
•
8
9
0
0
0
0
0
1
0
0
1
10
11
•
0
0
0
0
0
1
0
1
0
0
0
0
0
0
1
0
1
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
650
675
700
26
27
28
0
0
0
0
1
1
0
1
0
0
0
0
0
1
1
0
1
1
0
0
0
0
1
1
1
0
0
NOTE 1: These M divide values and the resulting frequencies correspond to crystal or TEST_CLK input frequency of
25MHz.
TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE
Inputs
Output Frequency (MHz)
N Divider Value
N1
0
N0
0
Minimum
Maximum
700
1
2
4
8
200
100
50
0
1
350
1
0
175
1
1
25
87.5
8432DY-01
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REV. B JUNE 18, 2002
4
ICS8432-01
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL
LVPECLFREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Incꢀ
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCCX
Inputs, VCC
Outputs, VCCO
4.6V
-0.5V to VCC + 0.5 V
-0.5V to VCCO + 0.5V
Package Thermal Impedance, θJA 47.9°C/W (0 lfpm)
Storage Temperature, TSTG -65°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC
Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
VCC
Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
Positive Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
3.465
3.465
3.465
110
V
V
VCCA
VCCO
IEE
3.135
3.3
3.135
3.3
V
mA
mA
ICCA
15
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VCO_SEL, XTAL_SEL, MR,
S_LOAD, nP_LOAD, N0:N1,
S_DATA, S_CLOCK, M0:M8
2
VCC + 0.3
V
V
Input
VIH
High Voltage
TEST_CLK
2
VCC + 0.3
VCO_SEL, XTAL_SEL, MR,
S_LOAD, nP_LOAD, N0:N1,
S_DATA, S_CLOCK, M0:M8
-0.3
-0.3
0.8
V
Input
VIL
Low Voltage
TEST_CLK
1.3
V
M0-M4, M6-M8, N0, N1, MR,
S_CLOCK, TEST_CLK,
S_DATA, S_LOAD, nP_LOAD
V
CC = VIN = 3.465V
150
µA
Input
IIH
High Current
M5, XTAL_SEL, VCO_SEL
VCC = VIN = 3.465V
VCC = 3.465V,
5
µA
µA
M0-M4, M6-M8, N0, N1, MR,
S_CLOCK, TEST_CLK,
S_DATA, S_LOAD, nP_LOAD
-5
VIN = 0V
Input
IIL
Low Current
VCC = 3.465V,
VIN = 0V
M5, XTAL_SEL, VCO_SEL
TEST; NOTE 1
-150
2.6
µA
V
Output
VOH
High Voltage
Output
VOL
TEST; NOTE 1
0.5
V
Low Voltage
NOTE 1: Outputs terminated with 50Ω to VCCO/2.
8432DY-01
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REV. B JUNE 18, 2002
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ICS8432-01
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL
LVPECLFREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Incꢀ
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VOH
Output High Voltage; NOTE 1
VCCO - 1.4
VCCO - 2.0
0.6
VCCO - 1.0
VCCO - 1.7
1.0
V
V
V
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50 Ω to VCCO - 2V. See "Parameter Measurement Information" section,
figure "3.3V Output Load Test Circuit".
TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
TEST_CLK; NOTE 1
14
14
25
25
50
MHz
MHz
MHz
fIN
Input Frequency XTAL1, XTAL2; NOTE 1
S_CLOCK
NOTE 1: For the input crystal and TEST_CLK frequency range, the M value must be set for the VCO to operate within the
200MHz to 700MHz range. Using the minimum input frequency of 14MHz, valid values of M are 15 ≤ M ≤ 50. Using the
maximum frequency of 25MHz, valid values of M are 8 ≤ M ≤ 28.
TABLE 6. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum Typical Maximum
Units
Mode of Oscillation
Frequency
Fundamental
14
25
70
7
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
pF
TABLE 7. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
FOUT
tjit(cc)
tjit(per)
tsk(o)
tR
Output Frequency
25
700
25
MHz
ps
ps
ps
ps
ps
ns
ns
ns
ns
ns
ns
%
Cycle-to-Cycle Jitter; NOTE 1, 3
Period Jitter, RMS; NOTE 1
Output Skew; NOTE 2, 3
Output Rise Time
fVCO > 350MHz
fOUT > 100MHz
4
15
20% to 80%
20% to 80%
200
700
700
tF
Output Fall Time
200
M, N to nP_LOAD
5
tS
Setup Time S_DATA to S_CLOCK
S_CLOCK to S_LOAD
M, N to nP_LOAD
5
5
5
tH
Hold Time
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
5
5
48
odc
tPW
Output Duty Cycle
Output Pulse Width
PLL Lock Time
N > 1
N = 1
52
tPERIOD/2 - 150
tPERIOD/2 + 150
1
ps
ms
tLOCK
See Parameter Measurement Information section.
NOTE 1: Jitter performance using XTAL inputs.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
8432DY-01
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REV. B JUNE 18, 2002
6
ICS8432-01
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL
LVPECLFREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Incꢀ
PARAMETER MEASUREMENT INFORMATION
VCC, VCCA, VCCO
SCOPE
Qx
LVPECL
VCC, VCCA, VCCO = 2V
nQx
VEE = -1.3V ± 0.135V
3.3V OUTPUT LOAD TEST CIRCUIT
nFOUTx
FOUTx
nFOUTy
FOUTy
tsk(o)
OUTPUT SKEW
80%
80%
VSWING
20%
20%
Clock Inputs
and Outputs
tR
tF
INPUT AND OUTPUT RISE AND FALL TIME
8432DY-01
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REV. B JUNE 18, 2002
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ICS8432-01
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL
LVPECLFREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Incꢀ
nFOUTx
TEST, FOUTx
Pulse Width
tPERIOD
tPW
tPERIOD
odc =
odc, tPW & tPERIOD
VOH
V
ref
VOL
1σ contains 68.26% of all measurements
2σ contains 95.4% of all measurements
3σ contains 99.73% of all measurements
4σ contains 99.99366% of all measurements
6σ contains (100-1.973x10-7)% of all measurements
Histogram
Reference Point
(Trigger Edge)
Mean Period
(First edge after trigger)
Period Jitter
nFOUTx
FOUTx
➤
➤
tcycle n+1
tcycle n
➤
➤
tjit(cc) = tcycle n –tcycle n+1
1000 Cycles
Cycle-to-Cycle Jitter
8432DY-01
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REV. B JUNE 18, 2002
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ICS8432-01
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL
LVPECLFREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Incꢀ
APPLICATIONS
STORAGE AREA NETWORKS
Avariety of technologies are used for interconnection of the elements within a SAN. The tables below list the common application
frequencies as well as the ICS8432-01 configurations used to generate the appropriate frequency.
Table 8. Common SANs Applications Frequencies
Reference Frequency to SERDES
(MHz)
Crystal Frequency
(MHz)
Interconnect Technology
Gigabit Ethernet
Fibre Channel
Clock Rate
1.25 GHz
125, 250, 156.25
106.25, 53.125, 132.8125
125, 250
25, 19.53125
16.6015625, 25
25
FC1 1.0625 GHz
FC2 2.1250 GHz
Infiniband
2.5 GHz
Table 9. Configuration Details for SANs Applications
ICS8432-01
ICS8432-01
Interconnect
Technology
Crystal Frequency
(MHz)
Output Frequency
to SERDES
(MHz)
M & N Settings
M8 M7 M6 M5 M4 M3 M2 M1 M0 N1 N0
25
125
250
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
1
1
1
0
1
1
0
1
1
0
0
1
0
0
0
0
0
0
1
1
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
0
0
0
1
0
1
1
1
1
1
1
0
0
1
0
0
1
0
0
0
1
25
Gigabit Ethernet
25
156.25
156.25
53.125
106.25
132.8125
125
19.53125
25
Fiber Channel 1
Fiber Channel 2
Infiniband
25
16.6015625
25
25
250
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS8432-01 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VCC, VCCA, and VCCO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 2 illustrates how
a 10Ω resistor along with a 10µF and a .01µF bypass
capacitor should be connected to each VCCA pin.
3.3V
VCC
.01µF
.01µF
10Ω
VCCA
10 µF
FIGURE 2 - POWER SUPPLY FILTERING
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8432DY-01
REV. B JUNE 18, 2002
9
ICS8432-01
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL
LVPECLFREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Incꢀ
CRYSTAL INPUT AND OSCILLATOR INTERFACE
The ICS8432-01 features an internal oscillator that uses an
external quartz crystal as the source of its reference frequency.
The oscillator is a series resonant, multi-vibrator type design. This
design provides better stability and eliminates the need for large
on chip capacitors. Though a series resonant crystal is preferred,
a parallel resonant crystal can be used. A parallel resonant mode
crystal used in a series resonant circuit will exhibit a frequency
of oscillation a few hundred ppm lower than specified. A few
hundred ppm translates to KHz inaccuracy. In general computing
applications, this level of inaccuracy is irrelevant. If better ppm
accuracy is required, an external capacitor can be added to a
parallel resonant crystal in series to pin 24. Figure 3A shows how
to interface with a crystal.
ICS8432-01
XTAL2
(Pin 25, LQFP)
XTAL1
(Pin 24, LQFP)
Optional
Figures 3A, 3B, and 3C show various crystal parameters which
are recommended only as guidelines. Figure 3A shows how to
interface a capacitor with an 18pF parallel resonant crystal. Fig-
ure 3B shows the capacitor value needed for the optimum ppm
performance over various parallel resonant crystal frequencies.
Figure 3C shows the recommended tuning capacitance for
various parallel resonant crystals.
FIGURE 3A - CRYSTAL INTERFACE
FIGURE 3B. Recommended tuning capacitance for various 18pF FIGURE 3C. Recommended tuning capacitance for various 18pF
parallel resonant crystals.
parallel resonant crystals.
60
100
80
60
40
20
0
14.318
50
15.000
40
16.667
19.440
30
20
10
0
20.000
-20
-40
24.000
0
10
20
30
40
50
60
-60
-80
14 15 16 17 18 19 20 21 22 23 24 25
Crystal Frequency (MHz)
-100
19.44MHz
16MHz
Series Capacitor, C1 (pF)
15.00MHz
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ICS8432-01
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL
LVPECLFREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Incꢀ
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termina- drive 50Ω transmission lines. Matched impedance techniques
tion for LVPECL outputs. The two different layouts mentioned should be used to maximize operating frequency and minimize
are recommended only as guidelines.
signal distortion. Figures 4Aand 4B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECLcompatible outputs. Therefore, terminat-
ing resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
3.3V
Zo = 50Ω
5
2
5
Zo
Zo
2
FIN
FOUT
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
➤
VCC - 2V
Zo = 50Ω
RTT
1
3
2
3
2
Zo
RTT =
Zo
Zo
(VOH + VOL / VCC –2) –2
FIGURE 4A - LVPECL OUTPUT TERMINATION
FIGURE 4B - LVPECL OUTPUT TERMINATION
LAYOUT GUIDELINE
The schematic of the ICS8432-01 layout example used in this layout guideline is shown in Figure 5A. The ICS8432-01 recommended
PCB board layout for this example is shown in Figure 5B. This layout example is used as a general guideline. The layout in the actual
system will depend on the selected component types, the density of the components, the density of the traces, and the stacking of
the P.C. board.
X1
R7
VCC
U1
10
C11
1
24
23
22
21
20
19
18
17
0.01u
C16
10u
M5
M6
M7
M8
N0
N1
nc
XTAL1
REF_IN
nXTAL_SEL
VCCA
S_LOAD
S_DATA
S_CLOCK
MR
REF_IN
XTAL_SEL
2
3
4
5
6
7
8
S_LOAD
S_DATA
S_CLOCK
MR
VEE
Termination A
Termination
B (Not shown
in the layout)
VCC
8432-01
IN+
R1
R3
125
125
Zo = 50 Ohm
IN+
IN-
IN-
TL1
Zo = 50 Ohm
R2
50
R1
50
C14
0.1u
C15
0.1u
TL2
R2
84
R4
84
R3
50
FIGURE 5A - SCHEMATIC OF RECOMMENDED LAYOUT
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ICS8432-01
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL
LVPECLFREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Incꢀ
• The differential 50Ω output traces should have the
same length.
The following component footprints are used in this layout
example:
• Avoid sharp angles on the clock trace. Sharp angle
turns cause the characteristic impedance to change on
the transmission lines.
All the resistors and capacitors are size 0603.
POWER AND GROUNDING
Place the decoupling capacitors C14 and C15, as close as pos-
sible to the power pins. If space allows, placement of the
decoupling capacitor on the component side is preferred. This
can reduce unwanted inductance between the decoupling ca-
pacitor and the power pin caused by the via.
• Keep the clock traces on the same layer. Whenever pos-
sible, avoid placing vias on the clock traces. Placement
of vias on the traces can affect the trace characteristic
impedance and hence degrade signal integrity.
• To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace
widths between the differential clock trace and the other
signal trace.
Maximize the power and ground pad sizes and number of vias
capacitors. This can reduce the inductance between the power
and ground planes and the component power and ground pins.
The RC filter consisting of R7, C11, and C16 should be placed
as close to the VCCA pin as possible.
• Make sure no other signal traces are routed between the
clock trace pair.
CLOCK TRACES AND TERMINATION
• The matching termination resistors should be located as
close to the receiver input pins as possible.
Poor signal integrity can degrade the system performance or
cause system failure. In synchronous high-speed digital systems,
the clock signal is less tolerant to poor signal integrity than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The shape of the trace and the
trace delay might be restricted by the available space on the board
and the component location. While routing the traces, the clock
signal traces should be routed first and should be locked prior to
routing other signal traces.
CRYSTAL
The crystal X1 should be located as close as possible to the pins
24 (XTAL1) and 25 (XTAL2). The trace length between the X1
and U1 should be kept to a minimum to avoid unwanted parasitic
inductance and capacitance. Other signal traces should not be
routed near the crystal traces.
X1
GND
VCC
VIA
U1
PIN 1
C11
C16
VCCA
R7
Close to the input
pins of the
receiver
R4
R3
TL1N
C15
C14
TL1
R2
R1
TL1, TL2 are 50 Ohm traces and
equal length
FIGURE 5B - PCB BOARD LAYOUT FOR ICS8432-01
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REV. B JUNE 18, 2002
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ICS8432-01
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL
LVPECLFREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Incꢀ
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8432-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8432-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 110mA = 381.2mW
Power (outputs)MAX = 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30.2mW = 60.4mW
Total Power_MAX (3.465V, with all outputs switching) = 381.2mW + 60.4mW = 441.6mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA =Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 10 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.441W * 42.1°C/W = 88.6°C. This is well below the limit of 125°C
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 10. THERMAL RESISTANCE qJA FOR 32-PIN LQFP, FORCED CONVECTION
qJA by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
55.9°C/W
50.1°C/W
47.9°C/W
42.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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ICS8432-01
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL
LVPECLFREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Incꢀ
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 6.
VCCO
Q1
VOUT
R L
50
VCCO - 2V
FIGURE 6 - LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CCO
•
•
For logic high, V = V
= V
– 1.0V
OUT
OH_MAX
CCO_MAX
)
= 1.0V
OH_MAX
(V
- V
CCO_MAX
For logic low, V = V
= V
– 1.7V
OUT
OL_MAX
CCO_MAX
)
= 1.7V
OL_MAX
(V
- V
CCO_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
/R ] * (V
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
- V
) =
OH_MAX
CCO_MAX
CCO_MAX
OH_MAX
CCO_MAX
OH_MAX
CCO_MAX
OH_MAX
L
L
[(2V - 1V)/50Ω) * 1V = 20.0mW
))
/R ] * (V
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
- V
) =
OL_MAX
CCO_MAX
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
L
L
[(2V - 1.7V)/50Ω) * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
8432DY-01
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REV. B JUNE 18, 2002
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ICS8432-01
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL
LVPECLFREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Incꢀ
RELIABILITY INFORMATION
TABLE 11. θJAVS. AIR FLOW TABLE
qJA by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
55.9°C/W
50.1°C/W
47.9°C/W
42.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8432-01 is: 3712
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REV. B JUNE 18, 2002
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ICS8432-01
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL
LVPECLFREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Incꢀ
PACKAGE OUTLINE -Y SUFFIX
TABLE 12. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
--
--
--
1.60
0.15
1.45
0.45
0.20
A1
A2
b
0.05
1.35
0.30
0.09
1.40
0.37
c
--
D
9.00 BASIC
7.00 BASIC
5.60 Ref.
9.00 BASIC
7.00 BASIC
5.60 Ref.
0.80 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0.75
q
--
0
°
7°
ccc
--
--
0.10
Reference Document: JEDEC Publication 95, MS-026
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REV. B JUNE 18, 2002
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ICS8432-01
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL
LVPECLFREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Incꢀ
TABLE 13. ORDERING INFORMATION
Part/Order Number
ICS8432DY-01
Marking
Package
32 Lead LQFP
Count
250 per tray
1000
Temperature
0°C to 70°C
0°C to 70°C
ICS8432DY-01
ICS8432DY-01
ICS8432DY-01T
32 Lead LQFP on Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
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REV. B JUNE 18, 2002
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ICS8432-01
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL
LVPECLFREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Incꢀ
REVISION HISTORY SHEET
Description of Change
Rev
Table
Page
Date
A
T6
T7
6
Crystal Characteristics table, ESR row value updated from 80Ω Max. to 70Ω Max.
1/10/02
AC Characteristics table, Setup Time & Hold Time rows - moved 5ns from
Maximum column to the Minimum column.
A
6
1/29/02
A
B
B
10
6
Added 18pF description to crystal input
2/22/02
6/12/02
6/18/02
T4C
LVPECL Characteristics table, VSWING changed from 0.950V max. to 1.0V max.
Updated Figure 1, Parallel & Serial Load Operations
2
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