ICS84330AM-01 [IDT]
Clock Generator, 700MHz, PDSO28, 7.50 X 18.05 MM, 2.25 MM HEIGHT, MS-013, MO-119, SOIC-28;
| 型号： | ICS84330AM-01 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, 700MHz, PDSO28, 7.50 X 18.05 MM, 2.25 MM HEIGHT, MS-013, MO-119, SOIC-28 光电二极管 |
| 文件： | 总14页 (文件大小：157K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS84330-01
Integrated
Circuit
Systems, Incꢀ
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
FEATURES
• Fully integrated PLL, no external loop filter requirements
• 1 differential 3.3V LVPECLoutput
The ICS84330-01 is a general purpose, single out-
put high frequency synthesizer and a member of
the HiPerClockS™ family of High Performance Clock
Solutions from ICS. The VCO operates at a fre-
quency range of 200MHz to 700MHz. The VCO
HiPerClockS™
• Crystal oscillator interface: 10MHz to 25MHz
• Output frequency range: 25MHz to 700MHz
• VCO range: 200MHz to 700MHz
and output frequency can be programmed using the serial or
parallel interfaces to the configuration logic. The output can be
configured to divide the VCO frequency by 1, 2, 4, and 8. Out-
put frequency steps from 250KHz to 2MHz can be achieved
using a 16MHz crystal depending on the output divider setting.
• Parallel or serial interface for programming M and N dividers
during power-up
• RMS Period jitter: TBD
• Cycle-to-cycle jitter: 15ps (typical)
• 3.3V supply voltage
• 0°C to 70°C ambient operating temperature
• Pin compatible with the SY89430V
BLOCK DIAGRAM
PIN ASSIGNMENT
M0
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
nP_LOAD
VCC
XTAL2
XTAL1
nc
M1
2
M2
3
M3
4
XTAL1
OSC
XTAL2
M4
5
M5
6
nc
M6
7
VCCA
M7
8
S_LOAD
S_DATA
S_CLOCK
VCCO
M8
9
÷ 16
N0
10
11
12
13
14
N1
VEE
TEST
VCC
FOUT
nFOUT
VEE
PLL
PHASE DETECTOR
1
FOUT
nFOUT
ICS84330-01
VCO
÷ 2
÷ N
28-Lead SOIC
0
÷ M
7.5mm x 18.05mm x 2.25mm body package
M Package
Top View
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
CONFIGURATION
INTERFACE
LOGIC
TEST
M0:M8
N0:N1
25 24 23 22 21 20 19
S_CLOCK
26
18
N1
N0
M8
M7
M6
M5
M4
S_DATA
S_LOAD
27
28
1
17
16
15
14
13
12
ICS84330-01
28-Lead PLCC
V Package
VCCA
nc
2
11.6mm x 11.4mm x 4.1mm
Top View
nc
3
4
XTAL1
5
6
7
8
9 10 11
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
84330AV-01
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 14, 2003
1
PRELIMINARY
ICS84330-01
Integrated
Circuit
Systems, Incꢀ
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
FUNCTIONAL DESCRIPTION
NOTE: The functional description that follows describes operation using a 16MHz crystal. Valid PLL loop divider values for
different crystal or input frequencies are defined in the Input Frequency Characteristics, Table 6, NOTE 1.
The ICS84330-01 features a fully integrated PLL and therefore requires no external components for setting the loop band-
width. A quartz crystal is used as the input to the on-chip oscillator. The output of the oscillator is divided by 16 prior to the
phase detector. With a 16MHz crystal this provides a 1MHz reference frequency. The VCO of the PLL operates over a range
of 200MHz to 700MHz. The output of the M divider is also applied to the phase detector.
The phase detector and the M divider force the VCO output frequency to be 2M times the reference frequency divided by 16 by
adjusting the VCO control voltage. Note that for some values of M (either too high or too low), the PLL will not achieve lock. The
output of the VCO is scaled by a divider prior to being sent to each of the LVPECLoutput buffers. The divider provides a 50% output
duty cycle.
The programmable features of the ICS84330-01 support two input modes to program the M divider and N output divider. The two
input operational modes are parallel and serial. Figure 1 shows the timing diagram for each mode. In parallel mode the nP_LOAD
input is LOW. The data on inputs M0 through M8 and N0 through N1 is passed directly to the M divider and N output divider. On the
LOW-to-HIGH transition of the nP_LOAD input, the data is latched and the M divider remains loaded until the next LOW transition
on nP_LOAD or until a serial event occurs. The TEST output is Mode 000 (shift register out) when operating in the parallel input
mode. The relationship between the VCO frequency, the crystal frequency and the M divider is defined as follows:
fxtal
x
fVCO =
2M
16
The M value and the required values of M0 through M8 are shown in Table 3B, Programmable VCO Frequency Function Table.
Valid M values for which the PLL will achieve lock are defined as 100 ≤ M ≤ 350. The frequency out is defined as follows:
fVCO fxtal 2M
fout
x
=
=
N
N
16
Serial operation occurs when nP_LOAD is HIGH and S_LOAD is LOW. The shift register is loaded by sampling the S_DATAbits
with the rising edge of S_CLOCK. The contents of the shift register are loaded into the M divider when S_LOAD transitions from
LOW-to-HIGH. The M divide and N output divide values are latched on the HIGH-to-LOW transition of S_LOAD. If S_LOAD is held
HIGH, data at the S_DATAinput is passed directly to the M divider on each rising edge of S_CLOCK. The serial mode can be used
to program the M and N bits and test bits T2:T0. The internal registers T2:T0 determine the state of the TEST output as follows:
T2
0
T1
0
T0
0
TEST Output
Shift Register Out
fOUT
fOUT
fOUT
fOUT
fOUT
0
0
0
0
1
1
1
0
1
High
PLL Reference Xtal ÷ 16
(VCO ÷ M) /2 (non 50% Duty M divider)
1
0
0
fOUT
fOUT
LVCMOS Output Frequency < 200MHz
1
1
1
0
1
1
1
0
1
Low
(S_CLOCK ÷ M) /2 (non 50% Duty Cycle M divider)
fOUT ÷ 4
fOUT
S_CLOCK ÷ N divider
fOUT
S
ERIAL LOADING
S_CLOCK
S_DATA
T2
T1
T0
N1
N0
M8
M7
M6
M5
M4 M3
M2
M1
M0
t
t
H
S
S_LOAD
t
nP_LOAD
S
P
ARALLEL LOADING
M, N
M0:M8, N0:N1
nP_LOAD
t
t
H
Time
S
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS
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84330AV-01
REV. A FEBRUARY 14, 2003
2
PRELIMINARY
ICS84330-01
Integrated
Circuit
Systems, Incꢀ
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Name
Type
Description
VCC
Power
Power
Power
Power
Core supply pins.
VCCA
Analog supply pin for the PLL.
Negative supply pins.
VEE
VCCO
Output supply pin.
nc
Unused
Input
Do not connect.
XTAL1, XTAL2
Crystal oscillator interface. XTAL1 is the input. XTAL2 is the output.
Parallel load input. Determines when data present at M8:M0 is loaded into
M divider, and when data present at N1:N0 sets the N output divide value.
LVCMOS / LVTTL interface levels.
nP_LOAD
Input
Pullup
Clocks the serial data present at S_DATA input into the shift register on the
rising edge of S_CLOCK. LVCMOS / LVTTL interface levels.
Shift register serial input. Data sampled on the rising edge of S_CLOCK.
LVCMOS / LVTTL interface levels.
Controls transition of data from shift register into the M divider.
LVCMOS / LVTTL interface levels.
S_CLOCK
S_DATA
Input
Input
Input
Pulldown
Pulldown
Pulldown
S_LOAD
M0, M1, M2
M3, M4, M5
M6, M7, M8
M divider inputs. Data latched on LOW-to-HIGH transition of nP_LOAD input.
LVCMOS / LVTTL interface levels.
Input
Input
Pullup
Pullup
Determines N output divider value as defined in Table 3C Function Table.
LVCMOS / LVTTL interface levels.
N0, N1
Test output which is used in the serial mode of operation.
LVCMOS / LVTTL interface levels.
TEST
Output
Output
nFOUT, FOUT
Differential output for the synthesizer. 3.3V LVPECL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum Typical Maximum Units
Input Capacitance
Input Pullup Resistor
4
pF
KΩ
KΩ
RPULLUP
51
51
RPULLDOWN Input Pulldown Resistor
84330AV-01
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REV. A FEBRUARY 14, 2003
3
PRELIMINARY
ICS84330-01
Integrated
Circuit
Systems, Incꢀ
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
TABLE 3A. PARALLEL AND SERIAL MODE FUNCTION TABLE
Inputs
Conditions
nP_LOAD
M
N
S_LOAD S_CLOCK S_DATA
X
X
X
X
X
X
X
X
X
Reset. M and N bits are all set HIGH.
Data on M and N inputs passed directly to M divider and
N output divider. TEST mode 000.
L
↑
Data Data
Data Data
Data is latched into input registers and remains loaded
until next LOW transition or until a serial event occurs.
Serial input mode. Shift register is loaded with data on
S_DATA on each rising edge of S_CLOCK.
Contents of the shift register are passed to the M divider
and N output divider.
X
L
↑
X
↑
X
H
H
X
X
X
X
Data
Data
L
H
H
H
X
X
X
X
X
X
↓
L
L
X
↑
Data
X
M divide and N output divide values are latched.
Parallel or serial input do not affect shift registers.
S_DATA passed directly to M Divider as it is clocked.
H
Data
NOTE: L = LOW
H = HIGH
X = Don't care
↑ = Rising edge transition
↓ = Falling edge transition
TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE
256
M8
0
128
M7
0
64
M6
1
32
M5
1
16
M4
0
8
M3
0
4
M2
1
2
M1
0
1
M0
0
VCO Frequency
(MHz)
M Divide
200
202
204
206
•
100
101
102
103
•
0
0
1
1
0
0
1
0
1
0
0
1
1
0
0
1
1
0
0
0
1
1
0
0
1
1
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
696
698
700
348
349
350
1
0
1
0
1
1
1
0
0
1
0
1
0
1
1
1
0
1
1
0
1
0
1
1
1
1
0
NOTE 1: These M divide values and the resulting frequencies correspond to a crystal frequency of 16MHz.
TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE
Inputs
Output Frequency (MHz)
N Divider Value
N1
0
N0
0
Minimum
100
Maximum
350
2
4
8
1
0
1
50
175
1
0
25
87.5
1
1
200
700
84330AV-01
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REV. A FEBRUARY 14, 2003
4
PRELIMINARY
ICS84330-01
Integrated
Circuit
Systems, Incꢀ
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
CC
Inputs, V
-0.5V to VCC + 0.5 V
-0.5V to VCCO + 0.5V
I
Outputs, VO
Package Thermal Impedance, θJA 37.8°C/W (0 lfpm)
Storage Temperature, T -65°C to 150°C
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VCC
VCCA
IEE
Core Supply Voltage
3.135
3.135
3.3
3.3
115
15
3.465
3.465
V
Analog Supply Voltage
Power Supply Current
Analog Supply Current
V
mA
mA
ICCA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
2
VCC + 0.3
0.8
V
V
Input Low Voltage
Input High Current
-0.3
M0:M8, N0, N1,
nP_LOAD, XTAL_SEL
S_LOAD, S_DATA,
S_CLOCK
M0:M8, N0, N1,
nP_LOAD, XTAL_SEL
S_LOAD, S_DATA,
S_CLOCK
V
CC = VIN = 3.465V
CC = VIN = 3.465V
5
µA
µA
µA
µA
IIH
V
150
VCC = 3.465V, VIN = 0V
CC = 3.465V, VIN = 0V
-150
IIL
Input Low Current
V
-5
VOH
VOL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
2.6
V
V
0.5
NOTE 1: Outputs terminated with 50Ω to VCCO/2.
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
VOH
Parameter
Test Conditions
Minimum
VCC - 1.4
VCC - 2.0
0.6
Typical Maximum Units
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
VCC - 1.0
VCC - 1.7
0.95
V
V
V
VOL
VSWING
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
84330AV-01
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REV. A FEBRUARY 14, 2003
5
PRELIMINARY
ICS84330-01
Integrated
Circuit
Systems, Incꢀ
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum Typical Maximum
Units
Mode of Oscillation
Frequency
Fundamental
10
25
70
7
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
pF
TABLE 6. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
fIN Input Frequency
Test Conditions
Minimum
Typical
Maximum
Units
MHz
MHz
XTAL; NOTE 1
S_CLOCK
10
25
50
NOTE 1: For the crystal frequency range the M value must be set to achieve the minimum or maximum VCO frequency
range of 200MHz or 700MHz. Using the minimum frequency of 10MHz, valid values of M are 160 ≤ M ≤ 511.
Using the maximum frequency of 25MHz, valid values of M are 64 ≤ M ≤ 224.
TABLE 7. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
FOUT
Output Frequency
700
MHz
ps
ps
ps
ns
ns
ns
ns
ns
ms
%
tjit(per)
tjit(cc)
tR, tF
Period Jitter, RMS; NOTE 1, 2
Cycle-to-Cycle Jitter; NOTE 1, 2
Output Rise/Fall Time
TBD
15
20% to 80%
500
S_DATA to S_CLOCK
20
20
20
20
20
tS
Setup Time
S_CLOCK to S_LOAD
M, N to nP_LOAD
S_DATA to S_CLOCK
M, N to nP_LOAD
tH
Hold Time
tL
PLL Lock Time
10
odc
Output Duty Cycle
50
See Parameter Measurement Information section.
Characterized using a 16MHz XTAL.
NOTE 1: This parameter is defined in accordance with JEDEC Standard 65
NOTE 2: See Applications section.
84330AV-01
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REV. A FEBRUARY 14, 2003
6
PRELIMINARY
ICS84330-01
Integrated
Circuit
Systems, Incꢀ
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
VCC, VCCA, VCCO = 2V
nFOUT
FOUT
SCOPE
Qx
➤
➤
LVPECL
tcycle n
tcycle n+1
➤
➤
nQx
tjit(cc) = tcycle n –tcycle n+1
1000 Cycles
VEE = -1.3V ± 0.165V
3.3V OUTPUT LOAD AC TEST CIRCUIT
CYCLE-TO-CYCLE JITTER
VOH
nFOUT
FOUT
VREF
Pulse Width
VOL
1σ contains 68.26% of all measurements
2σ contains 95.4% of all measurements
tPERIOD
3σ contains 99.73% of all measurements
4σ contains 99.99366% of all measurements
6σ contains (100-1.973x10-7)% of all measurements
tPW
odc =
Histogram
Reference Point
(Trigger Edge)
tPERIOD
Mean Period
(First edge after trigger)
PERIOD JITTER
odc & tPERIOD
80%
80%
VSWING
20%
20%
Clock Outputs
t
t
F
R
OUTPUT RISE/FALL TIME
84330AV-01
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REV. A FEBRUARY 14, 2003
7
PRELIMINARY
ICS84330-01
Integrated
Circuit
Systems, Incꢀ
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS84330-01 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VCC, VCCA and VCCO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 2 illustrates how
a 10Ω resistor along with a 10µF and a .01µF bypass
capacitor should be connected to each VCCA pin.
3.3V
VCC
.01µF
.01µF
10Ω
VCCA
10 µF
FIGURE 2. POWER SUPPLY FILTERING
TERMINATION FOR LVPECL OUTPUTS
drive 50Ω transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion. Figures 3A and 3B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminat-
ing resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
3.3V
Zo = 50Ω
5
2
5
Zo
Zo
2
FIN
FOUT
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
➤
VCC - 2V
RTT
1
3
2
3
2
Zo
RTT =
Zo
Zo
(VOH + VOL / VCC –2) –2
FIGURE 3A. LVPECL OUTPUT TERMINATION
FIGURE 3B. LVPECL OUTPUT TERMINATION
84330AV-01
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REV. A FEBRUARY 14, 2003
8
PRELIMINARY
ICS84330-01
Integrated
Circuit
Systems, Incꢀ
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS84330-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS84330-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 115mA = 398.5mW
Power (outputs)MAX = 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 1 * 30.2mW = 30.2mW
Total Power_MAX (3.465V, with all outputs switching) = 398.5mW + 30.2mW = 428.7mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA =Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 31.1°C/W per Table 8Abelow.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.429W * 31.1°C/W = 83.3°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 8A. THERMAL RESISTANCE qJA FOR 28-PIN PLCC, FORCED CONVECTION
qJA by Velocity (Linear Feet per Minute)
0
200
31.1°C/W
500
28.3°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
37.8°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 8B. THERMAL RESISTANCE qJA FOR 28-PIN SOIC, FORCED CONVECTION
qJA by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
76.2°C/W
46.2°C/W
60.8°C/W
39.7°C/W
53.2°C/W
36.8°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
84330AV-01
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REV. A FEBRUARY 14, 2003
9
PRELIMINARY
ICS84330-01
Integrated
Circuit
Systems, Incꢀ
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in the Figure 4.
VCCO
Q1
VOUT
R L
50
VCCO - 2V
FIGURE 4. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CCO
•
•
For logic high, V = V
= V
– 1.0V
OUT
OH_MAX
CCO_MAX
)
= 1.0V
OH_MAX
(V
- V
CCO_MAX
For logic low, V = V
= V
– 1.7V
OUT
OL_MAX
CCO_MAX
)
= 1.7V
OL_MAX
(V
- V
CCO_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
/R ] * (V
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
- V
) =
OH_MAX
CCO_MAX
CCO_MAX
OH_MAX
_MAX
OH_MAX
CCO_MAX
OH_MAX
L
CCO
L
[(2V - 1V)/50Ω] * 1V = 20.0mW
Pd_L = [(V – (V - 2V))/R ] * (V
))
/R ] * (V
- V
) = [(2V - (V
- V
- V
) =
OL_MAX
CCO_MAX
CCO_MAX
OL_MAX
_MAX
OL_MAX
CCO_MAX
OL_MAX
L
CCO
L
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
84330AV-01
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 14, 2003
10
PRELIMINARY
ICS84330-01
Integrated
Circuit
Systems, Incꢀ
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
RELIABILITY INFORMATION
TABLE 9A. θJAVS. AIR FLOW PLCC TABLE
qJA by Velocity (Linear Feet per Minute)
0
200
500
Multi-Layer PCB, JEDEC Standard Test Boards
37.8°C/W
31.1°C/W
28.3°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 9B. θJAVS. AIR FLOW SOIC TABLE
qJA by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
76.2°C/W
46.2°C/W
60.8°C/W
39.7°C/W
53.2°C/W
36.8°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS84330-01 is: 4442
84330AV-01
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 14, 2003
11
PRELIMINARY
ICS84330-01
Integrated
Circuit
Systems, Incꢀ
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
PACKAGE OUTLINE - V SUFFIX
TABLE 10A. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
SYMBOL
MINIMUM
MAXIMUM
N
A
28
4.19
2.29
4.57
3.05
A1
A2
b
1.57
2.11
0.33
0.53
c
0.19
0.32
D
12.32
11.43
4.85
12.57
11.58
5.56
D1
D2
E
12.32
11.43
4.85
12.57
11.58
5.56
E1
E2
Reference Document: JEDEC Publication 95, MS-018
84330AV-01
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 14, 2003
12
PRELIMINARY
ICS84330-01
Integrated
Circuit
Systems, Incꢀ
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
PACKAGE OUTLINE - M SUFFIX
TABLE 10B. PACKAGE DIMENSIONS
Millimeters
MINIMUM MAXIMUM
SYMBOL
N
A
28
--
2.65
--
A1
A2
B
0.10
2.05
0.33
0.18
17.70
7.40
2.55
0.51
0.32
18.40
7.60
C
D
E
e
1.27 BASIC
H
h
10.00
0.25
0.40
0°
10.65
0.75
1.27
8°
L
α
Reference Document: JEDEC Publication 95, MS-013, MO-119
84330AV-01
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 14, 2003
13
PRELIMINARY
ICS84330-01
Integrated
Circuit
Systems, Incꢀ
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
TABLE 11. ORDERING INFORMATION
Part/Order Number
Marking
Package
Count
38 per Tube
500
Temperature
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
ICS84330AV-01
ICS84330AVT-01
ICS84330AM-01
ICS84330AM-01T
ICS84330AV-01
ICS84330AV-01
ICS84330AM-01
ICS84330AM-01
28 Lead PLCC
28 Lead PLCC on Tape and Reel
28 Lead SOIC
26 per Tube
1000
28 Lead SOIC on Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
84330AV-01
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 14, 2003
14
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