ICS844011AGILF [IDT]
Clock Generator, 113.33MHz, PDSO8, 4.40 X 3 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-8;
| 型号： | ICS844011AGILF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, 113.33MHz, PDSO8, 4.40 X 3 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-8 光电二极管 |
| 文件： | 总10页 (文件大小：152K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS844011I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO- LVDS
CLOCK GENERATOR
GENERAL DESCRIPTION
FEATURES
• One differential LVDS output
The ICS844011I is a Fibre Channel Clock
ICS
HiPerClockS™
Generator and a member of the HiPerClocksTM
family of high performance devices from ICS.
The ICS844011I uses an 18pF parallel resonant
crystal over the range of 20.4MHz - 28.3MHz. For
• Crystal oscillator interface, 18pF parallel resonant crystal
(20.4MHz - 28.3MHz)
• Output frequency range: 81.66MHz - 113.33MHz
• VCO range: 490MHz - 680MHz
Fibre Channel applications, a 26.5625MHz crystal is used.
The ICS844011I has excellent <1ps phase jitter per-
formance, over the 637kHz - 10MHz integration range. The
ICS844011I is packaged in a small 8-pin TSSOP, making it
ideal for use in systems with limited board space.
• RMS phase jitter @ 106.25MHz, using a 26.5625MHz crystal
(637kHz - 10MHz): 0.75ps (typical)
• 3.3V or 2.5V operating supply
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS compliant
packages
COMMON CONFIGURATION TABLE - FIBRE CHANNEL
Inputs
Output Frequency
(MHz)
Multiplication
Value M/N
Crystal Frequency (MHz)
M
N
26.5625
25
24
24
6
6
4
4
106.25
100
BLOCK DIAGRAM
PIN ASSIGNMENT
Pullup
OE
VDDA
GND
VDD
Q
1
2
3
4
8
7
6
5
XTAL_OUT
XTAL_IN
nQ
OE
XTAL_IN
OSC
XTAL_OUT
Q
VCO
Phase
Detector
N = ÷6 (fixed)
490MHz - 680MHz
nQ
ICS844011I
8-Lead TSSOP
4.40mm x 3.0mm x 0.925mm
package body
M = ÷24 (fixed)
G Package
TopView
The Preliminary Information presented herein represents a product in prototyping or pre-production.The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
844011AGI
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REV.A APRIL 18, 2006
1
PRELIMINARY
ICS844011I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO- LVDS
CLOCK GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number
Name
VDDA
Type
Power
Description
1
2
Analog supply pin.
Power supply ground.
GND
Power
Input
XTAL_OUT,
XTAL_IN
Crystal oscillator interface. XTAL_IN is the input,
XTAL_OUT is the output.
Output enable pin. When HIGH, Q/nQ output is active. When LOW, the Q/nQ
output is in a high impedance state. LVCMOS/LVTTL interface levels.
3, 4
5
OE
Input
Pullup
6, 7
8
nQ, Q
VDD
Output
Power
Differential clock outputs. LVDS interface levels.
Core supply pin.
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum
Typical Maximum Units
CIN
Input Capacitance
Input Pullup Resistor
4
pF
RPULLUP
51
kΩ
844011AGI
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REV.A APRIL 18, 2006
2
PRELIMINARY
ICS844011I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO- LVDS
CLOCK GENERATOR
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
DD
Inputs, V
-0.5V to VDD + 0.5 V
I
Outputs, IO (LVDS)
Continuous Current
Surge Current
10mA
15mA
PackageThermal Impedance, θ
101.7°C/W (0 mps)
-65°C to 150°C
JA
StorageTemperature, T
STG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VDD
VDDA
IDD
Core Supply Voltage
3.465
3.465
V
Analog Supply Voltage
Power Supply Current
Analog Supply Current
3.135
3.3
V
TBD
TBD
mA
mA
IDDA
TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
2.375
Typical
2.5
Maximum Units
VDD
VDDA
IDD
Core Supply Voltage
2.625
2.625
V
Analog Supply Voltage
Power Supply Current
Analog Supply Current
2.375
2.5
V
TBD
TBD
mA
mA
IDDA
TABLE 3C. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V 5ꢀ OR 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
DD = 3.3V
VDD = 2.5V
DD = 3.3V
V
2
VDD + 0.3
VDD + 0.3
0.8
V
V
VIH
VIL
Input High Voltage
1.7
-0.3
-0.3
V
V
Input Low Voltage
VDD = 2.5V
0.7
V
IIH
IIL
Input High Current OE
Input Low Current OE
VDD = VIN = 3.465V or 2.625V
VDD = 3.465V or 2.625V, VIN = 0V
5
µA
µA
-150
844011AGI
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REV.A APRIL 18, 2006
3
PRELIMINARY
ICS844011I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO- LVDS
CLOCK GENERATOR
TABLE 3D. LVDS DC CHARACTERISTICS, VDD = VDDA = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum
Typical
350
Maximum Units
VOD
Differential Output Voltage
mV
mV
V
Δ VOD
VOS
VOD Magnitude Change
Offset Voltage
40
1.25
50
Δ VOS
VOS Magnitude Change
mV
NOTE: Please refer to Parameter Measurement Information for output information.
TABLE 3E. LVDS DC CHARACTERISTICS, VDD = VDDA = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
350
50
Maximum Units
VOD
Differential Output Voltage
mV
mV
V
Δ VOD
VOS
VOD Magnitude Change
Offset Voltage
1.2
Δ VOS
VOS Magnitude Change
40
mV
NOTE: Please refer to Parameter Measurement Information for output information.
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Typical Maximum Units
Fundamental
Mode of Oscillation
Frequency
20.4
28.3
50
7
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
pF
1
mW
TABLE 5A. AC CHARACTERISTICS, VDD = VDDA = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fOUT
Output Frequency
81.66
113.33
MHz
106.25MHz @ Integration Range:
637kHz - 10MHz
100MHz @ Integration Range:
637kHz - 10MHz
TBD
0.75
ps
RMS Phase Jitter ( Random);
NOTE 1
tjit(Ø)
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ
275
50
ps
ꢀ
NOTE 1: Please refer to the Phase Noise Plots following this section.
TABLE 5B. AC CHARACTERISTICS, VDD = VDDA = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fOUT
Output Frequency
81.66
113.33
MHz
106.25MHz @ Integration Range:
637kHz - 10MHz
100MHz @ Integration Range:
637kHz - 10MHz
TBD
0.93
ps
RMS Phase Jitter ( Random);
NOTE 1
tjit(Ø)
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ
295
50
ps
ꢀ
NOTE 1: Please refer to the Phase Noise Plots following this section.
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844011AGI
REV.A APRIL 18, 2006
4
PRELIMINARY
ICS844011I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO- LVDS
CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
SCOPE
SCOPE
Qx
Qx
2.5V 5ꢀ
3.3V 5ꢀ
POWER SUPPLY
+
POWER SUPPLY
+
LVDS
LVDS
Float GND
-
Float GND
-
nQx
nQx
LVDS 3.3V OUTPUT LOAD AC TEST CIRCUIT
LVDS 2.5V OUTPUT LOAD AC TEST CIRCUIT
Phase Noise Plot
nQ
Q
tPW
tPERIOD
Phase Noise Mask
tPW
tPERIOD
odc =
x 100ꢀ
Offset Frequency
f1
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS PHASE JITTER
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
VDD
out
80ꢀ
tF
80ꢀ
tR
➤
DC Input
LVDS
VSWING
20ꢀ
Clock
Outputs
20ꢀ
out
VOS/Δ VOS
➤
OFFSET VOLTAGE SETUP
OUTPUT RISE/FALL TIME
V
DD
➤
out
out
LVDS
DC Input
100
V
OD/Δ VOD
➤
DIFFERENTIAL OUTPUT VOLTAGE SETUP
844011AGI
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REV.A APRIL 18, 2006
5
PRELIMINARY
ICS844011I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO- LVDS
CLOCK GENERATOR
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS844011I provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL.VDD and VDDA should
be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10μF and a .01μF bypass
capacitor should be connected to each VDDA pin.
3.3V or 2.5V
VDD
.01μF
.01μF
10Ω
VDDA
10μF
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS844011I has been characterized with 18pF paral- 26.5625MHz, 18pF parallel resonant crystal and were cho-
lel resonant crystals. The capacitor values, C1 and C2, sen to minimize the ppm error. The optimum C1 and C2
shown in Figure 2 below were determined using a values can be slightly adjusted for different board layouts.
XTAL_OUT
C1
33p
X1
18pF Parallel Crystal
XTAL_IN
C2
27p
Figure 2. CRYSTAL INPUt INTERFACE
844011AGI
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REV.A APRIL 18, 2006
6
PRELIMINARY
ICS844011I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO- LVDS
CLOCK GENERATOR
LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS signal series resistance (Rs) equals the transmission line
impedance. In addition, matched termination at the crystal
input will attenuate the signal in half. This can be done in one
through an AC coupling capacitor.A general interface diagram
is shown in Figure 3. The XTAL_OUT pin can be left floating.
The input edge rate can be as slow as 10ns. For LVCMOS of two ways. First, R1 and R2 in parallel should equal the
transmission line impedance. For most 50Ω applications, R1
and R2 can be 100Ω. This can also be accomplished by
inputs, it is recommended that the amplitude be reduced from
full swing to half swing in order to prevent signal interference
with the power rail and to reduce noise. This configuration removing R1 and making R2 50Ω.
requires that the output impedance of the driver (Ro) plus the
VDD
Ro
VDD
R1
R2
.1uf
Rs
Zo = 50
XTAL_IN
Zo = Ro + Rs
XTAL_OU T
FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
3.3V, 2.5V LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 4. In a 100Ω
differential transmission line environment, LVDS drivers
require a matched load termination of 100Ω across near
the receiver input. For a multiple LVDS outputs buffer, if only
partial outputs are used, it is recommended to terminate the
un-used outputs.
2.5V or 3.3V
VDD
LVDS_Driv er
+
R1
100
-
100 Ohm Differential Transmission Line
FIGURE 4. TYPICAL LVDS DRIVERTERMINATION
844011AGI
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REV.A APRIL 18, 2006
7
PRELIMINARY
ICS844011I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO- LVDS
CLOCK GENERATOR
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP
θJA byVelocity (Meters per Second)
0
1
2.5
89.8°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
101.7°C/W
90.5°C/W
TRANSISTOR COUNT
The transistor count for ICS844011I is: 2533
844011AGI
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REV.A APRIL 18, 2006
8
PRELIMINARY
ICS844011I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO- LVDS
CLOCK GENERATOR
PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP
TABLE 7. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum
Maximum
N
A
8
--
1.20
0.15
1.05
0.30
0.20
3.10
A1
A2
b
0.05
0.80
0.19
0.09
2.90
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
844011AGI
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REV.A APRIL 18, 2006
9
PRELIMINARY
ICS844011I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO- LVDS
CLOCK GENERATOR
TABLE 8. ORDERING INFORMATION
Part/Order Number
ICS844011AGI
Marking
401AI
401AI
TBD
Package
Shipping Packaging Temperature
8 lead TSSOP
8 lead TSSOP
tube
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
ICS844011AGIT
ICS844011AGILF
ICS844011AGILFT
2500 tape & reel
tube
8 lead "Lead-Free" TSSOP
8 lead "Lead-Free" TSSOP
TBD
2500 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademarks, HiPerClockS and FemtoClocks are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
844011AGI
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REV.A APRIL 18, 2006
10
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