ICS844202BK-245 [IDT]
Clock Generator, 5 X 5 MM, 0.75 MM HEIGHT, MO-220VHHD-2, VFQFN-32;
| 型号： | ICS844202BK-245 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, 5 X 5 MM, 0.75 MM HEIGHT, MO-220VHHD-2, VFQFN-32 时钟 外围集成电路 晶体 |
| 文件： | 总13页 (文件大小：270K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
CRYSTAL-TO-LVDS PCI EXPRESS™
CLOCK SYNTHESIZER W/SPREAD SPECTRUM
ICS844202-245
GENERAL DESCRIPTION
FEATURES
• Two LVDS outputs at 25MHz, 100MHz, 125MHz or 250MHz
The ICS844202-245 is a 2 output PCI Express™ clock
ICS
HiPerClockS™
synthesizer optimized to generate low jitter PCIe
reference clocks with or without spread spectrum
modulation and is a member of the HiPerClockS™
family of high performance clock solutions from IDT.
• Crystal oscillator interface, 25MHz, 18pF parallel resonant
crystal
• Supports the following output frequencies:
25MHz, 100MHz, 125MHz or 250MHz
Spread type and amount can be configured via the SSC control
pins. Using a 25MHz, 18pF parallel resonant crystal, the device
will generate LVDS clocks at either 25MHz, 100MHz, 125MHz or
250MHz. The ICS844202-245 uses a low jitter VCO that easily
meets PCI Express jitter requirements and is packaged in a
32-pin VFQFN package.
• VCO range: 240MHz - 700MHz
• Supports SSC downspread at 0.50% and -0.75%,
centerspread at 0.25% and no spread options
• Cycle-to-cycle jitter: 70ps (typical)
• Period jitter: 40ps (typical)
• Full 3.3V power supply mode
• 0°C to 70°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
PIN ASSIGNMENT
32 31 30 29 28 27 26 25
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
VDD
VDD
nc
nc
nc
ICS844202-245
32-Lead VFQFN
5mm x 5mm x 0.75mm
package body
GND
nc
BLOCK DIAGRAM
nc
VDDO
nc
nc
K Package
Top View
SSC1
nc
FSEL0
nc
Pullup
OE
GND
9
10 11 12 13 14 15 16
Q0
25MHz
0 0 PLL Bypass
nQ0
XTAL_IN
Phase
Detector
VCO
240-700MHz
0 1 ÷5
1 0 ÷4
1 1 ÷2
OSC
Q1
XTAL_OUT
nQ1
Feedback Divider
÷20
2
2
Pullup:Pullup
Spread Spectrum
Control
SSC[1:0]
Default = 100MHz
Pulldown:Pullup
FSEL[1:0]
The Preliminary Information presented herein represents a product in pre-production.The noted characteristics are based on initial product characterization
and/or qualification.Integrated DeviceTechnology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT™ / ICS™ LVDS PCI EXPRESS™ CLOCK SYNTHESIZER
1
ICS844202BK-245 REV. A JULY 9, 2007
ICS844202-245
CRYSTAL-TO-LVDS PCI EXPRESS™ CLOCK SYNTHESIZER W/SPREAD SPECTRUM
PRELIMINARY
TABLE 1. PIN DESCRIPTIONS
Νυμ βερ
Number
Ναμ ε
Name
Type
Δεσχριπτιον
Description
1, 2, 11
VDD
Power
Core supply pins.
3, 4, 6, 8,
12, 18,
20, 21,
23, 24
nc
Unused
No connect.
5, 27
VDDO
Power
Input
Input
Output supply pins.
7
9
FSEL0
FSEL1
Pullup
Output frequency select pin. See Table 3A. LVCMOS/LVTTL interface levels.
Pulldown Output frequency select pin. See Table 3A. LVCMOS/LVTTL interface levels.
10,
19
SSC0
SSC1
XTAL_IN,
XTAL_OUT
Spread spectrum control pins. See Table 3B.
Pullup
Input
Input
Input
LVCMOS/LVTTL interface levels.
Parallel resonant crystal interface. XTAL_OUT is the output,
XTAL_IN is the input. (PLL reference.)
13, 14
15
Pullup
Output enable pin. Logic HIgh, outputs are enabled.
Logic LOW, outputs are in Hi-Z. LVCMOS/LVTTL interface levels.
OE
16, 17,
22. 29.
30
GND
Power
Power supply ground.
25, 26
28
nQ1, Q1
VDDA
Output
Power
Output
Differential output pair. LVDS interface levels.
Analog supply pin.
31, 32
nQ0, Q0
Differential output pair. LVDS interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum Units
Input Capacitance
Input Pulllup Resistor
4
pF
kΩ
kΩ
RPULLUP
51
51
RPULLDOWN Input Pulldown Resistor
TABLE 3A. FSEL[1:0] FUNCTION TABLE
TABLE 3B. SSC[1:0] FUNCTION TABLE
Input
Input
Outputs
Spread %
SSC1
SSC0
FSEL1
FSEL0
Q0:1/nQ0:1
PLL Bypass (25MHz)
100MHz (default)
125MHz
0
0
1
1
0
1
0
1
Center -0.25
Down -0.5
0
0
1
1
0
1
0
1
Down -0.75
250MHz
No Spread (default)
IDT™ / ICS™ LVDS PCI EXPRESS™ CLOCK SYNTHESIZER
2
ICS844202BK-245 REV. A JULY 9, 2007
ICS844202-245
CRYSTAL-TO-LVDS PCI EXPRESS™ CLOCK SYNTHESIZER W/SPREAD SPECTRUM
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
Inputs, V
-0.5V to VDD + 0.5V
I
Outputs, IO
Continuous Current
Surge Current
10mA
15mA
Package Thermal Impedance, θ
42.4°C/W (0 mps)
-65°C to 150°C
JA
Storage Temperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical Maximum Units
VDD
VDDA
VDDO
IDD
Core Supply Voltage
3.3
3.3
3.3
83
3.465
VDD
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
VDD – 0.12
3.135
3.465
V
mA
mA
mA
IDDA
IDDO
12
26
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
2
VDD + 0.3
0.8
V
V
Input Low Voltage
-0.3
FSEL1
VDD = VIN = 3.465V
VDD = VIN = 3.465V
150
µA
IIH
Input High Current
SSC0, SSC1,
FSEL0, OE
5
µA
µA
µA
FSEL1
VDD = 3.465V, VIN = 0V
VDD = 3.465V, VIN = 0V
-5
IIL
Input Low Current
SSC0, SSC1,
FSEL0, OE
-150
TABLE 4C. LVDS DC CHARACTERISTICS, DD = VDDA = VDDO = 3.3V 5%, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum
Typical
350
Maximum Units
VOD
Differential Output Voltage
mV
mV
V
Δ VOD
VOS
VOD Magnitude Change
Offset Voltage
50
1.33
50
Δ VOS
VOS Magnitude Change
mV
IDT™ / ICS™ LVDS PCI EXPRESS™ CLOCK SYNTHESIZER
3
ICS844202BK-245 REV. A JULY 9, 2007
ICS844202-245
CRYSTAL-TO-LVDS PCI EXPRESS™ CLOCK SYNTHESIZER W/SPREAD SPECTRUM
PRELIMINARY
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Fundamental
25
Typical Maximum Units
Mode of Oscillation
Frequency
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
TBD
7
pF
100
µW
NOTE: Characterized using an 18pF parallel resonant crystal.
TABLE 6. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
25
125
100
250
35
MHz
MHz
MHz
MHz
ps
fOUT
Output Frequency
25MHz
100MHz
125MHz
250MHz
25MHz
45
ps
tjit(per) Period Jitter, RMS
40
ps
40
ps
60
ps
100MHz
125MHz
250MHz
70
ps
Cycle-to-Cycle Jitter; NOTE 1, 2
t
jit(cc)
60
ps
70
ps
tsk(o)
Fxtal
Output Skew; NOTE 2, 3
40
ps
Crystal Input Range; NOTE 1
SSC Modulation Frequency; NOTE 4
SSC Modulation Factor; NOTE 4
Spectral Reduction; NOTE 5
Power-up to Stable Clock Output
Output Rise/Fall Time
12
25
35
10
MHz
kHz
%
FM
TBD
TBD
11
FMF
SSCred
tSTABLE
tR / tF
odc
dB
ms
ps
20% - 80%
525
50
Output Duty Cycle
%
NOTE 1: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 2: Only valid within the VCO operating range.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 4: Spread Spectrum clocking enabled.
IDT™ / ICS™ LVDS PCI EXPRESS™ CLOCK SYNTHESIZER
4
ICS844202BK-245 REV. A JULY 9, 2007
ICS844202-245
CRYSTAL-TO-LVDS PCI EXPRESS™ CLOCK SYNTHESIZER W/SPREAD SPECTRUM
PRELIMINARY
PARAMETER MEASUREMENT INFORMATION
VOH
VREF
SCOPE
VDD,
Qx
VOL
3.3V 10%
VDDO
1σ contains 68.26% of all measurements
2σ contains 95.4% of all measurements
3σ contains 99.73% of all measurements
4σ contains 99.99366% of all measurements
6σ contains (100-1.973x10-7)% of all measurements
VDDA
POWER SUPPLY
+
Float GND –
LVDS
nQx
Histogram
Reference Point
(Trigger Edge)
Mean Period
(First edge after trigger)
3.3V LVDS OUTPUT LOAD AC TEST CIRCUIT
PERIOD JITTER
nQx
Qx
nQ0, nQ1
Q0, Q1
➤
➤
tcycle n
tcycle n+1
➤
➤
nQy
tjit(cc) = tcycle n – tcycle n+1
Qy
1000 Cycles
tsk(o)
OUTPUT SKEW
CYCLE-TO-CYCLE JITTER
nQ0, nQ1
Q0, Q1
80%
80%
tR
VOD
tPW
Clock
Outputs
20%
tPERIOD
20%
tF
tPW
odc =
x 100%
tPERIOD
OUTPUT RISE/FALL TIME
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
IDT™ / ICS™ LVDS PCI EXPRESS™ CLOCK SYNTHESIZER
5
ICS844202BK-245 REV. A JULY 9, 2007
ICS844202-245
CRYSTAL-TO-LVDS PCI EXPRESS™ CLOCK SYNTHESIZER W/SPREAD SPECTRUM
PRELIMINARY
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS844204-245 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VDD, VDDA and
VDDO should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin.To achieve optimum jitter performance, power
supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10µF and a .01μF bypass
3.3V
VDD
.01μF
.01μF
10Ω
VDDA
10μF
capacitor should be connected to each VDDA
.
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
were determined using a 25MHz, 18pF parallel resonant crystal
and were chosen to minimize the ppm error.
The ICS844204-245 has been characterized with 18pF parallel
resonant crystals. The capacitor values shown in Figure 2 below
XTAL_OUT
XTAL_IN
C1
27p
X1
18pF Parallel Crystal
C2
27p
FIGURE 2. CRYSTAL INPUt INTERFACE
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
LVDS OUTPUTS
LVCMOS CONTROL PINS
All unused LVDS output pairs can be either left floating or
terminated with 100Ω across. If they are left floating, there should
be no trace attached.
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
IDT™ / ICS™ LVDS PCI EXPRESS™ CLOCK SYNTHESIZER
6
ICS844202BK-245 REV. A JULY 9, 2007
ICS844202-245
CRYSTAL-TO-LVDS PCI EXPRESS™ CLOCK SYNTHESIZER W/SPREAD SPECTRUM
PRELIMINARY
LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS
signal through an AC couple capacitor. A general interface
diagram is shown in Figure 3. The XTAL_OUT pin can be left
floating. The input edge rate can be as slow as 10ns. For
LVCMOS inputs, it is recommended that the amplitude be
reduced from full swing to half swing in order to prevent signal
interference with the power rail and to reduce noise. This
configuration requires that the output impedance of the driver
(Ro) plus the series resistance (Rs) equals the transmission
line impedance. In addition, matched termination at the crystal
input will attenuate the signal in half. This can be done in one
of two ways. First, R1 and R2 in parallel should equal the
transmission line impedance. For most 50Ω applications, R1
and R2 can be 100Ω. This can also be accomplished by
removing R1 and making R2 50Ω.
VDD
VDD
R1
.1uf
Ro
Rs
Zo = 50
XTAL_IN
R2
Zo = Ro + Rs
XTAL_OU T
FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
THERMAL RELEASE PATH
The expose metal pad provides heat transfer from the device to
the P.C. board. The expose metal pad is ground pad connected
to ground plane through thermal via. The exposed pad on the
device to the exposed metal pad on the PCB is contacted through
solder as shown in Figure 4. For further information, please refer
to the Application Note on Surface Mount Assembly of Amkor’s
Thermally /Electrically Enhance Leadframe Base Package, Amkor
Technology.
SOLDER
SOLDER
PIN
PIN
EPAD
PIN PAD
GROUND PLANE
EXPOSED METAL PAD
(GROUND PAD)
PIN PAD
THERMAL VIA
FIGURE 4. P.C. BOARD FOR EXPOSED PAD THERMAL RELEASE PATH EXAMPLE
IDT™ / ICS™ LVDS PCI EXPRESS™ CLOCK SYNTHESIZER
7
ICS844202BK-245 REV. A JULY 9, 2007
ICS844202-245
CRYSTAL-TO-LVDS PCI EXPRESS™ CLOCK SYNTHESIZER W/SPREAD SPECTRUM
PRELIMINARY
3.3V LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 5. In a 100Ω
differential transmission line environment, LVDS drivers require
a matched load termination of 100Ω across near the receiver
input. For a multiple LVDS outputs buffer, if only partial outputs
are used, it is recommended to terminate the un-used outputs.
3.3V
3.3V
LVDS
+
R1
100
-
100 Ohm Differential Transmission Line
FIGURE 5. TYPICAL LVDS DRIVER TERMINATION
IDT™ / ICS™ LVDS PCI EXPRESS™ CLOCK SYNTHESIZER
8
ICS844202BK-245 REV. A JULY 9, 2007
ICS844202-245
CRYSTAL-TO-LVDS PCI EXPRESS™ CLOCK SYNTHESIZER W/SPREAD SPECTRUM
PRELIMINARY
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS844202-245.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS844202-245 is the sum of the core power plus the analog power plus the power dissipated in
the load(s). The following is the power dissipation for V = 3.3V + 5% = 3.645V, which gives worst case results.
DD
•
Power (core) = V
* (I
+ I
+ I
) = 2.465V * (83mA + 12mA + 26mA) = 121mW
DDO_MAX
MAX
DD_MAX
DD_MAX
DDA_MAX
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
TM
device. The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air
flow and a multi-layer board, the appropriate value is 42.4°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.121W * 42.4°C/W = 75.1°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and
the type of board (single layer or multi-layer).
TABLE 7. THERMAL RESISTANCE θ FOR 32-LEAD VFQFN, FORCED CONVECTION
JA
θ by Velocity (Meters per Second)
JA
0
1
2.5
33.2°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
42.4°C/W
37.0°C/W
IDT™ / ICS™ LVDS PCI EXPRESS™ CLOCK SYNTHESIZER
9
ICS844202BK-245 REV. A JULY 9, 2007
ICS844202-245
CRYSTAL-TO-LVDS PCI EXPRESS™ CLOCK SYNTHESIZER W/SPREAD SPECTRUM
PRELIMINARY
RELIABILITY INFORMATION
TABLE 7. θ VS. AIR FLOW TABLE FOR 32 LEAD VFQFN
JA
θ by Velocity (Meters per Second)
JA
0
1
2.5
33.2°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
42.4°C/W
37.0°C/W
TRANSISTOR COUNT
The transistor count for ICS844202-245 is: 4715
IDT™ / ICS™ LVDS PCI EXPRESS™ CLOCK SYNTHESIZER
10
ICS844202BK-245 REV. A JULY 9, 2007
ICS844202-245
CRYSTAL-TO-LVDS PCI EXPRESS™ CLOCK SYNTHESIZER W/SPREAD SPECTRUM
PRELIMINARY
PACKAGE OUTLINE - K SUFFIX FOR 32 LEAD VFQFN
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
VHHD-2
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
--
0.80
0
1.00
0.05
A1
A3
b
--
0.25 Ref.
0.25
0.18
0.30
8
ND
NE
D
8
5.00 BASIC
2.25
D2
E
1.25
1.25
0.30
3.25
3.25
0.50
5.00 BASIC
2.25
E2
e
0.50 BASIC
0.40
L
Reference Document: JEDEC Publication 95, MO-220
IDT™ / ICS™ LVDS PCI EXPRESS™ CLOCK SYNTHESIZER
11
ICS844202BK-245 REV. A JULY 9, 2007
ICS844202-245
CRYSTAL-TO-LVDS PCI EXPRESS™ CLOCK SYNTHESIZER W/SPREAD SPECTRUM
PRELIMINARY
TABLE 9. ORDERING INFORMATION
Part/Order Number
ICS844202BK-245
Marking
TBD
Package
Shipping Packaging Temperature
32 Lead VFQFN
tray
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
ICS844202BK-245T
ICS844202BK-245LF
ICS844202BK-245LFT
TBD
32 Lead VFQFN
2500 tape & reel
tray
ICS402B245L
ICS402B245L
32 Lead "Lead-Free" VFQFN
32 Lead "Lead-Free" VFQFN
2500 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extneded temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional
processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical
instruments.
IDT™ / ICS™ LVDS PCI EXPRESS™ CLOCK SYNTHESIZER
12
ICS844202BK-245 REV. A JULY 9, 2007
ICS844202-245
CRYSTAL-TO-LVDS PCI EXPRESS™ CLOCK SYNTHESIZER W/SPREAD SPECTRUM
PRELIMINARY
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
800-345-7015
408-284-8200
Fax: 408-284-2775
For Tech Support
netcom@idt.com
480-763-2056
Corporate Headquarters
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
Asia Pacific and Japan
Integrated Device Technology
Singapore (1997) Pte. Ltd.
Reg. No. 199707558G
435 Orchard Road
Europe
IDT Europe, Limited
321 Kingston Road
Leatherhead, Surrey
KT22 7TU
United States
800 345 7015
#20-03 Wisma Atria
England
+408 284 8200 (outside U.S.)
Singapore 238877
+44 (0) 1372 363 339
Fax: +44 (0) 1372 378851
+65 6 887 5505
© 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks
of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be
trademarks or registered trademarks used to identify products or services of their respective owners.
Printed in USA
相关型号：
ICS844202BK-245LF
Clock Generator, 5 X 5 MM, 0.75 MM HEIGHT, ROHS COMPLIANT, MO-220VHHD-2, VFQFN-32
IDT
ICS844204BK-245LF
Clock Generator, 250MHz, 5 X 5 MM, 0.75 MM HEIGHT, ROHS COMPLIANT, MO-220VHHD-2, VFQFN-32
IDT
ICS844204BK-245LFT
Clock Generator, 250MHz, 5 X 5 MM, 0.75 MM HEIGHT, ROHS COMPLIANT, MO-220VHHD-2, VFQFN-32
IDT
ICS844242AGI-04LF
Clock Generator, 150MHz, PDSO16, 4.40 X 5 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-16
IDT
ICS844242AGI-04LFT
Clock Generator, 150MHz, PDSO16, 4.40 X 5 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-16
IDT
ICS844242AGI-08LF
Clock Generator, 75MHz, PDSO16, 4.40 X 5 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-16
IDT
ICS844242AGI-08LFT
Clock Generator, 75MHz, PDSO16, 4.40 X 5 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-16
IDT
ICS844244AGI-04LF
Clock Generator, 150MHz, PDSO16, 4.40 X 5 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-16
IDT
ICS844244AGI-04LFT
Clock Generator, 150MHz, PDSO16, 4.40 X 5 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-16
IDT
©2020 ICPDF网 联系我们和版权申明