ICS85104AMILFT [IDT]

Low Skew Clock Driver, 85104 Series, 4 True Output(s), 0 Inverted Output(s), PDSO20, 7.50 MM, 12.80 MM, 2.30 MM HEIGHT, ROHS COMPLIANT, MS-013, MO-119, SOIC-20;


型号：	ICS85104AMILFT
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	Low Skew Clock Driver, 85104 Series, 4 True Output(s), 0 Inverted Output(s), PDSO20, 7.50 MM, 12.80 MM, 2.30 MM HEIGHT, ROHS COMPLIANT, MS-013, MO-119, SOIC-20 光电二极管
文件：	总13页 (文件大小：304K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PRELIMINARY

LOW SKEW, 1-TO-4, DIFFERENTIAL/

LVCMOS-TO-0.7V HCSL FANOUT BUFFER

ICS85104I

GENERAL DESCRIPTION

FEATURES

The ICS85104I is a low skew, high performance 1-

• Four 0.7V differential HCSL outputs

ICS

HiPerClockS™

to-4 Differential/LVCMOS-to-0.7V HCSL Fanout

• Selectable differential CLK0, nCLK0 or LVCMOS inputs

Buffer and a member of the HiPerClockS™family

of High Performance Clock Solutions from IDT.

The ICS85104I has two selectable clock inputs.

• CLK0, nCLK0 pair can accept the following differential

input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL

The CLK0, nCLK0 pair can accept most standard differential

input levels. The single-ended CLK1 can accept LVCMOS or

LVTTL input levels. The clock enable is internally synchronized

to eliminate runt clock pulses on the outputs during asynchro-

nous assertion/deassertion of the clock enable pin.

• CLK1 can accept the following input levels:

LVCMOS or LVTTL

• Maximum output frequency: 500MHz

• Translates any single-ended input signal to 3.3V

HCSL levels with resistor bias on nCLK input

Guaranteed output and part-to-part skew characteristics make

the ICS85104I ideal for those applications demanding well

defined performance and repeatability.

• Output skew: 75ps (typical), TSSOP package

TBD, SOIC package

• Part-to-part skew: 300ps (typical)

• Propagation delay: 2.4ns (typical)

• Additive phase jitter, RMS: 0.31ps (typical)

• 3.3V operating supply

• -40°C to 85°C ambient operating temperature

• Available in both standard (RoHS 5) and lead-free (RoHS 6)

packages

BLOCK DIAGRAM

PIN ASSIGNMENT

VSS

CLK_EN

CLK_SEL

CLK0

nCLK0

CLK1

nQ0

V^DD

nQ1

nQ2

V^DD

Pullup

CLK_EN

Pulldown

Pullup

CLK0

nCLK0

IREF

V^DD

nQ0

nQ3

Pulldown

CLK1

nQ1

ICS85104I

20-Lead TSSOP

6.5mm x 4.4mm x 0.92mm Package Body

G Package

CLK_SEL

nQ2

IREF

nQ3

Top View

ICS85104I

20-Lead SOIC

7.5mm x 12.8mm x 2.3mm Package Body

M Package

Top View

The Preliminary Information presented herein represents a product in pre-production.The noted characteristics are based on initial product characterization and/

or qualification.Integrated DeviceTechnology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.

IDT^™/ ICS^™0.7V HCSL FANOUT BUFFER

ICS85104AGI REV. A NOVEMBER 13, 2006

ICS85104I

LOW SKEW, 1-TO-4, DIFFERENTIAL/LVCMOS-TO-0.7V HCSL FANOUT BUFFER

PRELIMINARY

TABLE 1. PIN DESCRIPTIONS

Number

Name

Type

Description

V_SS

Power

Input

Negative supply pin.

Synchronizing clock enable. When HIGH, clock outputs follow clock input.

When LOW, Qx outputs are forced low, nQx outputs are forced high.

LVTTL / LVCMOS interface levels.

CLK_EN

Pullup

Clock select input. When HIGH, selects CLK1 input.

CLK_SEL

Input

Pulldown When LOW, selects CLK0, nCLK0 inputs.

LVTTL / LVCMOS interface levels.

CLK0

nCLK0

CLK1

Input

Pulldown Non-inverting differential clock input.

Pullup

Inverting differential clock input.

Input

Pulldown Single-ended clock input. LVTTL / LVCMOS interface levels.

No connect.

7, 8

Unused

A fixed precision resistor (475Ω) from this pin to ground provides a

reference current used for differential current-mode Qx/nQx clock outputs.

IREF

Input

10, 13, 18

11, 12

V_DD

Power

Output

Positive supply pins.

nQ3, Q3

nQ2, Q2

nQ1, Q1

nQ0, Q0

Differential output pair. HCSL interface levels.

14, 15

16, 17

19, 20

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

TABLE 2. PIN CHARACTERISTICS

Symbol

C_IN

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

Input Capacitance

Input Pullup Resistor

Input Pulldown Resistor

R_PULLUP

R_PULLDOWN

kΩ

IDT^™/ ICS^™0.7V HCSL FANOUT BUFFER

ICS85104AGI REV. A NOVEMBER 13, 2006

ICS85104I

LOW SKEW, 1-TO-4, DIFFERENTIAL/LVCMOS-TO-0.7V HCSL FANOUT BUFFER

PRELIMINARY

TABLE 3A. CONTROL INPUT FUNCTION TABLE

Inputs

Outputs

CLK_EN

CLK_SEL

Selected Source

CLK0, nCLK0

CLK1

Q0:Q3

Disabled; LOW

Enabled

nQ0:nQ3

Enabled

CLK0, nCLK0

CLK1

Disabled; HIGH

Enabled

After CLK_EN switches, the clock outputs are disabled or enabled following a falling input clock edge

as shown in Figure 1.

In the active mode, the state of the outputs are a function of the CLK0, nCLK0 and CLK1 inputs

as described in Table 3B.

Enabled

Disabled

nCLK0

CLK0, CLK1

CLK_EN

nQ0:nQ3

Q0:Q3

FIGURE 1. CLK_EN TIMING DIAGRAM

TABLE 3B. CLOCK INPUT FUNCTION TABLE

Inputs

Outputs

Input to Output Mode

Polarity

CLK0 or CLK1

nCLK0

Q0:Q3

LOW

nQ0:nQ3

HIGH

Differential to Differential

Non Inverting

HIGH

LOW

IDT^™/ ICS^™0.7V HCSL FANOUT BUFFER

ICS85104AGI REV. A NOVEMBER 13, 2006

ICS85104I

LOW SKEW, 1-TO-4, DIFFERENTIAL/LVCMOS-TO-0.7V HCSL FANOUT BUFFER

PRELIMINARY

ABSOLUTE MAXIMUM RATINGS

Supply Voltage, V_DD

4.6V

NOTE: Stresses beyond those listed under Absolute

Maximum Ratings may cause permanent damage to the

device.These ratings are stress specifications only. Functional op-

eration of product at these conditions or any conditions beyond

those listed in the DC Characteristics or AC Characteristics is not

implied. Exposure to absolute maximum rating conditions for ex-

tended periods may affect product reliability.

Inputs, V

-0.5V to V_DD+ 0.5V

Outputs, I_O

Continuous Current

Surge Current

50mA

100mA

Package Thermal Impedance, θ

20 Lead TSSOP

20 Lead SOIC

73.2°C/W (0 lfpm)

46.2°C/W (0 lfpm)

Storage Temperature, T

-65°C to 150°C

STG

TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V_DD= 3.3V 10ꢀ, TA = -40°C TO 85°C

Symbol Parameter

Test Conditions

Minimum

Typical

3.3

Maximum Units

V_DD

V_SS

Positive Supply Voltage

Power Supply Current

2.97

3.63

TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, V_DD= 3.3V 10ꢀ, TA = -40°C TO 85°C

Symbol Parameter

Test Conditions

Minimum Typical Maximum Units

V_IH

V_IL

Input High Voltage

Input Low Voltage

V_DD+ 0.3

-0.3

0.8

150

CLK1, CLK_SEL

V_IN= V_DD= 3.63V

µA

Input

I_IH

High Current

CLK_EN

_IN= V_DD= 3.63V

_IN= 0V, V_DD= 3.63V

V_IN= 0V, V_DD= 3.63V

CLK1, CLK_SEL

CLK_EN

-5

Input

Low Current

I_IL

-150

TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, V_DD= 3.3V 10ꢀ, TA = -40°C TO 85°C

Symbol Parameter

Test Conditions

V_DD= V_IN= 3.63V

Minimum Typical

Maximum Units

CLK0

150

µA

I_IHInput High Current

nCLK0

CLK0

V_DD= V_IN= 3.63V

V_DD= 3.63V, V_IN= 0V

-5

I_IL

Input Low Current

nCLK0

-150

0.15

V_PP

Peak-to-Peak Input Voltage

1.3

Common Mode Input Voltage;

NOTE 1, 2

V_CMR

_SS+ 0.5

V_DD- 0.85

NOTE 1: For single ended applications, the maximum input voltage for CLK0, nCLK0 is V_DD+ 0.3V.

NOTE 2: Common mode voltage is defined as V_IH.

IDT^™/ ICS^™0.7V HCSL FANOUT BUFFER

ICS85104AGI REV. A NOVEMBER 13, 2006

ICS85104I

LOW SKEW, 1-TO-4, DIFFERENTIAL/LVCMOS-TO-0.7V HCSL FANOUT BUFFER

PRELIMINARY

TABLE 5. AC CHARACTERISTICS, V_DD= 3.3V 10ꢀ, TA = -40°C TO 85°C

Symbol Parameter

Test Conditions

Minimum Typical

Maximum

500

Units

MHz

CLK0, nCLK0

CLK1

f_MAXOutput Frequency

250

CLK0, nCLK0

CLK1

2.4

2.2

Propagation Delay;

NOTE 1

t_PD

tsk(o)

Output Skew; NOTE 2, 4

tsk(pp)

Part-to-Part Skew; NOTE 3, 4

Buffer Additive Phase

300

100MHz,

(12kHz - 20MHz)

100MHz,

CLK0, nCLK0

0.22

0.31

Jitter, RMS; refer to

Additive Phase Jitter

Section

tjit

CLK1

(12kHz - 20MHz)

V_HIGH

V_LOW

V_OVS

V_UDS

V_rb

Voltage High

660

850

Voltage Low

-150

Max. Voltage, Overshoot

V_HIGH+ 0.3

Min. Voltage, Undershoot

Ringback Voltage

-0.3

250

0.2

550

140

V_CROSS

ΔV_CROSS

t_L

Absolute Crossing Voltage

Total Variation of V_CROSSover all edges

PLL Lock Time

TBD

Measured between

0.175 to 0.525

t_R/t_F

Output Rise/Fall Time

175

700

Δt_R/Δt_F

Rise/Fall Time Variation

125

ꢀ

t_RFM

Rise/Fall Matching; NOTE 5

CLK0, nCLK0

Output Duty Cycle

ƒ≤ 700MHz

ƒ≤ 250MHz

odc

CLK1

All parameters measured at ƒ≤ 500MHz unless noted otherwise.

NOTE 1: Measured from the V_DD/2 of the input to the differential output crossing point.

NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.

Measured at the output differential cross points.

NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages

and with equal load conditions. Using the same type of inputs on each device, the outputs are measured

at the differential cross points.

NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.

NOTE 5: Matching applies to rising edge rate for Qx and falling edge rate for nQx. It is measured using a 75mV window

centered on the median cross point where Qx rising meets nQx falling.

IDT^™/ ICS^™0.7V HCSL FANOUT BUFFER

ICS85104AGI REV. A NOVEMBER 13, 2006

ICS85104I

LOW SKEW, 1-TO-4, DIFFERENTIAL/LVCMOS-TO-0.7V HCSL FANOUT BUFFER

PRELIMINARY

PARAMETER MEASUREMENT INFORMATION

3.3V±±0ꢀ

V_DD

Measurement

V_DD

50Ω

33Ω

Point

49.9Ω

nCLK0

CLK0

2pF

HCSL

V_PP

V_CMR

Measurement

Point

Cross Points

33Ω

GND

2pF

V_SS

HCSL OUTPUT LOAD AC TEST CIRCUIT

DIFFERENTIAL INPUT LEVELS

PART ±

nQx

PART 2

nQy

tsk(pp)

tsk(o)

OUTPUT SKEW

PART-TO-PART SKEW

nQ0:nQ3

nCLK0

CLK0

Q0:Q3

t_PW

t_PERIOD

nQ0:nQ4

Q0:Q4

t_PW

odc =

x ±00ꢀ

t_PD

t_PERIOD

OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD

80ꢀ

t_F

80ꢀ

CLK±

V_SWING

20ꢀ

Clock

20ꢀ

nQ0:nQ3

Outputs

t_R

Q0:Q3

t_PD

PROPAGATION DELAY (LVCMOS INPUT)

OUTPUT RISE/FALL TIME

IDT^™/ ICS^™0.7V HCSL FANOUT BUFFER

ICS85104AGI REV. A NOVEMBER 13, 2006

ICS85104I

LOW SKEW, 1-TO-4, DIFFERENTIAL/LVCMOS-TO-0.7V HCSL FANOUT BUFFER

PRELIMINARY

APPLICATION INFORMATION

RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS

INPUTS:

CLK INPUT:

OUTPUTS:

DIFFERENTIAL OUTPUT

For applications not requiring the use of a clock input, it can be

left floating. Though not required, but for additional protection, a

1kΩ resistor can be tied from the CLK input to ground.

All unused differential outputs can be left floating.We recommend

that there is no trace attached. Both sides of the differential output

pair should either be left floating or terminated.

CLK/nCLK I^NPUT:

For applications not requiring the use of the differential input,

both CLK and nCLK can be left floating. Though not required, but

for additional protection, a 1kΩ resistor can be tied from CLK to

ground.

LVCMOS C^ONTROLPINS:

All control pins have internal pull-ups or pull-downs; additional

resistance is not required but can be added for additional

protection. A 1kΩ resistor can be used.

WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS

Figure 2 shows how the differential input can be wired to accept

single ended levels. The reference voltage V_REF = V /2 is

generated by the bias resistors R1, R2 and C1. This bias ^Dc^Dircuit

should be located as close as possible to the input pin. The ratio

of R1 and R2 might need to be adjusted to position the V_REF in

the center of the input voltage swing. For example, if the input

clock swing is only 2.5V and V = 3.3V, V_REF should be 1.25V

and R2/R1 = 0.609.

VDD

Single Ended Clock Input

V_REF

CLK

nCLK

0.1u

FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT

IDT^™/ ICS^™0.7V HCSL FANOUT BUFFER

ICS85104AGI REV. A NOVEMBER 13, 2006

ICS85104I

LOW SKEW, 1-TO-4, DIFFERENTIAL/LVCMOS-TO-0.7V HCSL FANOUT BUFFER

PRELIMINARY

DIFFERENTIAL CLOCK INPUT INTERFACE

The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL

and other differential signals. Both V_SWINGand V_OHmust meet the

V_PPand V_CMRinput requirements. Figures 3A to 3E show interface

examples for the HiPerClockS CLK/nCLK input driven by the most

common driver types. The input interfaces suggested here are

examples only. Please consult with the vendor of the driver

component to confirm the driver termination requirements. For

example in Figure 3A, the input termination applies for IDT

HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver

from another vendor, use their termination recommendation.

3.3V

1.8V

Zo = 50 Ohm

CLK

Zo = 50 Ohm

CLK

Zo = 50 Ohm

nCLK

Zo = 50 Ohm

HiPerClockS

LVPECL

Input

nCLK

HiPerClockS

LVHSTL

Input

ICS

HiPerClockS

LVHSTL Driver

FIGURE 3A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY

IDT HIPERCLOCKS LVHSTL DRIVER

FIGURE 3B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY

3.3V LVPECL DRIVER

3.3V

Zo = 50 Ohm

3.3V

125

LVDS_Driver

Zo = 50 Ohm

CLK

100

nCLK

Receiv er

nCLK

HiPerClockS

Input

Zo = 50 Ohm

LVPECL

FIGURE 3C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY

3.3V LVPECL DRIVER

FIGURE 3D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY

3.3V LVDS DRIVER

3.3V

125

LVPECL

Zo = 50 Ohm

CLK

nCLK

HiPerClockS

Input

100 - 200

R5,R6 locate near the driver pin.

FIGURE 3E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY

3.3V LVPECL DRIVER WITH AC COUPLE

IDT^™/ ICS^™0.7V HCSL FANOUT BUFFER

ICS85104AGI REV. A NOVEMBER 13, 2006

ICS85104I

LOW SKEW, 1-TO-4, DIFFERENTIAL/LVCMOS-TO-0.7V HCSL FANOUT BUFFER

PRELIMINARY

RECOMMENDEDT ERMINATION

Figure 4A is the recommended termination for applications

which require the receiver and driver to be on a separate PCB.

All traces should be 50Ω impedance.

FIGURE 4A. RECOMMENDED TERMINATION

Figure 4B is the recommended termination for applications

and receiver on the same PCB. All traces should all be 50Ù

which require a point to point connection and contain the driver

impedance.

FIGURE 4B. RECOMMENDED TERMINATION

IDT^™/ ICS^™0.7V HCSL FANOUT BUFFER

ICS85104AGI REV. A NOVEMBER 13, 2006

ICS85104I

LOW SKEW, 1-TO-4, DIFFERENTIAL/LVCMOS-TO-0.7V HCSL FANOUT BUFFER

PRELIMINARY

RELIABILITY INFORMATION

TABLE 6A. θ VS. AIR FLOW TABLE FOR 20 LEAD TSSOP

θ by Velocity (Linear Feet per Minute)

200

98.0°C/W

66.6°C/W

500

88.0°C/W

63.5°C/W

Single-Layer PCB, JEDEC Standard Test Boards

Multi-Layer PCB, JEDEC Standard Test Boards

114.5°C/W

73.2°C/W

NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

TABLE 6B. θ VS. AIR FLOW TABLE FOR 20 LEAD SOIC

θ by Velocity (Linear Feet per Minute)

200

65.7°C/W

39.7°C/W

500

57.5°C/W

36.8°C/W

Single-Layer PCB, JEDEC Standard Test Boards

Multi-Layer PCB, JEDEC Standard Test Boards

83.2°C/W

46.2°C/W

NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

TRANSISTOR COUNT

The transistor count for ICS85104I is: 614

IDT^™/ ICS^™0.7V HCSL FANOUT BUFFER

ICS85104AGI REV. A NOVEMBER 13, 2006

ICS85104I

LOW SKEW, 1-TO-4, DIFFERENTIAL/LVCMOS-TO-0.7V HCSL FANOUT BUFFER

PRELIMINARY

PACKAGE OUTLINE - G SUFFIX FOR 20 LEAD TSSOP

PACKAGE OUTLINE - M SUFFIX FOR 20 LEAD SOIC

T^ABLE7A. PACKAGE DIMENSIONS

TABLE 7B. PACKAGE DIMENSIONS

Millimeters

SYMBOL

Minimum

Maximum

Minimum

Maximum

2.65

1.20

0.15

1.05

0.30

0.20

6.60

0.10

2.05

0.33

0.18

12.60

7.40

0.05

0.80

0.19

0.09

6.40

2.55

0.51

0.32

13.00

7.60

6.40 BASIC

0.65 BASIC

1.27 BASIC

4.30

4.50

10.00

0.25

0.40

0°

10.65

0.75

1.27

8°

0.45

0°

0.75

8°

aaa

0.10

Reference Document: JEDEC Publication 95, MS-013, MO-119

Reference Document: JEDEC Publication 95, MO-153

IDT^™/ ICS^™0.7V HCSL FANOUT BUFFER

ICS85104AGI REV. A NOVEMBER 13, 2006

ICS85104I

LOW SKEW, 1-TO-4, DIFFERENTIAL/LVCMOS-TO-0.7V HCSL FANOUT BUFFER

PRELIMINARY

TABLE 8. ORDERING INFORMATION

Part/Order Number

ICS85104AGI

Marking

ICS85104AGI

ICS85104AGIL

TBD

Package

Shipping Packaging

tube

Temperature

20 lead TSSOP

-40°C to 85°C

ICS85104AGIT

ICS85104AGILF

ICS85104AGILFT

ICS85104AMI

20 lead TSSOP

2500 tape & reel

tube

20 lead "Lead-Free" TSSOP

20 lead SOIC

2500 tape & reel

tube

ICS85104AMIT

ICS85104AMILF

ICS85104AMILFT

TBD

20 lead SOIC

1000 tape & reel

tube

TBD

20 lead "Lead-Free" SOIC

TBD

1000 tape & reel

NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.

While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for

infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and

industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT

reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.

IDT^™/ ICS^™0.7V HCSL FANOUT BUFFER

ICS85104AGI REV. A NOVEMBER 13, 2006

ICS85104I

LOW SKEW, 1-TO-4, DIFFERENTIAL/LVCMOS-TO-0.7V HCSL FANOUT BUFFER

PRELIMINARY

Innovate with IDT and accelerate your future networks. Contact:

www.IDT.com

For Sales

800-345-7015

408-284-8200

Fax: 408-284-2775

For Tech Support

netcom@idt.com

480-763-2056

Corporate Headquarters

Integrated Device Technology, Inc.

6024 Silver Creek Valley Road

San Jose, CA 95138

Asia Pacific and Japan

Integrated Device Technology

Singapore (1997) Pte. Ltd.

Reg. No. 199707558G

435 Orchard Road

Europe

IDT Europe, Limited

321 Kingston Road

Leatherhead, Surrey

KT22 7TU

United States

800 345 7015

#20-03 Wisma Atria

England

+408 284 8200 (outside U.S.)

Singapore 238877

+44 (0) 1372 363 339

Fax: +44 (0) 1372 378851

+65 6 887 5505

of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be

trademarks or registered trademarks used to identify products or services of their respective owners.

Printed in USA

ICS85104AMILFT [IDT]

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