ICS8516FY-01T [IDT]
Low Skew Clock Driver, 16 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, LQFP-48;
| 型号： | ICS8516FY-01T |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew Clock Driver, 16 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, LQFP-48 |
| 文件： | 总15页 (文件大小：158K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS8516-01
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
GENERAL DESCRIPTION
FEATURES
The ICS8516-01 is a low skew, high performance • 16 Differential LVDS outputs
1-to-16 Differential-to-LVDS Clock Distribution
Chip and a member of the HiPerClockS™
family of High Performance Clock Solutions
from ICS. The ICS8516-01 CLK, nCLK pair can
• CLK, nCLK pair can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
HiPerClockS™
• Output frequency: 700MHz
accept any differential input levels and translates them to
3.3V LVDS output levels. Utilizing Low Voltage Differential
Signaling (LVDS), the ICS8516-01 provides a low power, low
noise, point-to-point solution for distributing clock signals over
controlled impedances of 100Ω.
• Translates any differential input signal (LVPECL, LVHSTL,
SSTL, DCM) to LVDS levels without external bias networks
• Translates any single-ended input signal to LVDS with
resistor bias on nCLK input
Dual output enable inputs allow the ICS8516-01 to be used
in a 1-to-16 or 1-to-8 input/output mode.
• Multiple output enable inputs for disabling unused outputs
in reduced fanout applications
Guaranteed output and part-to-part skew specifications make
the ICS8516-01 ideal for those applications demanding well
defined performance and repeatability.
• Output skew: 120ps (maximum)
• Part-to-part skew: 500ps (maximum)
• Propagation delay: 1.9ns (maximum)
• 3.3V operating supply
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
BLOCK DIAGRAM
PIN ASSIGNMENT
OE2
D
Q
Q
LE
D
OE1
48 47 46 45 44 43 42 41 40 39 38 37
VDD
nQ5
Q5
1
36
35
34
33
32
31
30
29
28
27
26
25
VDD
LE
2
nQ10
Q10
nQ11
Q11
VDD
3
CLK
nCLK
nQ4
Q4
4
5
6
VDD
GND
nQ3
Q3
ICS8516-01
7
GND
nQ12
Q12
nQ13
Q13
VDD
Q0
nQ0
Q15
nQ15
8
9
Q1
nQ1
Q14
nQ14
nQ2
Q2
10
11
12
Q2
nQ2
Q13
nQ13
VDD
13 14 15 16 17 18 19 20 21 22 23 24
Q12
nQ12
Q3
nQ3
Q11
nQ11
Q4
nQ4
48-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Q10
Q5
nQ10
nQ5
Q9
nQ9
Q6
nQ6
Top View
Q8
nQ8
Q7
nQ7
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
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REV. A OCTOBER 2, 2002
1
PRELIMINARY
ICS8516-01
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 6, 12,
25, 31, 36
VDD
Power
Positive supply pins.
2, 3
4, 5
nQ5, Q5
nQ4, Q4
Output
Output
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
7, 17, 20,
30, 41, 44
GND
Power
Power supply ground.
8, 9
nQ3, Q3
nQ2, Q2
nQ1, Q1
nQ0, Q0
nCLK
Output
Output
Output
Output
Input
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Inverting differential clock input.
10, 11
13, 14
15, 16
18
Pullup
19
CLK
Input
Pulldown Non-inverting differential clock input.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
21, 22
23, 24
26, 27
28, 29
32, 33
34, 35
37, 38
39, 40
Q15, nQ15
Q14, nQ14
Q13, nQ13
Q12, nQ12
Q11, nQ11
Q10, nQ10
Q9, nQ9
Q8, nQ8
Output
Output
Output
Output
Output
Output
Output
Output
Differential output pair. LVDS interface levels.
Output enable. OE2 controls outputs Q8, nQ:Q15, nQ15; OE1
42, 43
OE2, OE1
Input
Pullup
controls outputs Q0, nQ0:Q7, nQ7.
LVCMOS interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
4
RPULLUP
RPULLDOWN
51
51
KΩ
KΩ
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PRELIMINARY
ICS8516-01
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs
Outputs
OE1
OE2
Q0:Q7
LOW
nQ0:nQ7
HIGH
Q8:Q15
LOW
nQ8:nQ15
HIGH
0
1
0
1
0
0
1
1
ACTIVE
LOW
ACTIVE
HIGH
LOW
HIGH
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling
input clock edge as shown in Figure 1.
In the active mode, the state of the outputs are a function of the CLK and nCLK inputs as described in Table 3B.
Enabled
Disabled
nCLK
CLK
CLK_EN
nQ0:nQ15
Q0:Q15
FIGURE 1 - CLK_EN TIMING DIAGRAM
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs
Outputs
Input to Output Mode
Polarity
CLK
nCLK
Q0:Q15
LOW
nQ0:nQ15
HIGH
LOW
0
1
Differential to Differential
Differential to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Non Inverting
Non Inverting
Non Inverting
Non Inverting
Inverting
1
0
HIGH
LOW
0
Biased; NOTE 1
HIGH
LOW
1
Biased; NOTE 1
HIGH
HIGH
LOW
Biased; NOTE 1
Biased; NOTE 1
0
1
LOW
HIGH
Inverting
NOTE 1: Please refer to the Application Information section "Wiring the Differential Input to Accept Single Ended Levels".
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REV. A OCTOBER 2, 2002
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PRELIMINARY
ICS8516-01
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
Inputs, VDD
Outputs, VDDO
Package Thermal Impedance, θJA
Storage Temperature, TSTG
4.6V
-0.5V to VDD + 0.5V
-0.5V to VDD + 0.5V
47.9°C/W (0 lfpm)
-65°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in
the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
3.3
Maximum Units
VDD
IDD
Positive Supply Voltage
Power Supply Current
3.135
3.465
V
140
mA
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
VIL
IIH
Input High Voltage OE1, OE2
2
VDD + 0.3
V
V
Input Low Voltage OE1, OE2
Input High Current OE1, OE2
Input Low Current OE1, OE2
-0.3
0.8
5
VDD = VIN = 3.465V
µA
µA
IIL
VDD = 3.465V, VIN = 0V
-150
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
VIN = VDD = 3.465V
VIN = VDD = 3.465V
VDD = 3.465V, VIN = 0V
VDD = 3.465V, VIN = 0V
Minimum
Typical
Maximum Units
CLK
150
5
µA
µA
µA
µA
Input High Current
IIH
nCLK
CLK
-5
IIL
Input Low Current
Differential Input
High Threshold Voltage
Differential Input
nCLK
-150
VTH
100
mV
VTL
-100
0.15
0.5
mV
V
Low Threshold Voltage
VPP
Peak-to-Peak Voltage
1.3
Common Mode Input Voltage;
NOTE 1, 2
VCMR
VDD - 0.85
V
NOTE 1: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V.
NOTE 2: Common mode voltage is defined ast VIH.
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REV. A OCTOBER 2, 2002
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PRELIMINARY
ICS8516-01
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
TABLE 4D. LVDS DC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VOD
Differential Output Voltage
247
454
50
mV
mV
V
RL = 100Ω
∆ VOD
VOS
VOD Magnitude Change
Offset Voltage
1.125
1.375
50
RL = 100Ω
∆ VOS
VOS Magnitude Change
mV
NOTE 1: Refer to the Parameter Measurement Information section, "3.3V Output Load Test Circuit".
TABLE 5. AC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
fMAX Output Frequency
tPD
Test Conditions
Minimum
Typical
Maximum Units
700
1.9
MHz
ns
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Output Rise Time
1.3
tsk(o)
tsk(pp)
tR
80
120
500
600
600
55
ps
ps
20% TO 80% at 50MHz
20% TO 80% at 50MHz
200
200
45
450
450
ps
tF
Output Fall Time
ps
odc
Output Duty Cycle
%
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
8516FY-01
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REV. A OCTOBER 2, 2002
5
PRELIMINARY
ICS8516-01
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
PARAMETER MEASUREMENT INFORMATION
SCOPE
Qx
LVDS
3.3V±5% POWER SUPPLY
Float GND
+
-
nQx
3.3V OUTPUT LOAD AC TEST CIRCUIT
VDD
nCLK
CLK
VPP
VCMR
Cross Points
GND
DIFFERENTIAL INPUT LEVEL
nQx
Qx
nQy
Qy
tsk(o)
OUTPUT SKEW
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PRELIMINARY
ICS8516-01
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
nQx
PART1
Qx
nQy
PART2
Qy
tsk(pp)
PART-TO-PART SKEW
80%
80%
VSWING
20%
20%
Clock Outputs
tR
tF
OUTPUT RISE AND FALL TIME
nCLK
CLK
nQ0:nQ15
Q0:Q15
tPD
PROPAGATION DELAY
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REV. A OCTOBER 2, 2002
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PRELIMINARY
ICS8516-01
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
nQ0:nQ15
Q0:Q15
Pulse Width
tPERIOD
tPW
odc =
tPERIOD
odc & tPERIOD
VDD
out
out
➤
DC Input
LVDS
VOS/∆ VOS
➤
VOS / DVOS SETUP
VDD
➤
out
out
DC Input
100
VOD/∆ VOD
LVDS
➤
VOD / DVOD SETUP
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PRELIMINARY
ICS8516-01
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock
swing is only 2.5V and VDD= 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VDD
R1
1K
CLK_IN
+
V_REF
-
C1
0.1uF
R2
1K
FIGURE 2 - SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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PRELIMINARY
ICS8516-01
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
SCHEMATIC EXAMPLE
Figure 3 shows a schematic example of ICS8516-01. In this example, the input is driven by an LVDS driver. For LVDS buffer, it is
recommended to terminate the unused outputs for better signal integrity. The decoupling capacitors should be physically located
near the power pin.
Zo = 50 Ohm
+
R16
100
VDD=3.3V
-
Zo = 50 Ohm
LVDS_input
U1
8516
Zo = 50 Ohm
Zo = 50 Ohm
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
nQ1
Q1
nQ0
Q0
GND
nCLK
CLK
GND
Q15
nQ15
Q14
nQ14
Q6
nQ6
Q7
nQ7
GND
OE1
OE2
GND
nQ8
Q8
+
-
R10
100
LVDS_Driver
Zo = 50 Ohm
LVDS_input
R17
100
nQ9
Q9
Zo = 50 Ohm
Zo = 50 Ohm
+
-
R1
100
Zo = 50 Ohm
LVDS_input
(U1-1)
(U1-6)
(U1-12)
(U1-25)
(U1-31)
(U1-36)
VDD=3.3V
C1
0.1u
C2
0.1u
C3
0.1u
C4
0.1u
C5
0.1u
C6
0.1u
Decoupling capacitors located near the power pins
FIGURE 3 - ICS8516-01 LVDS BUFFER SCHEMATIC EXAMPLE
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PRELIMINARY
ICS8516-01
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
CLOCK INPUT INTERFACE
Additional interface examples for the ICS8516-01 clock input driven by various types of driver are shown in Figures 4 to 7. The
input interfaces suggest here are examples only. Please consult with the vendor of the driver component to confirm the driver
termination requirement.
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
HiPerClockS
LVHSTL
Input
R1
50
R2
50
FIGURE 4 - ICS8516-01 CLK/NCLK INPUT DRIVEN BY LVHSTL DRIVER
3.3V
3.3V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
HiPerClockS
LVPECL
Input
R1
50
R2
50
R3
50
FIGURE 5 - ICS8516-01 CLK/NCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER
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PRELIMINARY
ICS8516-01
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
3.3V
3.3V
3.3V
R3
125
R4
125
Zo = 50 Ohm
Zo = 50 Ohm
CLK
nCLK
HiPerClockS
Input
LVPECL
R1
84
R2
84
FIGURE 6 - ICS8516-01 CLK/NCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
R3
125
R4
125
C1
C2
LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
CLK
nCLK
HiPerClockS
Input
R5
100 - 200
R6
100 - 200
R1
84
R2
84
R5,R6 locate near the driver pin.
FIGURE 7 - ICS8516-01 CLK/NCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER WITH AC COUPLE
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PRELIMINARY
ICS8516-01
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE
qJA by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
55.9°C/W
42.1°C/W
50.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8516-01 is: 1414
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PRELIMINARY
ICS8516-01
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
PACKAGE OUTLINE - Y SUFFIX
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBC
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
48
--
--
--
1.60
0.15
1.45
0.27
0.20
A1
A2
b
0.05
1.35
0.17
0.09
1.40
0.22
c
--
D
9.00 BASIC
7.00 BASIC
5.50 Ref.
9.00 BASIC
7.00 BASIC
5.50 Ref.
0.50 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0.75
q
--
0°
7°
ccc
--
--
0.08
Reference Document: JEDEC Publication 95, MS-026
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PRELIMINARY
ICS8516-01
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
TABLE 8. ORDERING INFORMATION
Part/Order Number
ICS8516FY-01
Marking
Package
48 Lead LQFP
Count
250 per tray
1000
Temperature
0°C to 70°C
0°C to 70°C
ICS8516FY-01
ICS8516FY-01
ICS8516FY-01T
48 Lead LQFP on Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
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REV. A OCTOBER 2, 2002
15
相关型号：
ICS8520CY
Low Skew Clock Driver, 16 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, LQFP-48
IDT
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