ICS85211AM-01 [IDT]
Low Skew Clock Driver, 2 True Output(s), 0 Inverted Output(s), PDSO8, 3.90 X 4.90 MM, 1.37 MM HEIGHT, SOIC-8;
| 型号： | ICS85211AM-01 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew Clock Driver, 2 True Output(s), 0 Inverted Output(s), PDSO8, 3.90 X 4.90 MM, 1.37 MM HEIGHT, SOIC-8 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总12页 (文件大小：134K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS85211-01
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
FEATURES
GENERAL DESCRIPTION
• 2 differential LVHSTLcompatible outputs
The ICS85211-01 is a low skew, high perfor-
mance 1-to-2 Differential-to-LVHSTL Fanout
Buffer and a member of the HiPerClockS™
family of High Performance Clock Solutions
from ICS. The CLK, nCLK pair can accept most
• 1 differential CLK, nCLK input pair
HiPerClockS™
• CLK, nCLK pair can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
standard differential input levels.The ICS85211-01 is
characterized to operate from a 3.3V power supply.
Guaranteed output and part-to-part skew char-
acteristics make the ICS85211-01 ideal for those clock
distribution applications demanding well defined
performance and repeatability. For optimal performance,
terminate all outputs.
• Maximum output frequency: 650MHz
• Translates any single-ended input signal to LVHSTL
levels with resistor bias on nCLK input
• Output skew: TBD
• Part-to-part skew: TBD
• Propagation delay: 880ps (typical)
• VOH = 1.4V (maximum)
• 3.3V operating supply
• 0°C to 85°C ambient operating temperature
• Industrial temperature information available upon request
BLOCK DIAGRAM
PIN ASSIGNMENT
Q0
nQ0
Q1
VDD
1
2
3
4
8
7
6
5
Q0
nQ0
CLK
nCLK
GND
CLK
nCLK
Q1
nQ1
nQ1
ICS85211-01
8-Lead SOIC
3.90mm x 4.90mm x 1.37mm package body
M Package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
85211AM-01
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REV. A JANUARY 3, 2003
1
PRELIMINARY
ICS85211-01
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Q0, nQ0
Q1, nQ1
GND
Type
Description
1, 2
3, 4
5
Output
Output
Power
Input
Differential output pair. LVHSTL interface levels.
Differential output pair. LVHSTL interface levels.
Power supply ground.
6
nCLK
CLK
VDD/2
Inverting differential clock input. VDD/2 default when left floating.
7
Input
Pulldown Non-inverting differential clock input.
Positive supply pin.
8
VDD
Power
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum Typical
Maximum Units
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
4
pF
KΩ
KΩ
RPULLUP
RPULLDOWN
51
51
TABLE 3. CLOCK INPUT FUNCTION TABLE
Inputs
Outputs
Q0, Q1 nQ0, nQ1
Input to Output Mode
Polarity
CLK
nCLK
0
0
LOW
HIGH
LOW
HIGH
HIGH
LOW
HIGH
LOW
HIGH
LOW
LOW
HIGH
Differential to Differential
Differential to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Non Inverting
Non Inverting
Non Inverting
Non Inverting
Inverting
1
1
0
Biased; NOTE 1
1
Biased; NOTE 1
Biased; NOTE 1
Biased; NOTE 1
0
1
Inverting
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".
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REV. A JANUARY 3, 2003
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PRELIMINARY
ICS85211-01
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
Inputs, VDD
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
-0.5V to VDD + 0.5 V
-0.5V to VDD + 0.5V
Outputs, VDD
Package Thermal Impedance, θJA 112.7°C/W (0 lfpm)
StorageTemperature, TSTG -65°C to 150°C
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V ± 5%, TA = 0°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VDD
IDD
Power Supply Voltage
Power Supply Current
3.135
3.3
3.465
TBD
V
mA
TABLE 4B. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V ± 5%, TA = 0°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
nCLK
CLK
V
DD = VIN = 3.465V
150
150
µA
µA
µA
µA
V
IIH
Input High Current
V
DD = VIN = 3.465V
nCLK
CLK
V
DD = 3.465V, VIN = 0V
DD = 3.465V, VIN = 0V
-150
-5
IIL
Input Low Current
V
VPP
Peak-to-Peak Input Voltage
0.15
1.3
Common Mode Input Voltage;
NOTE 1, 2
VCMR
0.5
VDD - 0.85
V
NOTE 1: For single ended applications the maximum input voltage for CLK and nCLK is VDD + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
TABLE 4C. LVHSTL DC CHARACTERISTICS, VDD = 3.3V ± 5%, TA = 0°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VOH
Output High Voltage; NOTE 1
1.0
0
1.4
0.4
0.9
1.0
V
V
V
V
VOL
Output Low Voltage; NOTE 1
Output Crossover Voltage
VOX
0.68
0.4
VSWING
Peak-to-Peak Output Voltage Swing
0.8
NOTE 1: All outputs must be terminated with 50Ω to ground.
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REV. A JANUARY 3, 2003
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PRELIMINARY
ICS85211-01
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
TABLE 5. AC CHARACTERISTICS, VDD = 3.3V ± 5%, TA = 0°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
fMAX
Output Frequency
650
MHz
ps
tPD
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Output Rise/Fall Time
IJ 650MHz
880
tsk(o)
tsk(pp)
tR / tF
odc
TBD
TBD
500
ps
ps
20% to 80%
200
ps
Output Duty Cycle
50
%
All parameters measured at 500MHz unless noted otherwise.
The cycle-to-cycle jitter on the input will equal the jitter on the output. The part does not add jitter.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
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PRELIMINARY
ICS85211-01
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
VDD = 3.3V±5%
VDD
SCOPE
Qx
nCLK
CLK
LVHSTL
VPP
VCMR
Cross Points
nQx
GND
GND = 0V
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx
Qx
Qx
PART 1
nQx
Qy
nQy
PART 2
nQy
Qy
tsk(pp)
tsk(o)
OUTPUT SKEW
PART-TO-PART SKEW
nCLK
CLK
80%
80%
VSWING
20%
20%
nQ0, nQ1
Clock Outputs
t
t
F
R
Q0, Q1
tPD
OUTPUT RISE/FALL TIME
PROPAGATION DELAY
nQ0, nQ1
Q0, Q1
Pulse Width
tPERIOD
tPW
odc =
tPERIOD
odc & tPERIOD
85211AM-01
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REV. A JANUARY 3, 2003
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PRELIMINARY
ICS85211-01
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept of R1 and R2 might need to be adjusted to position the V_REF in
single ended levels. The reference voltage V_REF = VDD/2 is the center of the input voltage swing. For example, if the input
generated by the bias resistors R1, R2 and C1. This bias circuit clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V
should be located as close as possible to the input pin. The ratio and R2/R1 = 0.609.
VDD
R1
1K
CLK_IN
+
V_REF
-
C1
0.1uF
R2
1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
SCHEMATIC EXAMPLE
Figure 2 shows a schematic example of ICS85211-01. In this
example, the input is driven by an ICS HiPerClockS LVHSTL
driver. The decoupling capacitors should be physically located
near the power pin. For ICS85211-01, the unused outputs need
to be terminated.
Zo = 50 Ohm
1.8V
-
U1
Zo = 50 Ohm
Zo = 50 Ohm
5
6
7
8
4
3
2
1
Zo = 50 Ohm
GND
nCLK
CLK
nQ1
Q1
nQ0
Q0
+
VDD
R1
50
R2
50
LVHSTL Input
VDD=3.3V
LVHSTL
ICS
ICS85211-03
R6
50
R5
50
C1
0.1u
Zo = 50 Ohm
Zo = 50 Ohm
HiPerClockS
LVHSTL Driver
-
+
R3
50
R4
50
LVHSTL Input
FIGURE 2. ICS85211-01 LVHSTL BUFFER SCHEMATIC EXAMPLE
85211AM-01
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REV. A JANUARY 3, 2003
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PRELIMINARY
ICS85211-01
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
CLOCK INPUT INTERFACE
The CLK /nCLK accepts differential input signals of both VSWING component to confirm the driver termination requirement. For ex-
and VOH meet the VPP and VCMR input requirements. Figures 3 to 6 ample in Figure 3, the input termination applies for ICS
show interface examples for the ICS85211-01 clock input driven HiPerClockS LVHSTLdrivers. If you are using an LVHSTLdriver
from another vendor, use their termination recommendation.
by most common driver types. The input interfaces suggest here
are examples only. Please consult with the vendor of the driver
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
HiPerClockS
LVPECL
Input
nCLK
HiPerClockS
LVHSTL
Input
R1
50
R2
50
ICS
R1
50
R2
50
HiPerClockS
LVHSTL Driver
R3
50
FIGURE 3. ICS85211-01 CLK/NCLK INPUT DRIVEN BY
HIPERCLOCKS LVHSTL DRIVER
FIGURE 4. ICS85211-01 CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
R3
R4
R3
125
R4
125
125
125
Zo = 50 Ohm
Zo = 50 Ohm
C1
C2
LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
nCLK
nCLK
HiPerClockS
Input
HiPerClockS
Input
LVPECL
R5
100 - 200
R6
100 - 200
R1
84
R2
84
R1
84
R2
84
R5,R6 locate near the driver pin.
FIGURE 5. ICS85211-01 CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 6. ICS85211-01 CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER WITH AC COUPLE
85211AM-01
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REV. A JANUARY 3, 2003
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PRELIMINARY
ICS85211-01
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85211-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS85211-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * TBDmA = TBDmW
Power (outputs)MAX = 82.34mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 82.34mW = 164.7mW
Total Power_MAX (3.465V, with all outputs switching) = TBDmW + 164.7mW = TBDmW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA =Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.TBDW * 103.3°C/W = TBD°C. This is well below the limit of 125°C
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE qJA FOR 8-PIN SOIC, FORCED CONVECTION
qJA by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
153.3°C/W
112.7°C/W
128.5°C/W
103.3°C/W
115.5°C/W
97.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
85211AM-01
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PRELIMINARY
ICS85211-01
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVHSTL output driver circuit and termination are shown in Figure 7.
VDD
Q1
VOUT
RL
50
Ω
FIGURE 7. LVHSTL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load.
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = (V
Pd_L = (V
/R ) * (V
- V
)
OH_MAX
OH_MAX
DD_MAX
L
/R ) * (V
- V
)
OL_MAX
DD_MAX
OL_MAX
L
Pd_H = (1.4V/50Ω) * (3.465V - 1.4V) = 57.82mW
Pd_L = (0.4V/50Ω) * (3.465V - 0.4V) = 24.52mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 82.34mW
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PRELIMINARY
ICS85211-01
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE
qJA by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
153.3°C/W
128.5°C/W
115.5°C/W
112.7°C/W
103.3°C/W
97.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS85211-01 is: 411
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REV. A JANUARY 3, 2003
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PRELIMINARY
ICS85211-01
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
PACKAGE OUTLINE - M SUFFIX
TABLE 8. PACKAGE DIMENSIONS
Millimeters
SYMBOL
MINIMUN
MAXIMUM
N
A
A1
B
C
D
E
e
8
1.35
0.10
0.33
0.19
4.80
3.80
1.75
0.25
0.51
0.25
5.00
4.00
1.27 BASIC
H
h
5.80
0.25
0.40
0°
6.20
0.50
1.27
8°
L
α
Reference Document: JEDEC Publication 95, MS-012
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REV. A JANUARY 3, 2003
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PRELIMINARY
ICS85211-01
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
TABLE 9. ORDERING INFORMATION
Part/Order Number
ICS85211AM-01
ICS85211AM-01T
Marking
Package
8 lead SOIC
Count
96 per tube
2500
Temperature
0°C to 85°C
0°C to 85°C
5211A01
5211A01
8 lead SOIC on Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement
of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications.
Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by
ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
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REV. A JANUARY 3, 2003
12
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