ICS8521AY [IDT]
Low Skew Clock Driver, 9 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, LQFP-32;
| 型号： | ICS8521AY |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew Clock Driver, 9 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, LQFP-32 驱动 逻辑集成电路 |
| 文件： | 总6页 (文件大小：189K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8521
LOW SKEW 1-TO-9 LVHSTL
FANOUT BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS8521 is a very low skew, 1-to-9 LVHSTL • 9 LVHSTL outputs each with the ability to drive 50Ω to ground
,&6
Fanout Buffer and a member of the
• Selectable differential HSTL or PECL clock inputs
HiPerClockS family of High Performance
HiPerClockS™
Clock Solutions from ICS. The ICS8521 has
selectable clock inputs that accept either HSTL
or PECL input levels. The output enable is synchronous which
eliminates the runt clock pulses which occur during asyn-
chronous enabling and disabling of the outputs.
• Voh(max) = 1.2V
• 0.68V ≤ Vcrossover ≤ 0.9V
• Output frequency up to 500MHz
• 50ps output skew
Guaranteed output skew, part-to-part skew and crossover
voltage characteristics make the ICS8521 ideal for interfac-
ing to todays most advanced microprocessor and static
RAMs.
• 3.3V core, 1.8V output operating supply voltages
• 32 lead low-profile QFP(LQFP), 7mm x 7mm x 1.4mm
package body, 0.8mm package lead pitch
• 0°C to 70°C ambient operating temperature
BLOCK DIAGRAM
PIN ASSIGNMENT
nD
LE
OE
Q
32 31 30 29 28 27 26 25
HCLK
nHCLK
PCLK
0
1
Q0
nQ0
VCC
HSTL_CLK
nHSTL_CLK
CLK_SEL
PECL_CLK
nPECL_CLK
GND
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
VCCO
Q3
nPCLK
Q1
nQ1
nQ3
Q4
CLK_SEL
ICS8521
Q2
nQ2
nQ4
Q5
nQ5
VCCO
Q3
nQ3
OE
9 10 11 12 13 14 15 16
Q4
nQ4
Q5
nQ5
Q6
nQ6
32-Lead LQFP
Y Package
Top View
Q7
nQ7
Q8
nQ8
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
8521
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REV. A - AUGUST 1, 2000
1
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8521
LOW SKEW 1-TO-9 LVHSTL
FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
VCC
Power
Input power supply. Connect to 3.3V.
2
3
HCLK
Input
Input
Pulldown
Pullup
Non-inverting differential HSTL clock input.
Inverting differential HSTL clock input.
nHCLK
Selects between HSTL or PECL clock inputs. LVTTL / LVCMOS interface
levels.
4
CLK_SEL
Input
Pullup
5
6
7
PCLK
nPCLK
GND
Input
Input
Pulldown
Pullup
Non-inverting differential PECL clock input.
Inverting differential PECL clock input.
Power supply ground. Connect to ground.
Power
Synchronous control for enabling and disabling clock outputs. LVTTL /
LVCMOS interface levels.
8
OE
Input
Pullup
9, 16, 17,
24, 25, 32
VCCO
Power
Output power supply. Connect to 1.8V.
10, 11
12, 13
14, 15
18, 19
20, 21
22, 23
26, 27
28, 29
30, 31
nQ8, Q8
nQ7, Q7
nQ6, Q6
nQ5, Q5
nQ4, Q4
nQ3 Q3
nQ2, Q2
nQ1, Q1
nQ0, Q0
Output
Output
Output
Output
Output
Output
Output
Output
Output
Differential output pair. LVHSTL interface level.
Differential output pair. LVHSTL interface level.
Differential output pair. LVHSTL interface level.
Differential output pair. LVHSTL interface level.
Differential output pair. LVHSTL interface level.
Differential output pair. LVHSTL interface level.
Differential output pair. LVHSTL interface level.
Differential output pair. LVHSTL interface level.
Differential output pair. LVHSTL interface level.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum
Typical
TBD
Maximum
Units
pF
CIN
Input Capacitance
Output Capacitance
COUT
TBD
pF
TABLE 3A. CONTROL INPUTS FUNCTION TABLE
Inputs
Outputs
OE
0
CLK_SEL
Q0 thru Q8
nQ0 thru nQ8
HIGH
0
1
0
1
LOW
LOW
Active
Active
0
HIGH
1
Active
1
Active
In the active mode the state of the output is a function of the HCLK , nCLK and PCLK, nPCLK inputs as described in Table 3B.
TABLE 3B. CLOCK INPUTS FUNCTION TABLE
Inputs
Outputs
Input to Output Mode
Polarity
HCLK or PCLK
nHCLK or nPCLK
Q0 thru Q8
LOW
nQ0 thru nQ8
HIGH
0
1
Differential to Differential
Differential to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Non Inverting
Non Inverting
Non Inverting
Non Inverting
Inverting
1
0
HIGH
LOW
0
Biased; NOTE 1
LOW
HIGH
1
Biased; NOTE 1
HIGH
LOW
Biased; NOTE 1
Biased; NOTE 1
0
1
HIGH
LOW
LOW
HIGH
Inverting
NOTE 1: Single ended use requires that one of the differential inputs be biased. The voltage at the biased input sets the switch point for the
single ended input. For LVCMOS and LVTTL levels the recommended input bias network is a resistor to VCC, a resistor of equal value to
ground and a 0.1µF capacitor from the input to ground. The resulting switch point is approximately VCC/2 ± 300mV.
8521
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REV. A - AUGUST 1, 2000
2
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8521
LOW SKEW 1-TO-9 LVHSTL
FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
4.6V
Inputs
Outputs
-0.5V to VDD + 0.5V
-0.5V to VDDO + 0.5V
0°C to 70°C
Ambient Operating Temperature
Storage Temperature
-65°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only and functional operation of product at these condition or any conditions beyond those listed in the DC Electrical
Characteristics or AC Electrical Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect product reliability.
TABLE 4. DC ELECTRICAL CHARACTERISTICS, VCC=3.3V±5%, VCCO=1.8V±10%, TA=0°C TO 70°C
Symbol
Parameter
Test Conditions
Minimum
3.135
1.6
Typical
3.3
Maximum
3.465
2.0
Units
V
VCC
Input Power Supply Voltage
Output Power Supply Voltage
Input Power Supply Current
VCCO
ICC
1.8
V
50
70
mA
HSTL DC Characteristics
VX
Input Crossover Voltage
3.135V ≤ VCC ≤ 3.465V
3.135V ≤ VCC ≤ 3.465V
3.135V ≤ VCC ≤ 3.465V
3.135V ≤ VCC ≤ 3.465V
3.135V ≤ VCC ≤ 3.465V
3.135V ≤ VCC ≤ 3.465V
3.135V ≤ VCC ≤ 3.465V
1.6V ≤ VCCO ≤ 2V
0.68
Vx + 0.1
-0.3
0.9
1.6
V
V
VIH
VIL
Input High Voltage
Input Low Voltage
Vx - 0.1
150
V
HCLK
nHCLK
HCLK
µA
µA
µA
µA
V
IIH
IIL
Input High Current
Input Low Current
1
1
-150
1.0
0
nHCLK
VOH
VOL
Output High Voltage
Output Low Voltage
1.2
0.4
1.6V ≤ VCCO ≤ 2V
V
40% x
(VOH-VOL)
+
60% x
(VOH-VOL)
+
VOX
Output Crossover Voltage
1.6V ≤ VCCO ≤ 2V
V
VOL
VOL
PECL DC Characteristics
VIH
VIL
Input High Voltage
3.135V ≤ VCC ≤ 3.465V
3.135V ≤ VCC ≤ 3.465V
3.135V ≤ VCC ≤ 3.465V
3.135V ≤ VCC ≤ 3.465V
3.135V ≤ VCC ≤ 3.465V
3.135V ≤ VCC ≤ 3.465V
2.135
1.49
2.42
1.825
150
1
V
V
Input Low Voltage
PCLK
nPCLK
PCLK
µA
µA
µA
µA
mV
V
IIH
IIL
Input High Current
1
Input Low Current
nPCLK
-150
VPP
Peak-to-Peak Input Voltage
Common Mode Input Voltage
600
VCMR
1.5
VCC - 0.2
8521
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REV. A - AUGUST 1, 2000
3
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8521
LOW SKEW 1-TO-9 LVHSTL
FANOUT BUFFER
TABLE 5. AC ELECTRICAL CHARACTERISTICS, VCC=3.3V±5%, VCCO=1.8V±10%, TA=0°C TO 70°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
fMAX
Maximum Input Frequency
500
MHz
Propagation Delay, Low-to-High
NOTE 2
Propagation Delay, High-to-Low
NOTE 2
tpLH
tpHL
0 < f ≤ 250MHz
0 < f ≤ 250MHz
1
1
1.6
1.6
ns
ns
tsk(o)
tsk(pp)
tR
Output Skew; NOTE 3
Part-to-Part Skew; NOTE 4
Output Rise Time
50
TBD
800
800
ps
ps
ps
ps
300
300
tF
Output Fall Time
tCYCLE/2
- TBD
tCYCLE/2
+ TBD
tPW
Output Pulse Width
tCYCLE/2
ns
tS
tH
Output Enable Setup Time
Output Enable Hold Time
1
ns
ns
0.5
NOTE 1: All parameters measured at 250MHz unless noted otherwise.
NOTE 2: Measured from the differential input crossing point to the differential output crossing point.
NOTE 3: Defined as skew across outputs at the same supply voltages and with equal load conditions. Measured from the differential input
crossing point to the differential output crossing point.
NOTE 4: Defined as skew at different outputs on different devices operating at the same supply voltages and with equal load conditions.
Measured from the differential input crossing point to the differential output crossing point.
FIGURE 1A, 1B - INPUT CLOCK WAVEFORMS
VCC
CLK
CROSS POINTS
VPP
VCMR
nCLK
GND
FIGURE 1A - HSTL DIFFERENTIAL INPUT LEVELS
VCC
CLK
CROSS POINTS
VCMR
VPP
nCLK
GND
FIGURE 1B - LVPECL DIFFERENTIAL INPUT LEVEL
8521
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REV. A - AUGUST 1, 2000
4
Integrated
Circuit
Systems, Inc.
ICS8521
LOW SKEW 1-TO-9 LVHSTL
FANOUT BUFFER
PACKAGE OUTLINE AND DIMENSIONS - Y SUFFIX
e / 2
NOTE 4
D
NOTE 5, 7
D1
D/2
NOTE 3
-D-
-A, B, OR -D-
D1/2
b
NOTE 3
-A-
NOTE 3
-B-
E1
E
e
-A, B, OR -D-
N
O
T
N
O
T
E
4
NOTES:
1. ALL DIMENSIONS AND TOLERANCING CONFORM TO
ANSI Y14.5-1982
E
5,
7
2. DATUM PLANE -H- LOCATED AT MOLD PARTING
LINE AND COINCIDENT WITH LEAD, WHERE LEAD
EXITS PLASTIC BODY AT BOTTOM OF PARTING LINE.
3. DATUMS A-B AND -D- TO BE DETERMINED AT
CENTERLINE BETWEEN LEADS WHERE LEADS EXIT
E/2
N/4 TIPS
4X
0.20 C A-B D
E1/2
PLASTIC AT DATUM PLANE -H-
.
4. TO BE DETERMINED AT SEATING PLACE -C-
.
5. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD
PROTRUSION.
SEE DETAIL “A”
6. N IS THE TOTAL NUMBER OF TERMINALS.
7. THESE DIMENSIONS TO BE DETEREMINED AT DATUM
PLANE -H-.
8 PLACES
11 / 13°
8. PACKAGE TOP DIMENSIONS ARE SMALLER THAN
BOTTOM DIMENSIONS AND TOP OF PACKAGE WILL
NOT OVERHANG BOTTOM OF PACKAGE.
9. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.08mm TOTAL IN EXCESS OF THE b
DIMENSION AT MAXIMUM MATERIAL CONDITION.
10. CONTROLLING DIMENSION: MILLIMETER.
11. THIS OUTLINE CONFORMS TO JEDEC PUBLIBCATION
95 REGISTRATION MS-026, VARIATION ABA.
12. A1 IS DEFINED AS THE DISTANCE FROM THE
SEATING PLANE TO THE LOWEST POINT OF THE
PACKAGE.
A
-H- NOTE 2 / / 0.10 C
ccc
-C-
SEE DETAIL “B”
S
Y
M
B
O
L
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
NOTE 9
b
ddd M C A-B S D S
WITH LEAD FINISH
N
O
T
BBA
E
MIN
NOM
MAX
1.60
0.15
1.45
0.09 / 0.20
0.09 / 0.16
A
A1
A2
D
0.05
1.35
12
b1
BASE MET AL
1.4
9.00 BSC.
7.00 BSC.
9.00 BSC.
7.00 BSC.
0.60
4
D1
E
7, 8
4
0° MIN.
- 0.05 S
E1
L
7, 8
0.08/0.20 R.
0.25
GAUGE PLANE
DATUM
A2
A1
PLANE
-H-
0.45
0.75
N
32
e
0.80 BSC.
0.37
0.08
R. MIN.
0° - 7 °
b
0.30
0.30
0.45
0.40
0.10
0.20
0.20 MIN.
L
b1
ccc
ddd
0.35
9
1.00 REF.
8521
www.icst.com
REV. A - AUGUST 1, 2000
5
Integrated
Circuit
Systems, Inc.
ICS8521
LOW SKEW 1-TO-9 LVHSTL
FANOUT BUFFER
ORDERING INFORMATION
Part/Order Number
ICS8521AY
Marking
ICS8521AY
ICS8521AY
Package
32 Lead LQFP
Count
250 per tray
2000
Temperature
0°C to 70°C
0°C to 70°C
ICS8521AYYT
32 Lead LQFP on Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its
use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for
use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental
requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize
or warrant any ICS product for use in life support devices or critical medical instruments.
8521
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REV. A - AUGUST 1, 2000
6
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