ICS85356AGILFT [IDT]
Low Skew Clock Driver, 85356 Series, 2 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-20;
| 型号： | ICS85356AGILFT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew Clock Driver, 85356 Series, 2 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-20 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总15页 (文件大小：1109K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2:1, Differential-to-3.3V Dual LVPECL/ECL
Clock Multiplexer
ICS85356I
DATA SHEET
General Description
Features
The ICS85356I is a dual 2:1 Differential-to-LVPECL
Multiplexer. The device has both common select and
individual select inputs. When COM_SEL is logic High,
the CLKxx input pairs will be passed to the output.
When COM_SEL is logic Low, the output is
• High speed differential muliplexer. The device can be configured
as a 2:1 multiplexer
S
IC
HiPerClockS™
• Dual 3.3V LVPECL outputs
• Selectable differential CLKx/nCLKx input pairs
• Differential CLKx/nCLKx pairs can accept the following interface
determined by the setting of the SEL0 pin for channel 0 and the
SEL1 pin for Channel 1.
levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
• Output frequency: 900MHz (typical)
The differential input has a common mode range that can accept
most differential input types such as LVPECL, LVDS, LVHSTL,
SSTL, and HCSL. The ICS85356I can therefore be used as a
differential translator to translate almost any differential input type to
LVPECL. It can also be used in ECL mode by setting VCC = 0V and
• Translates any single-ended input signal to 3.3V LVPECL levels
with resistor bias on nCLKx input
• Output skew: 75ps (typical)
• Propagation delay: 1.15ns (typical)
V
EE to -3.0V to - 3.8V.
• LVPECL mode operating voltage supply range:
VCC = 3V to 3.8V, VEE = 0V
The ICS85356I adds negligible jitter to the input clock and can
operate at high frequencies in excess of 900MHz thus making
it ideal for use in demanding applications such as SONET,
Fibre Channel, 1 Gigabit/10 Gigabit Ethernet.
• ECL mode operating voltage supply range:
VCC = 0V, VEE = -3V to -3.8V
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Block Diagram
Pin Assignment
Pulldown
CLK0A
CLK0A
nCLK0A
nc
1
2
20
19
VCC
Q0
0
Pullup
nCLK0A
Q0
3
4
18
17
nQ0
SEL0
Pulldown
Pullup
CLK0B
CLK0B
nQ0
CLK0B
1
nCLK0B
CLK1A
nCLK1A
5
6
7
16 COM_SEL
15
14
13
SEL1
VCC
Pullup
SEL0
COM_SEL
SEL1
Q1
nc
CLK1B
nCLK1B
8
Pulldown
Pullup
9
10
12 nQ1
11
VEE
ICS85356I
Pulldown
Pullup
CLK1A
0
1
nCLK1A
20-Lead SOIC
7.5mm x 12.8mm x 2.3mm package body
M Package
Q1
Pulldown
Pullup
CLK1B
CLK1B
nQ1
Top View
ICS85356I
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm package body
G Package
Top View
ICS85356AMI REVISION B MAY 10, 2010
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©2010 Integrated Device Technology, Inc.
ICS85356I Data Sheet
2:1, DIFFERENTIAL-TO-3.3V LVPECL/ECL CLOCK MULTIPLEXER
Table 1. Pin Descriptions
Number
Name
VCC
Type
Description
14, 20
Power
Input
Positive supply pins.
1
2
CLK0A
nCLK0A
nc
Pulldown
Non-inverting differential clock input.
Inverting differential clock input.
No connect.
Input
Pullup
3, 8
Unused
4
CLK0B
Input
Pulldown
Non-inverting differential clock input.
5
6
nCLK0B
CLK1A
nCLK1A
CLK1B
nCLK1B
VEE
Input
Input
Input
Input
Input
Power
Output
Input
Pullup
Pulldown
Pullup
Inverting differential clock input.
Non-inverting differential clock input.
Inverting differential clock input.
7
9
Pulldown
Pullup
Non-inverting differential clock input.
Inverting differential clock input.
10
11
Negative supply pin.
12, 13
15, 17
nQ1,Q1
Differential output pair. LVPECL interface levels.
Clock select inputs. LVCMOS/LVTTL interface levels.
Pullup
SEL1, SEL0
16
Input
Pulldown
Common select input. LVCMOS/LVTTL interface levels.
Differential output pair. LVPECL interface levels.
COM_SEL
nQ0,Q0
18, 19
Output
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
Input Capacitance
Input Pullup Resistor
4
RPULLUP
51
51
kΩ
RPULLDOWN Input Pulldown Resistor
kΩ
Function Tables
Table 3. Control Input Function Table
Inputs
Outputs
COM_SEL
SEL1
SEL0
Q0
CLK0A
nQ0
Q1
nQ1
0
0
0
0
1
0
0
1
1
x
0
1
0
1
x
nCLK0A
nCLK0B
nCLK0A
nCLK0B
nCLK0B
CLK1A
CLK1A
CLK1B
CLK1B
CLK1B
nCLK1A
nCLK1A
nCLK1B
nCLK1B
nCLK1B
CLK0B
CLK0A
CLK0B
CLK0B
ICS85356AMI REVISION B MAY 10, 2010
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©2010 Integrated Device Technology, Inc.
ICS85356I Data Sheet
2:1, DIFFERENTIAL-TO-3.3V LVPECL/ECL CLOCK MULTIPLEXER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VCC
Inputs, VI
4.6V
-0.5V to VCC+ 0.5V
Outputs, IO
Continuos Current
Surge Current
50mA
100mA
Package Thermal Impedance, θJA
20 Lead SOIC
20 Lead TSSOP
46.2°C/W (0 lfpm)
73.2°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VCC = 3.3V 0.3V; VEE = 0V, TA = -40°C to 85°C
Symbol
VCC
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
V
Positive Supply Voltage
Power Supply Current
3.0
3.3
3.6
40
IEE
mA
Table 4B. LVCMOS/LVTTL DC Characteristics, VCC = 3.3V 0.3V; VEE = 0V, TA = -40°C to 85°C
Symbol
VIH
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
V
Input High Voltage
Input Low Voltage
2
VCC + 0.3
VIL
-0.3
0.8
5
V
SEL0, SEL1
COM_SEL
SEL0, SEL1
COM_SEL
VCC = VIN = 3.6V
µA
µ
Input
High Current
IIH
V
CC = VIN = 3.6V
150
VCC = 3.6V, VIN = 0V
VCC = 3.6V, VIN = 0V
-150
-5
µA
µ
Input
Low Current
IIL
ICS85356AMI REVISION B MAY 10, 2010
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©2010 Integrated Device Technology, Inc.
ICS85356I Data Sheet
2:1, DIFFERENTIAL-TO-3.3V LVPECL/ECL CLOCK MULTIPLEXER
Table 4C. Differential DC Characteristics, VCC = 3.3V 0.3V; VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
CLK0A, CLK0B,
CLK1A, CLK1B
VCC = VIN = 3.6V
150
µA
Input
High Current
IIH
nCLK0A, nCLK0B,
nCLK1A, nCLK1B
VCC = VIN = 3.6V
VCC = 3.6V, VIN = 0V
VCC = 3.6V, VIN = 0V
5
µA
µA
µA
CLK0A, CLK0B,
CLK1A, CLK1B
-5
Input
Low Current
IIL
nCLK0A, nCLK0B,
nCLK1A, nCLK1B
-150
VPP
Peak-to-Peak Voltage; NOTE 1
0.15
1.0
V
V
VCMR
Common Mode Range; NOTE 1, 2
VEE + 0.5
VCC – 0.85
NOTE 1: VIL should not be less than -0.3V
NOTE 2: Common mode voltage is defined as VIH.
Table 4D. LVPECL DC Characteristics, VCC = 3.3V 0.3V; VEE = 0V, TA = -40°C to 85°C
Symbol
VOH
Parameter
Test Conditions
Minimum
VCC – 1.4
VCC – 2.0
0.6
Typical
Maximum
VCC – 0.9
VCC – 1.7
1.0
Units
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
V
V
V
VOL
VSWING
NOTE 1: Outputs termination with 50Ω to VCC – 2V.
AC Electrical Characteristics
Table 5. AC Characteristics, VCC = 3.3V 0.3V; VEE = 0V, TA = -40°C to 85°C
Symbol
fMAX
Parameter
Test Conditions
Minimum
0.85
Typical
900
Maximum
Units
MHz
ns
Output Frequency
tPD
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 3
Output Rise/Fall Time
Output Duty Cycle Skew
ƒ ≤ 900MHz
1.15
75
1.45
150
580
100
tsk(o)
tR / tF
tODC
ps
20% to 80%
200
ps
ps
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions
NOTE: All parameters measured at ƒ ≤ 622MHz, unless otherwise noted.
NOTE: This part does not add measurable jitter.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defined according with JEDEC Standard 65.
ICS85356AMI REVISION B MAY 10, 2010
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©2010 Integrated Device Technology, Inc.
ICS85356I Data Sheet
2:1, DIFFERENTIAL-TO-3.3V LVPECL/ECL CLOCK MULTIPLEXER
Parameter Measurement Information
2V
V
CC
nCLKxA,
nCLKxB
SCOPE
Qx
VCC
VPP
VCMR
Cross Points
CLKxA,
CLKxB
LVPECL
nQx
VEE
V
EE
-1.3V ꢀ.3V
LVPECL Output Load AC Test Circuit
Differential Input Level
nQx
nQx
nQꢀ, nQ1
8ꢀ%
tF
8ꢀ%
VSWING
2ꢀ%
2ꢀ%
nQy
Qꢀ, Q1
tR
nQy
tsk(o)
Output Skew
Output Rise/Fall Time
nCLKxA,
nCLKxB
nCLKxA,
nCLKxB
CLKxA,
CLKxB
CLKxA,
CLKxB
nQꢀ, nQ1
nQꢀ, nQ1
Qꢀ, Q1
tpLH
Qꢀ, Q1
tPD
tpHL
tsk(odc) = tpLH - tpHL
Propagation Delay
Output Duty Cycle Skew
ICS85356AMI REVISION B MAY 10, 2010
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©2010 Integrated Device Technology, Inc.
ICS85356I Data Sheet
2:1, DIFFERENTIAL-TO-3.3V LVPECL/ECL CLOCK MULTIPLEXER
Application Information
Wiring the Differential Input to Accept Single-Ended Levels
Figure 1 shows how a differential input can be wired to accept single
ended levels. The reference voltage VREF = VCC/2 is generated by
the bias resistors R1 and R2. The bypass capacitor (C1) is used to
help filter noise on the DC bias. This bias circuit should be located as
close to the input pin as possible. The ratio of R1 and R2 might need
to be adjusted to position the VREF in the center of the input voltage
swing. For example, if the input clock swing is 2.5V and VCC = 3.3V,
R1 and R2 value should be adjusted to set VREF at 1.25V. The values
below are for when both the single ended swing and VCC are at the
same voltage. This configuration requires that the sum of the output
impedance of the driver (Ro) and the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination at
the input will attenuate the signal in half. This can be done in one of
two ways. First, R3 and R4 in parallel should equal the transmission
line impedance. For most 50Ω applications, R3 and R4 can be 100Ω.
The values of the resistors can be increased to reduce the loading for
slower and weaker LVCMOS driver. When using single-ended
signaling, the noise rejection benefits of differential signaling are
reduced. Even though the differential input can handle full rail
LVCMOS signaling, it is recommended that the amplitude be
reduced. The datasheet specifies a lower differential amplitude,
however this only applies to differential signals. For single-ended
applications, the swing can be larger, however VIL cannot be less
than -0.3V and VIH cannot be more than VCC + 0.3V. Though some
of the recommended components might not be used, the pads
should be placed in the layout. They can be utilized for debugging
purposes. The datasheet specifications are characterized and
guaranteed by using a differential signal.
Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels
Recommendations for Unused Input and Output Pins
Inputs:
Inputs:
CLK/nCLK Inputs
LVPECL Outputs
For applications not requiring the use of the differential input, both
CLK and nCLK can be left floating. Though not required, but for
additional protection, a 1kΩ resistor can be tied from CLK to ground.
All unused LVPECL outputs can be left floating. We recommend that
there is no trace attached. Both sides of the differential output pair
should either be left floating or terminated.
Control Pins
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional protection.
A 1kΩ resistor can be used.
ICS85356AMI REVISION B MAY 10, 2010
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©2010 Integrated Device Technology, Inc.
ICS85356I Data Sheet
2:1, DIFFERENTIAL-TO-3.3V LVPECL/ECL CLOCK MULTIPLEXER
Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both VSWING and VOH must meet the
VPP and VCMR input requirements. Figures 2A to 2F show interface
examples for the CLK/nCLK input driven by the most common
driver types. The input interfaces suggested here are examples
only. Please consult with the vendor of the driver component to
confirm the driver termination requirements. For example, in Figure
2A, the input termination applies for IDT open emitter LVHSTL
drivers. If you are using an LVHSTL driver from another vendor,
use their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50Ω
Zo = 50Ω
CLK
CLK
Zo = 50Ω
Zo = 50Ω
nCLK
Differential
Input
nCLK
LVPECL
Differential
R1
R2
LVHSTL
50Ω
50Ω
Input
R1
50Ω
R2
50Ω
IDT
LVHSTL Driver
R2
50Ω
Figure 2A. CLK/nCLK Input Driven by an
IDT Open Emitter LVHSTL Driver
Figure 2B. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
3.3V
3.3V
3.3V
3.3V
3.3V
R3
R4
Zo = 50Ω
125Ω
125Ω
Zo = 50Ω
Zo = 50Ω
CLK
CLK
R1
100
nCLK
nCLK
Zo = 50Ω
Differential
Input
LVPECL
Receiver
LVDS
R1
R2
84Ω
84Ω
Figure 2C. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
Figure 2D. CLK/nCLK Input Driven by a
3.3V LVDS Driver
2.5V
3.3V
3.3V
3.3V
2.5V
R3
R4
120Ω
120Ω
Zo = 50Ω
Zo = 60Ω
Zo = 60Ω
*R3
*R4
33Ω
33Ω
CLK
CLK
Zo = 50Ω
nCLK
nCLK
Differential
Input
SSTL
Differential
Input
HCSL
R1
50Ω
R2
50Ω
R1
120Ω
R2
120Ω
*Optional – R3 and R4 can be 0Ω
Figure 2E. CLK/nCLK Input Driven by a
3.3V HCSL Driver
Figure 2F. CLK/nCLK Input Driven by a
2.5V SSTL Driver
ICS85356AMI REVISION B MAY 10, 2010
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©2010 Integrated Device Technology, Inc.
ICS85356I Data Sheet
2:1, DIFFERENTIAL-TO-3.3V LVPECL/ECL CLOCK MULTIPLEXER
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 3A and 3B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and clock
component process variations.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50Ω
3.3V
R3
R4
3.3V
125Ω
125Ω
3.3V
3.3V
3.3V
Z
o = 50Ω
Z
o = 50Ω
+
_
+
_
Input
LVPECL
Zo = 50Ω
LVPECL
Input
Zo = 50Ω
R1
50Ω
R2
50Ω
R1
84Ω
R2
84Ω
VCC - 2V
1
RTT =
* Zo
RTT
((VOH + VOL) / (VCC – 2)) – 2
Figure 3A. 3.3V LVPECL Output Termination
Figure 3B. 3.3V LVPECL Output Termination
ICS85356AMI REVISION B MAY 10, 2010
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©2010 Integrated Device Technology, Inc.
ICS85356I Data Sheet
2:1, DIFFERENTIAL-TO-3.3V LVPECL/ECL CLOCK MULTIPLEXER
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS85356I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS85356I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 0.3V = 3.6V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.6V * 40mA = 144mW
Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power_MAX (3.6V, with all outputs switching) = 144mW + 60mW = 204mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 83.2°C/W per Table 6B below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.204W * 73.2°C/W = 99.9°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (single layer or multi-layer).
Table 6A. Thermal Resistance θJA for 20 Lead SOIC, Forced Convection
θJA by Velocity
Linear Feet per Minute
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
83.2°C/W
46.2°C/W
65.7°C/W
39.7°C/W
57.5°C/W
36.8°C/W
NOTE: Most modern PCB design use multi-layered boards. The data in the second row pertains to most designs.
Table 6B. Thermal Resistance θJA for 20 Lead TSSOP, Forced Convection
θJA by Velocity
Linear Feet per Minute
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
73.2°C/W
98.0°C/W
66.6°C/W
88.0°C/W
63.5°C/W
NOTE: Most modern PCB design use multi-layered boards. The data in the second row pertains to most designs.
ICS85356AMI REVISION B MAY 10, 2010
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©2010 Integrated Device Technology, Inc.
ICS85356I Data Sheet
2:1, DIFFERENTIAL-TO-3.3V LVPECL/ECL CLOCK MULTIPLEXER
3. Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the LVPECL output pair.
LVPECL output driver circuit and termination are shown in Figure 4.
VCC
Q1
VOUT
RL
50Ω
VCC - 2V
Figure 4. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of
VCC – 2V.
•
•
For logic high, VOUT = VOH_MAX = VCC_MAX – 0.9V
(VCC_MAX – VOH_MAX) = 0.9V
For logic low, VOUT = VOL_MAX = VCC_MAX – 1.7V
(VCC_MAX – VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX) = [(2V – (VCC_MAX – VOH_MAX))/RL] * (VCC_MAX – VOH_MAX) =
[(2V – 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOL_MAX) = [(2V – (VCC_MAX – VOL_MAX))/RL] * (VCC_MAX – VOL_MAX) =
[(2V – 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
ICS85356AMI REVISION B MAY 10, 2010
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©2010 Integrated Device Technology, Inc.
ICS85356I Data Sheet
2:1, DIFFERENTIAL-TO-3.3V LVPECL/ECL CLOCK MULTIPLEXER
Reliability Information
Table 7A. θJA vs. Air Flow Table for a 20 Lead SOIC, Forced Convection
θJA by Velocity
Linear Feet per Minute
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
83.2°C/W
46.2°C/W
65.7°C/W
39.7°C/W
57.5°C/W
36.8°C/W
NOTE: Most modern PCB design use multi-layered boards. The data in the second row pertains to most designs.
Table 7B. θJA vs. Air Flow Table for a 20 Lead TSSOP, Forced Convection
θJA by Velocity
Linear Feet per Minute
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
73.2°C/W
98.0°C/W
66.6°C/W
88.0°C/W
63.5°C/W
NOTE: Most modern PCB design use multi-layered boards. The data in the second row pertains to most designs.
Transistor Count
The transistor count for ICS85356I is: 446
ICS85356AMI REVISION B MAY 10, 2010
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©2010 Integrated Device Technology, Inc.
ICS85356I Data Sheet
2:1, DIFFERENTIAL-TO-3.3V LVPECL/ECL CLOCK MULTIPLEXER
Package Outlines and Package Dimensions
Package Outline - G Suffix for 20 Lead TSSOP
Package Outline - M Suffix for 20 Lead SOIC
Table 7A. Package Dimensions
All Dimensions in Millimeters
Table 7B. Package Dimensions for 20 Lead SOIC
300 Millimeters
All Dimensions in Millimeters
Symbol
Minimum
Maximum
Symbol
Minimum
Maximum
N
A
20
N
A
A1
A2
B
C
D
E
20
1.20
0.15
1.05
0.30
0.20
6.60
2.65
A1
A2
b
0.05
0.80
0.19
0.09
6.40
0.10
2.05
0.33
0.18
12.60
7.40
2.55
0.51
0.32
13.00
7.60
c
D
E
6.40 Basic
E1
e
4.30
4.50
e
1.27 Basic
0.65 Basic
H
h
10.00
0.25
0.40
0°
10.65
0.75
1.27
7°
L
0.45
0°
0.75
8°
α
L
aaa
0.10
α
Reference Document: JEDEC Publication 95, MO-153
Reference Document: JEDEC Publication 95, MS-013, MS-119
ICS85356AMI REVISION B MAY 10, 2010
12
©2010 Integrated Device Technology, Inc.
ICS85356I Data Sheet
2:1, DIFFERENTIAL-TO-3.3V LVPECL/ECL CLOCK MULTIPLEXER
Ordering Information
Table 8. Ordering Information
Part/Order Number
85356AMI
85356AMIT
85356AMILF
85356AMILFT
85356AGI
85356AGIT
85356AGILF
85356AGILFT
Marking
85356AMI
85356AMI
85356AMILF
85356AMILF
ICS85356AGI
ICS85356AGI
ICS85356AGIL
ICS85356AGIL
Package
20 lead SOIC
20 lead SOIC
Shipping Packaging
Tube
1000 Tape & Reel
Tube
1000 Tape & Reel
Tube
2500 Tape & Reel
Tube
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
“Lead-Free” 20 Lead SOIC
“Lead-Free” 20 Lead SOIC
20 Lead TSSOP
20 Lead TSSOP
“Lead-Free” 20 Lead TSSOP
“Lead-Free” 20 Lead TSSOP
2500 Tape & Reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without
additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support
devices or critical medical instruments.
ICS85356AMI REVISION B MAY 10, 2010
13
©2010 Integrated Device Technology, Inc.
ICS85356I Data Sheet
2:1, DIFFERENTIAL-TO-3.3V LVPECL/ECL CLOCK MULTIPLEXER
Revision History Sheet
Rev
Table
Page
Description of Change
Date
7
13
Added Differential Clock Input Interface section.
Ordering Information Table - added Lead Free part number.
Updated data sheet format.
A
10/7/04
T2
T4D
2
4
8-9
13
Pin Characteristics Table - changed CIN 4pF max, to 4pF typical.
LVPECL DC Characteristics Table - corrected VOH max. from VCC - 1.0V to VCC - 0.9V.
Power Considerations - corrected power dissipation to reflect VOH max in Table 4D.
Ordering Information Table - added ICS85356AMI lead-free part/order number and lead-free
note.
B
B
4/11/07
2/14/08
T9
3
5
6
7
9
Absolute Maximum Ratings - added TSSOP Package Thermal Impedance.
Parameter Measurement Information - corrected Output Duty Cycle Skew diagram.
Added Recommendations for Unused Input/Output Pins section.
Updated Differential Clock Input Interface section.
Power Considerations - updated Junction Temperature calculation to worst case ambient
temperature.
Updated datasheet format.
T1
T5
2
Pin Description Table - corrected nCLKx and SELx pins from Pulldown to Pullup. Made error
when converting the datasheet format.
AC Characteristics Table - added thermal note.
Updated Wiring the Differential Input to Accept Single-ended Levels.
Updated Figures 3A and 3B.
4
6
8
B
5/10/10
T8
13
Ordering Information Table - deleted “ICS” prefix for Part/Order column. Added LF marking
for SOIC, deleted “ICS” from marking for non-LF SOIC.
Updated Header/Footer of datasheet.
ICS85356AMI REVISION B MAY 10, 2010
14
©2010 Integrated Device Technology, Inc.
ICS85356I Data Sheet
2:1, DIFFERENTIAL-TO-3.3V LVPECL/ECL CLOCK MULTIPLEXER
6024 Silver Creek Valley Road Sales
Technical Support
800-345-7015 (inside USA)
netcom@idt.com
+408-284-8200 (outside USA) +480-763-2056
Fax: 408-284-2775
San Jose, California 95138
www.IDT.com/go/contactIDT
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document,
including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not
guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the
suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any
license under intellectual property rights of IDT or any third parties.
IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT
product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third
party owners.
Copyright 2009. All rights reserved.
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