ICS8535AG-21LFT [IDT]
Low Skew Clock Driver, 8535 Series, 2 True Output(s), 0 Inverted Output(s), PDSO14, 4.40 X 5 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-14;
| 型号： | ICS8535AG-21LFT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew Clock Driver, 8535 Series, 2 True Output(s), 0 Inverted Output(s), PDSO14, 4.40 X 5 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-14 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总15页 (文件大小：774K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LOW SKEW, 1-TO-2 LVCMOS/LVTTL-TO-
3.3V LVPECL CLOCK GENERATOR
ICS8535-21
General Description
Features
The ICS8535-21 is a low skew, high performance
• Two differential 3.3V LVPECL outputs
S
IC
1-to-2 LVCMOS/LVTTL-to-3.3V LVPECL fanout
buffer and a member of the HiPerClockS™family of
High Performance Clock Solutions from IDT. The
ICS8535-21 has two single-ended clock inputs. The
• Selectable CLK0 or CLK1 inputs for redundant and multiple
HiPerClockS™
frequency fanout applications
• CLK0 or CLK1 can accept the following input levels:
LVCMOS or LVTTL
single-ended clock input accepts LVCMOS or LVTTL input levels
and translate them to 3.3V LVPECL levels. The clock enable is
internally synchronized to eliminate runt clock pulses on the output
during asynchronous assertion/deassertion of the clock enable
pin.
• Maximum output frequency: 266MHz
• Translates LVCMOS and LVTTL levels to 3.3V LVPECL levels
• Output skew: 20ps (maximum)
• Part-to-part skew: 300ps (maximum)
Guaranteed output and part-to-part skew characteristics make the
ICS8535-21 ideal for those applications demanding well defined
performance and repeatability.
• Propagation delay: 1.6ns (maximum)
• Additive phase jitter, RMS: 0.03ps (typical)
• 3.3V operating supply
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
Pin Assignment
Block Diagram
VEE
CLK_EN
CLK_SEL
1
2
14 VCC
13 Q0
Pullup
CLK_EN
D
Q
Q0
3
4
5
6
7
12
LE
Pulludown
Pulludown
CLK0
VEE
11 nc
10 Q1
CLK0
CLK1
0
1
Q0
Q0
CLK1
VCC
9
8
Q1
VCC
Q1
Q1
ICS8535-21 14 Lead TSSOP
4.40mm x 5.0mm x 0.925mm package body
G Package
Pulludown
CLK_SEL
Top View
IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER
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Table 1. Pin Descriptions
Number
Name
Type
Description
1, 5
VEE
Power
Input
Negative supply pins.
Synchronizing clock enable. When HIGH, clock outputs follow clock input.
When LOW, Qx outputs are forced low, Qx outputs are forced high.
LVCMOS/LVTTL interface levels.
2
CLK_EN
Pullup
Clock select input. When HIGH, selects CLK1 input.
When LOW, selects CLK0 input. LVCMOS/LVTTL interface levels.
3
CLK_SEL
Input
Pulldown
4, 6
7, 8, 14
9, 10
11
CLK0, CLK1
VCC
Input
Power
Output
Unused
Output
Pulldown Single-ended clock inputs. LVCMOS/LVTTL interface levels.
Power supply pins.
Q1, Q1
nc
Differential output pair. LVPECL interface levels.
No connect.
12, 13
Q0, Q0
Differential output pair. LVPECL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
Input Capacitance
Input Pullup Resistor
4
RPULLUP
51
51
kΩ
RPULLDOWN Input Pulldown Resistor
kΩ
IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER
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Function Tables
Table 3A. Control Input Function Table
Inputs
Outputs
CLK_EN
CLK_SEL
Selected Source
CLK0
Q0, Q1
Disabled; Low
Disabled; Low
Enabled
Q0, Q1
Disabled; High
Disabled; High
Enabled
0
0
1
1
0
1
0
1
CLK1
CLK0
CLK1
Enabled
Enabled
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1.
In the active mode, the state of the outputs are a function of the CLK0 and CLK1 inputs as described in Table 3B.
Enabled
Disabled
CLK0, CLK1
CLK_EN
Q0, Q1
Q0, Q1
Figure 1. CLK_EN Timing Diagram
Table 3B. Clock Input Function Table
Inputs
Outputs
CLK0 or CLK1
Q0, Q1
LOW
Q0, Q1
HIGH
LOW
0
1
HIGH
IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER
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Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VCC
Inputs, VI
4.6V
-0.5V to VCC+ 0.5V
Outputs, IO
Continuos Current
Surge Current
50mA
100mA
Package Thermal Impedance, θJA
93.2°C/W (0 lfpm)
-65°C to 150°C
Storage Temperature, TSTG
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VCC = 3.3V 5%, TA = 0°C to 70°C
Symbol Parameter
VCC Positive Supply Voltage
IEE Power Supply Current
Test Conditions
Minimum
Typical
Maximum
3.465
50
Units
V
3.135
3.3
mA
Table 4B. LVCMOS/LVTTL DC Characteristics, VCC = 3.3V 5%, TA = 0°C to 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
VCC + 0.3
1.3
Units
VIH
Input High Voltage
2
V
V
CLK0, CLK1
-0.3
Input
Low Voltage
VIL
CLK_EN,
CLK_SEL
-0.3
0.8
V
CLK0, CLK1,
CLK_SEL
VCC = VIN = 3.465
VCC = VIN = 3.465
150
5
µA
µA
µA
µA
Input
High Current
IIH
CLK_EN
CLK0, CLK1,
CLK_SEL
VCC = 465V, VIN = 0V
VCC = 465V, VIN = 0V
-5
Input
Low Current
IIL
CLK_EN
-150
IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER
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Table 4C. LVPECL DC Characteristics, VCC = 5%, TA = 0°C to 70°C
Symbol
VOH
Parameter
Test Conditions
Minimum
VCC – 1.4
VCC – 2.0
0.6
Typical
Maximum
VCC – 0.9
VCC – 1.7
1.0
Units
µA
Output High Current; NOTE 1
Output Low Current; NOTE 1
Peak-to-Peak Output Voltage Swing
VOL
µA
VSWING
V
NOTE 1: Outputs termination with 50Ω to VCC – 2V.
AC Electrical Characteristics
Table 5. AC Characteristics, VCC = 3.3V 5%, TA = 0°C to 70°C
Parameter Symbol Test Conditions
fMAX Output Frequency
tPD
Minimum Typical Maximum
Units
MHz
ns
266
Propagation Delay; NOTE 1
IJ 266MHz
1.0
1.6
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section;
NOTE 2
156.25MHz, Integration Range:
12kHz – 20MHz
tjit
0.03
ps
tsk(o)
tsk(pp)
tR / tF
odc
Output Skew; NOTE 3, 4
Part-to-Part Skew; NOTE 4, 5
Output Rise/Fall Time
Output Duty Cycle
20
300
600
55
ps
ps
ps
%
20% to 80% @ 50MHz
300
45
IJ 200MHz
All parameters measured at IJ 266MHz unless noted otherwise.
NOTE 1: Measured from VCC/2 of the input to the differential output crossing point. The part does not add jitter.
NOTE 2: Driving only one input clock.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VCC/2 of the input to the differential output crossing point.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions.
Using the same type of inputs on each device, the outputs are measured at the differential cross points.
IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER
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Additive Phase Jitter
The spectral purity in a band at a specific offset from the
to the power in the fundamental. When the required offset is
fundamental compared to the power of the fundamental is called
the dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz band
specified, the phase noise is called a dBc value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
10k
100k
1M
10M
100M
Offset Frequency (Hz)
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The device
meets the noise floor of what is shown, but can actually be lower.
The phase noise is dependant on the input source and
measurement equipment.
IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER
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LOW SKEW, 1-TO-2 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER
Parameter Measurement Information
2V
Part 1
Qx
Qx
SCOPE
VCC
Qx
Part 1
Qy
Qy
LVPECL
nQx
tsk(pp)
VEE
1.3V 0.165V
-
3.3V LVPECL Output Load AC Test Circuit
Part-to-Part Skew
Qx
Qx
CLK0,
CLK1
Qy
Q0, Q1
Q0, Q1
Qy
tsk(o)
tpLH
Output Skew
Propagation Delay
Q0, Q1
Q, Q1
80%
tF
80%
tR
tPW
VSWING
20%
tPERIOD
Clock
Outputs
20%
tPW
odc =
x 100%
tPERIOD
Output Duty Cycle/Pulse Width/Period
Output Rise/Fall Time
IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER
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Application Information
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
CLK Inputs
LVPECL Outputs
For applications not requiring the use of a clock input, it can be left
floating. Though not required, but for additional protection, a 1kΩ
resistor can be tied from the CLK input to ground.
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
LVCMOS Control Pins
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
transmission lines. Matched impedance techniques should be
used to maximize operating frequency and minimize signal
distortion. Figures 2A and 2B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and
clock component process variations.
FOUT and FOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50Ω
3.3V
Z
o = 50Ω
125Ω
125Ω
FOUT
FIN
Z
o = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
Zo = 50Ω
VCC - 2V
1
RTT =
Zo
RTT
((VOH + VOL) / (VCC – 2)) – 2
84Ω
84Ω
Figure 2A. 3.3V LVPECL Output Termination
Figure 2B. 3.3V LVPECL Output Termination
IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER
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Schematic Example
Figure 3 shows a schematic example of the ICS8535-21. The
pin. For ICS8535-21, the unused clock outputs can be left floating.
decoupling capacitors should be physically located near the power
Zo = 50
Zo = 50
+
-
VCC = 3.3V
R2
50
R1
50
R3
50
U2
1
2
3
4
5
6
7
14
13
12
11
10
9
VEE
VCC
Q0
CLK_EN
CLK_SEL
CLK0
CLK_EN
CLK_SEL
CLK0
VEE
nQ0
nc
Q1
CLK1
CLK1
VCC
nQ1
VCC
8
8535-21
Vcco = 3.3V
R4
R6
133
133
(U1-7)
(U1-8)
(U1-14)
VCC
Zo = 50
Zo = 50
+
-
C1
C2
C3
C4
.1uF
.1uF
.1uF
10uf
R5
R7
82.5
82.5
Optional Termination
Figure 3. ICS8535-21 LVPECL Buffer Schematic Example
IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER
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Power Considerations
This section provides information on power dissipation and junction temperature for the ICS535-21.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8535-21 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 50mA = 173.25mW
Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power_MAX (3.3V, with all outputs switching) = 173.25mW + 60mW = 233.25mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device.
The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate
air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 85.5°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.233W * 85.5°C/W = 90°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type
of board (single layer or multi-layer).
Table 6. Thermal Resitance θJA for 48 Lead TQFP, Forced Convection
θJA vs. Air Flow
Linear Feet per Minute
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
146.4°C/W
93.2°C/W
125.2°C/W
85.5°C/W
112.1°C/W
81.2°C/W
IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER
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ICS8535AG-21 REV. A FEBRUARY 24, 2009
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LOW SKEW, 1-TO-2 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 4.
VCC
Q1
VOUT
RL
50Ω
VCC - 2V
Figure 4. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage
of VCC – 2V.
•
•
For logic high, VOUT = VOH_MAX = VCC_MAX – 0.9V
(VCC_MAX – VOH_MAX) = 0.9V
For logic low, VOUT = VOL_MAX = VCO_MAX – 1.7V
(VCC_MAX – VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX) = [(2V - (VCC_MAX – VOH_MAX))/RL] * (VCC_MAX – VOH_MAX) =
[(2V – 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOL_MAX) = [(2V – (VCC_MAX – VOL_MAX))/RL] * (VCC_MAX – VOL_MAX) =
[(2V – 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER
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Reliability Information
Table 7. θJA vs. Air Flow Table for a 14 Lead TSSOP
θJA vs. Air Flow
Linear Feet per Minute
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
146.4°C/W
93.2°C/W
125.2°C/W
85.5°C/W
112.1°C/W
81.2°C/W
Transistor Count
The transistor count for ICS8535-21 is: 412
Package Outline and Package Dimension
Package Outline - G Suffix for 14 Lead TSSOP
Table 8. Package Dimensions
All Dimensions in Millimeters
Symbol
Minimum
Maximum
N
A
14
1.20
0.15
1.05
0.30
0.20
5.10
A1
A2
b
0.5
0.80
0.19
0.09
4.90
c
D
E
6.40 Basic
E1
e
4.30
4.50
0.65 Basic
L
0.45
0°
0.75
8°
α
aaa
0.10
Reference Document: JEDEC Publication 95, MO-153
IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER
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LOW SKEW, 1-TO-2 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER
Ordering Information
Table 9. Ordering Information
Part/Order Number
8535AG-21
8535AG-21T
8535AG-21LF
8535AG-21LFT
Marking
8535AG21
8535AG21
8535A21L
8535A21L
Package
14 Lead TSSOP
14 Lead TSSOP
Shipping Packaging
Tube
2500 Tape & Reel
Tube
Temperature
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
“Lead-Free” 14 Lead TSSOP
“Lead-Free” 14Lead TSSOP
2500 Tape & Reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for
the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT
product for use in life support devices or critical medical instruments.
IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER
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LOW SKEW, 1-TO-2 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER
Revision History Sheet
Rev
Table
Page
Description of Change
Date
12/5/05
6/4/07
1
8
Features Section - added lead-free bullet.
A
Added Recommendations for Unused Input and Output Pins.
Ordering Information Table - added lead-free part number, marking and note.
T9
T9
14
A
13
Ordering Information Table - added lead-free marking.
IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER
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LOW SKEW, 1-TO-2 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER
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