ICS853P022AM
更新时间:2024-09-18 18:22:29
品牌:IDT
描述:TTL/CMOS to PECL Translator, 2 Func, Complementary Output, PDSO8, 3.90 X 4.90 MM, 1.37 MM HEIGHT, SOIC-8
ICS853P022AM 概述
TTL/CMOS to PECL Translator, 2 Func, Complementary Output, PDSO8, 3.90 X 4.90 MM, 1.37 MM HEIGHT, SOIC-8 电平转换器
ICS853P022AM 规格参数
是否无铅: | 含铅 | 是否Rohs认证: | 不符合 |
生命周期: | Obsolete | 零件包装代码: | SOIC |
包装说明: | SOP, | 针数: | 8 |
Reach Compliance Code: | not_compliant | ECCN代码: | EAR99 |
HTS代码: | 8542.39.00.01 | 风险等级: | 5.92 |
其他特性: | ECL MODE : VEE = -2.375V TO -5.25V WITH VCC=0V | 最大延迟: | |
接口集成电路类型: | TTL/CMOS TO PECL TRANSLATOR | JESD-30 代码: | R-PDSO-G8 |
JESD-609代码: | e0 | 长度: | 4.9 mm |
湿度敏感等级: | 1 | 位数: | 1 |
功能数量: | 2 | 端子数量: | 8 |
最高工作温度: | 85 °C | 最低工作温度: | -40 °C |
输出锁存器或寄存器: | NONE | 输出极性: | COMPLEMENTARY |
封装主体材料: | PLASTIC/EPOXY | 封装代码: | SOP |
封装形状: | RECTANGULAR | 封装形式: | SMALL OUTLINE |
峰值回流温度(摄氏度): | 240 | 认证状态: | Not Qualified |
座面最大高度: | 1.75 mm | 最大供电电压: | 5.25 V |
最小供电电压: | 2.375 V | 标称供电电压: | 3.3 V |
表面贴装: | YES | 温度等级: | INDUSTRIAL |
端子面层: | Tin/Lead (Sn85Pb15) | 端子形式: | GULL WING |
端子节距: | 1.27 mm | 端子位置: | DUAL |
处于峰值回流温度下的最长时间: | 30 | 宽度: | 3.9 mm |
Base Number Matches: | 1 |
ICS853P022AM 数据手册
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PDF下载ICS853P022
UAL LVCMOS / LVTTL-TO-DIFFERENTIAL
3.3V LVPECL TRANSLATOR
Integrated
Circuit
Systems, Inc.
D
GENERAL DESCRIPTION
FEATURES
The ICS853P022 is a Dual LVCMOS / LVTTL-to- • 2 differential 3.3V LVPECL outputs
ICS
Differential 3.3V LVPECL translator and a mem-
• LVCMOS/LVTTL clock inputs
HiPerClockS™
ber of the HiPerClocks™ family of High Perfor-
mance Clocks Solutions from ICS. The
ICS853P022 has single ended clock inputs.The
• Maximum output frequency: 1.1GHz
• Part-to-part skew: 650ps (maximum)
• Propagation Delay: 320ps (typical)
• Additive phase jitter, RMS: 0.03ps (typical)
single ended clock input accepts LVCMOS or LVTTL input
levels and translate them to LVPECL levels.The small outline
8-pin TSSOP package makes this device ideal for applica-
tions where space, high performance and low power are im-
portant.
• LVPECL mode operating voltage supply range:
VCC = 3.0V to 3.8V, VEE = 0V
• ECL mode operating voltage supply range:
VCC = 0V, VEE = -3.8V to -3.0V
• -40°C to 85°C ambient operating temperature
• Lead-Free package RoHS compliant
BLOCK DIAGRAM
PIN ASSIGNMENT
Q0
nQ0
D0
Q0
nQ0
Q1
VCC
D0
D1
VEE
1
2
3
4
8
7
6
5
Q1
nQ1
D1
nQ1
ICS853P022
8-LeadTSSOP, 118 mil
3mm x 3mm x 0.95mm package body
G Package
TopView
8-Lead SOIC, 150 mil
3.90mm x 4.90mm x 1.37mm package body
M Package
TopView
853P022AG
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REV. A FEBRUARY 23, 2005
1
ICS853P022
UAL LVCMOS / LVTTL-TO-DIFFERENTIAL
3.3V LVPECL TRANSLATOR
Integrated
Circuit
Systems, Inc.
D
TABLE 1. PIN DESCRIPTIONS
Number
Name
Q0, nQ0
Q1, nQ1
VEE
Type
Description
1, 2
3, 4
5
Output
Output
Power
Input
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Negative supply pin.
6
D1
LVCMOS / LVTTL clock input.
LVCMOS / LVTTL clock input.
Positive supply pin.
7
D0
Input
8
VCC
Power
853P022AG
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REV. A FEBRUARY 23, 2005
2
ICS853P022
UAL LVCMOS / LVTTL-TO-DIFFERENTIAL
3.3V LVPECL TRANSLATOR
Integrated
Circuit
Systems, Inc.
D
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, VCC
4.6V (LVPECL mode, VEE = 0) NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage
to the device. These ratings are stress specifi-
cations only. Functional operation of product at
these conditions or any conditions beyond those
listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may
affect product reliability.
Negative Supply Voltage, VEE
Inputs, VI (LVPECL mode)
Inputs, VI (ECL mode)
-4.6V (ECL mode, VCC = 0)
-0.5V to VCC + 0.5 V
0.5V to VEE - 0.5V
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
OperatingTemperature Range, TA -40°C to +85°C
StorageTemperature,TSTG -65°C to 150°C
PackageThermal Impedance, θJA 101.7°C/W (0 m/s)TSSOP
112.7°C/W (0 lfpm) SOIC
(Junction-to-Ambient)
TABLE 2A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.0V TO 3.8V; VEE = 0V
Symbol Parameter Test Conditions
Minimum Typical Maximum Units
VCC
IEE
Positive Supply Voltage
Power Supply Current
3.0
3.3
3.8
35
V
mA
TABLE 2B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = 3.0V TO 3.8V; VEE = 0V
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VIH
VIL
IIH
Input High Voltage
0.7 * VCC
V
Input Low Voltage
Input High Current
Input Low Current
0.3 * VCC
100
V
VCC = VIN = 3.8V
µA
mA
IIL
VCC = 3.8V, VIN = 0V
-0.6
TABLE 2C. LVPECL DC CHARACTERISTICS, VCC = 3.3V; VEE = 0V
-40°C
25°C
85°C
Symbol Parameter
Units
Min
2.175
1.405
Typ
Max
2.38
1.68
Min
2.225 2.295
1.425 1.52
Typ
Max
Min
2.295
1.44
Typ
2.33
Max
2.365
1.63
2.275
1.545
2.37
V
V
VOH
VOL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
1.615
1.535
Output parameters vary 1:1 with VCC. VCC can vary +3.8V to 3.0V.
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
853P022AG
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REV. A FEBRUARY 23, 2005
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ICS853P022
UAL LVCMOS / LVTTL-TO-DIFFERENTIAL
3.3V LVPECL TRANSLATOR
Integrated
Circuit
Systems, Inc.
D
TABLE 2D. ECL DC CHARACTERISTICS, VCC = 0V; VEE = -3.8V TO -3.0V
-40°C
25°C
Typ
85°C
Typ
Symbol Parameter
Units
Min
Typ
Max
Min
Max
Min
Max
-1.125 -1.025 -0.92 -1.075 -1.005 -0.93 -1.005 -0.97 -0.935
-1.895 -1.755 -1.62 -1.875 -1.78 -1.685 -1.86 -1.765 -1.67
VOH
VOL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
V
V
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
TABLE 3. AC CHARACTERISTICS, VCC = 0V; VEE = -3.8V TO -3.0V OR VCC = 3.0V TO 3.8V; VEE = 0V
-40°C
Min Typ
25°C
Max Min Typ
85°C
Max Min Typ
Symbol Parameter
Units
Max
fMAX
tpLH
Output Frequency
1.1
1.1
1.1
GHz
ps
Propagation Delay, Low to High;
NOTE 1
125 320
600
180 320
475
190 300
410
410
Propagation Delay, High to Low;
NOTE 1
tpHL
125 320
12
600
180 320
12
475
190 300
12
ps
tsk(o)
Output Skew; NOTE 2, 4
55
50
50
ps
ps
tsk(pp)
Part-to-Part Skew; NOTE 3, 4
330
225
225
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section
tjit
0.03
0.03
0.03
ps
ps
tR/tF
Output Rise/Fall Time
20% to 80%
85
200
315
100 200
285
85
200
315
All parameters are measured ≤ 650MHz unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
853P022AG
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REV. A FEBRUARY 23, 2005
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ICS853P022
UAL LVCMOS / LVTTL-TO-DIFFERENTIAL
3.3V LVPECL TRANSLATOR
Integrated
Circuit
Systems, Inc.
D
PARAMETER MEASUREMENT INFORMATION
2V
nQx
SCOPE
VCC
Qx
Qx
nQy
LVPECL
nQx
Qy
VEE
tsk(o)
-1.8V to -1.0V
OUTPUT LOAD AC TEST CIRCUIT
OUTPUT SKEW
nQx
PART 1
Qx
D0, D1
nQy
PART 2
Qy
nQ0, nQ1
Q0, Q1
tsk(pp)
tpLH
PROPAGATION DELAY
PART-TO-PART SKEW
80%
tF
80%
VSWING
20%
Clock
20%
Outputs
tR
OUTPUT RISE/FALL TIME
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REV. A FEBRUARY 23, 2005
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ICS853P022
UAL LVCMOS / LVTTL-TO-DIFFERENTIAL
3.3V LVPECL TRANSLATOR
Integrated
Circuit
Systems, Inc.
D
APPLICATION INFORMATION
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs.The two different layouts mentioned
are recommended only as guidelines.
50Ω transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion. Figures 1A and 1B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs.Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
3.3V
Z
o = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
((VOH + VOL) / (VCC – 2)) – 2
84Ω
84Ω
FIGURE 1A. LVPECL OUTPUT TERMINATION
FIGURE 1B. LVPECL OUTPUT TERMINATION
853P022AG
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REV. A FEBRUARY 23, 2005
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ICS853P022
UAL LVCMOS / LVTTL-TO-DIFFERENTIAL
3.3V LVPECL TRANSLATOR
Integrated
Circuit
Systems, Inc.
D
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS853P022.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS853P022 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.8V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.8V * 35mA = 133mW
Power (outputs)MAX = 30.94mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30.94mW = 61.88mW
Total Power_MAX (3.8V, with all outputs switching) = 133mW + 61.88mW = 194.88mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = JunctionTemperature
θJA = Junction-to-AmbientThermal Resistance
Pd_total =Total Device Power Dissipation (example calculation is in section 1 above)
TA = AmbientTemperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 1 meters per second and a multi-layer board, the appropriate value is 90.5°C/W perTable 4A below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.195W * 90.5°C/W = 102.6°C. This is below the limit of 125°C.
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 4A. THERMAL RESISTANCE θJA FOR 8-PIN TSSOP, FORCED CONVECTION
θJA byVelocity (Meters per Second)
0
1
2
Multi-Layer PCB, JEDEC StandardTest Boards
101.7°C/W
90.5°C/W
89.8°C/W
TABLE 4B. THERMAL RESISTANCE θJA FOR 8 LEAD SOIC
θJA byVelocity (Linear Feet per Minute)
0
200
128.5°C/W
103.3°C/W
500
115.5°C/W
97.1°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
153.3°C/W
112.7°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
853P022AG
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ICS853P022
UAL LVCMOS / LVTTL-TO-DIFFERENTIAL
3.3V LVPECL TRANSLATOR
Integrated
Circuit
Systems, Inc.
D
3. Calculations and Equations.
LVPECL output driver circuit and termination are shown in Figure 4.
VCC
Q1
VOUT
RL
50
VCC - 2V
Figure 4. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage ofV - 2V.
CCO
•
•
For logic high, VOUT = V
= V
– 0.935V
OH_MAX
CCO_MAX
)
= 0.935V
OH_MAX
(V
- V
CC_MAX
For logic low, VOUT = V
= V
– 1.67V
CCO_MAX
OL_MAX
)
= 1.67V
OL_MAX
(V
- V
CCO_MAX
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OH_MAX
CCO_MAX
CCO_MAX
OH_MAX
_MAX
CCO
OH_MAX
CCO _MAX
OH_MAX
L
L
[(2V - 0.935V)/50Ω] * 0.935V = 19.92mW
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
- V
/R ] * (V
- V
) =
OL_MAX
CCO_MAX
CCO_MAX
OL_MAX
_MAX
OL_MAX
CCO_MAX
OL_MAX
L
CCO
L
[(2V - 1.67V)/50Ω] * 1.67V = 11.02mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW
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REV. A FEBRUARY 23, 2005
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ICS853P022
UAL LVCMOS / LVTTL-TO-DIFFERENTIAL
3.3V LVPECL TRANSLATOR
Integrated
Circuit
Systems, Inc.
D
RELIABILITY INFORMATION
TABLE 5A. θJAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP
θJA byVelocity (Meters per Second)
0
1
2
Multi-Layer PCB, JEDEC Standard Test Boards
101.7°C/W
90.5°C/W
89.8°C/W
TABLE 5B. θJAVS. AIR FLOW TABLE FOR 8 LEAD SOIC
θJA byVelocity (Linear Feet per Minute)
0
200
128.5°C/W
103.3°C/W
500
115.5°C/W
97.1°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
153.3°C/W
112.7°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS853P022 is: 92
Pin compatible with MC100EPT22
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REV. A FEBRUARY 23, 2005
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ICS853P022
UAL LVCMOS / LVTTL-TO-DIFFERENTIAL
3.3V LVPECL TRANSLATOR
Integrated
Circuit
Systems, Inc.
D
PACKAGE OUTLINE - M SUFFIX FOR 8 LEAD SOIC
PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP
TABLE 6A. PACKAGE DIMENSIONS
TABLE 6B. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Millimeters
SYMBOL
Minimum
Maximum
MINIMUN
MAXIMUM
N
A
8
N
A
A1
B
C
D
E
e
8
--
1.10
0.15
0.97
0.38
0.23
1.35
0.10
0.33
0.19
4.80
3.80
1.75
0.25
0.51
0.25
5.00
4.00
A1
A2
b
0
0.79
0.22
0.08
c
D
3.00 BASIC
4.90 BASIC
3.00 BASIC
0.65 BASIC
1.95 BASIC
E
1.27 BASIC
E1
e
H
h
5.80
0.25
0.40
0°
6.20
0.50
1.27
8°
e1
L
L
0.40
0°
0.80
8°
α
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-187
853P022AG
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REV. A FEBRUARY 23, 2005
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ICS853P022
UAL LVCMOS / LVTTL-TO-DIFFERENTIAL
3.3V LVPECL TRANSLATOR
Integrated
Circuit
Systems, Inc.
D
TABLE 7. ORDERING INFORMATION
Part/Order Number
ICS853P022AG
Marking
Package
8 lead TSSOP
Count
96 per tube
2500
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
P22A
P22A
ICS853P022AGT
ICS853P022AGLF
ICS853P022AGLFT
ICS853P022AM
8 lead TSSOP on Tape and Reel
8 lead "Lead-Free" TSSOP
8 lead "Lead-Free" TSSO on Tape and Reel
8 lead SOIC
P2AL
96 per tube
2500
P2AL
53P022A
53P022A
53P022AL
53P022AL
96 per tube
2500
ICS853P022AMT
ICS853P022AMLF
ICS853P022AMLFT
8 lead SOIC on Tape and Reel
8 lead "Lead-Free" SOIC
96 per tube
2500
8 lead "Lead-Free" SOIC on Tape and Reel
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
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11
ICS853P022AM 相关器件
型号 | 制造商 | 描述 | 价格 | 文档 |
ICS853P022AMT | IDT | TTL/CMOS to PECL Translator, 2 Func, Complementary Output, PDSO8, 3.90 X 4.90 MM, 1.37 MM HEIGHT, SOIC-8 | 获取价格 | |
ICS853S012AKI | IDT | Low Skew Clock Driver, 853S Series, 1 True Output(s), 0 Inverted Output(s), 5 MM X 5 MM, 0.75 MM HEIGHT, MO-220VHHD-2, VFQFN-32 | 获取价格 | |
ICS853S012AKILF | IDT | Low Skew Clock Driver, 853S Series, 1 True Output(s), 0 Inverted Output(s), 5 MM X 5 MM, 0.75 MM HEIGHT, ROHS COMPLIANT, MO-220VHHD-2, VFQFN-32 | 获取价格 | |
ICS853S012AKILFT | IDT | Low Skew Clock Driver, 853S Series, 1 True Output(s), 0 Inverted Output(s), 5 MM X 5 MM, 0.75 MM HEIGHT, ROHS COMPLIANT, MO-220VHHD-2, VFQFN-32 | 获取价格 | |
ICS853S012AKIT | IDT | Low Skew Clock Driver, 853S Series, 1 True Output(s), 0 Inverted Output(s), 5 MM X 5 MM, 0.75 MM HEIGHT, MO-220VHHD-2, VFQFN-32 | 获取价格 | |
ICS853S012I | IDT | 12:1, Different ial-to-3.3V, 2.5V LVPECL Clock/Data Mult iplexer | 获取价格 | |
ICS853S012I_17 | IDT | 12:1, Different ial-to-3.3V, 2.5V LVPECL Clock/Data Mult iplexer | 获取价格 | |
ICS853S024 | IDT | LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL FANOUT BUFFER | 获取价格 | |
ICS853S202AYI | IDT | Low Skew Clock Driver, 853S Series, 2 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, MS-026BBC, LQFP-48 | 获取价格 | |
ICS853S202AYILF | IDT | Low Skew Clock Driver, 853S Series, 2 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-026BBC, LQFP-48 | 获取价格 |
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