ICS873991-147 [IDT]
LOW VOLTAGE, LVCMOS/LVPECL-TO LVPECL/ECL CLOCK GENERATOR; 低电压， LVCMOS / LVPECL -TO LVPECL / ECL时钟发生器
| 型号： | ICS873991-147 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | LOW VOLTAGE, LVCMOS/LVPECL-TO LVPECL/ECL CLOCK GENERATOR |
| 文件： | 总17页 (文件大小：307K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
LOW VOLTAGE, LVCMOS/LVPECL-TO LVPECL/ECL
CLOCK GENERATOR
ICS873991-147
GENERAL DESCRIPTION
FEATURES
• Fourteen differential 3.3V LVPECL/ECL outputs
• Selectable differential LVPECL or REF_CLK inputs
The ICS873991-147 is a low voltage, low skew, 3.3V
ICS
LVPECL or ECL Clock Generator and a member of
the HiPerClockS™ family of High Performance
Clock Solutions from IDT. The ICS873991-147 has
two selectable clock inputs. The PCLK, nPCLK pair
HiPerClockS™
• PCLK, nPCLK can accept the following input levels:
LVPECL, CML, SSTL
can accept an LVPECL input and the REF_CLK pin can accept
a LVCMOS or LVTTL input. This device has a fully integrated
PLL along with frequency configurable outputs. An external
feedback input and output regenerates clocks with “zero de-
lay”.
• REF_CLK accepts the following input levels:
LVCMOS, LVTTL
• Input clock frequency range: 6.25MHz to 125MHz
• Maximum output frequency: 500MHz
• VCO range: 200MHz to 1GHz
The four independent banks of outputs each have their own
output dividers, which allow the device to generate a multitude
of different bank frequency ratios and output-to-input frequency
ratios. The output frequency range is 25MHz to 500MHz and
the input frequency range is 6.25MHz to 125MHz.The PLL_SEL
input can be used to bypass the PLL for test and system debug
purposes. In bypass mode, the input clock is routed around the
PLL and into the internal output dividers.
• Output skew: 70ps (typical)
• Cycle-to-cyle jitter: 35ps (typical)
• LVPECL mode operating voltage supply range:
VCC = 3.135V to 3.465V, VEE = 0V
• ECL mode operating voltage supply range:
VCC = 0V, VEE = -3.465V to -3.135V
The ICS873991-147 also has a SYNC output which can be
used for system synchronization purposes. It monitors Bank A
and Bank C outputs for coincident rising edges and signals a
pulse per the timing diagrams in this data sheet. This feature is
used primarily in applications where Bank A and Bank C are
running at different frequencies, and is particularly useful when
they are running at non-integer multiples of each other.
• 0°C to 70°C ambient operating temperature
• Available in lead-free (RoHS 6) package
• Industrial temperature available upon request
PIN ASSIGNMENT
Example Applications:
1. Line Card Multiplier: Multiply 19.44MHz from a back-plane
to 77.76MHz on the line card ASIC and Serdes.
39 38 37 36 35 34 33 32 31 30 29 28 27
nQB3 40
2. Zero Delay Buffer: Fan out up to thirteen 100MHz copies
from a reference clock to multiple processing units on an
embedded system.
26
25
24
23
22
21
20
19
18
17
16
15
14
QC1
QB3 41
nQC1
QC0
VCCO
42
nQA0 43
QA0 44
nQC0
VCCO
QD1
ICS873991-147
52-Lead LQFP
10mm x 10mm x 1.4mm
package body
nQA1 45
QA1 46
nQD1
QD0
nQA2 47
QA2 48
Y package
Top View
nQD0
VCCO
QFB
nQA3 49
QA3 50
SYNC_SEL 51
VCO_SEL 52
nQFB
VCCA
1
2
3
4
5
6
7 8 9 10 11 12 13
The Preliminary Information presented herein represents a product in pre-production.The noted characteristics are based on initial product characterization
and/or qualification.Integrated DeviceTechnology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT™ / ICS™ LVPECL/ECL CLOCK GENERATOR
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LOW VOLTAGE, LVCMOS/LVPECL-TO-LVPECL/ECL CLOCK GENERATOR
PRELIMINARY
BLOCK DIAGRAM
Pulldown
VCO_SEL
Pulldown
PLL_EN
QA0
Pulldown
REF_SEL
nQA0
Pulldown
REF_CLK
QA1
nPCLK
nQA1
PCLK
QA2
PHASE
DETECTOR
VCO
nQA2
QA3
EXT_FB
LPF
nQA3
nEXT_FB
QB0
nQB0
Pulldown
MR
QB1
nQB1
FREQUENCY
GENERATOR
QB2
nQB2
Pulldown
FSEL_0:3
QB3
SYNC
nQB3
QC0
Pulldown
FSEL_FB0:2
nQC0
QC1
nQC1
QC2
nQC2
QD0
nQD0
Pulldown
SYNC_SEL
QD1
nQD1
QFB
nQFB
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LOW VOLTAGE, LVCMOS/LVPECL-TO-LVPECL/ECL CLOCK GENERATOR
PRELIMINARY
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
VEE
Power
Negative supply pin.
Active High Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs (Qx) to go low and the inverted outputs
(nQx) to go high. When logic LOW, the internal dividers and the outputs
are enabled. LVCMOS/LVTTL interface levels.
PLL enable pin. When logic LOW, PLL is enabled. When logic HIGH,
PLL is in bypass mode. LVCMOS/LVTTL interface levels.
2
MR
Input Pulldown
Input Pulldown
3
4
PLL_EN
Selects between the different reference inputs as the PLL reference
REF_SEL
Input Pulldown source. When logic LOW, selects PCLK/nPCLK. When logic HIGH,
selects REF_CLK. LVCMOS/LVTTL interface levels.
5
6
7
FSEL_FB2
FSEL_FB1
FSEL_FB0
Input Pulldown Feedback frequency select pins. LVCMOS/LVTTL interface levels.
8
9
REF_CLK
PCLK
Input Pulldown Reference clock input. LVCMOS/LVTTL interface levels.
Input Pulldown Non-inverting differential LVPECL clock input.
Pullup/
10
nPCLK
Input
Inverting differential LVPECL clock input. VCC/2 default when left floating.
Core supply pin.
Pulldown
11
12
VCC
Power
EXT_FB
Input Pulldown Non-inverting external feedback input.
Pullup/
13
14
nEXT_FB
VCCA
Input
Power
Output
Power
Inverting external feedback input. VCC/2 default when left floating.
Pulldown
Analog supply pin.
15
16
nQFB
QFB
Differential feedback output pair. LVPECL Interface levels.
17, 22, 30, 42
18, 19
VCCO
Output supply pins.
nQD0, QD0 Output
nQD1, QD1 Output
nQC0, QC0 Output
nQC1, QC1 Output
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
20, 21
23, 24
25, 26
27
33
36
39
FSEL3
FSEL2
FSEL1
FSEL0
Input Pulldown Frequency select pins. LVCMOS/LVTTL interface levels.
28, 29
31, 32
34, 35
37, 38
40, 41
43, 44
45, 46
47, 48
49, 50
nQC2, QC2 Output
nQB0, QB0 Output
nQB1, QB1 Output
nQB2, QB2 Output
nQB3, QB3 Output
nQA0, QA0 Output
nQA1, QA1 Output
nQA2, QA2 Output
nQA3, QA3 Output
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
SYNC output select pin. When LOW, the SYNC otuput follows the
51
52
SYNC_SEL Input Pulldown timing diagram (page 5). When HIGH, QD output follows QC output
LVCMOS/LVTTL interface levels..
VCO_SEL
Input Pulldown Selects VCO range. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
IDT™ / ICS™ LVPECL/ECL CLOCK GENERATOR
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LOW VOLTAGE, LVCMOS/LVPECL-TO-LVPECL/ECL CLOCK GENERATOR
PRELIMINARY
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
CIN
Input Capacitance
4
pF
kΩ
kΩ
RPULLDOWN Input Pulldown Resistor
51
51
RPULLup
Input Pullup Resistor
TABLE 3A. SELECT PIN FUNCTION TABLE
Inputs
TABLE 3B. FEEDBACK CONTROL FUNCTION TABLE
Inputs
Outputs
Outputs
FSEL_FB2 FSEL_FB1 FSEL_FB0
QFB
÷2
FSEL3 FSEL2 FSEL1 FSEL0 QAx QBx QCx
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
÷ 2
÷ 2
÷ 2
÷ 2
÷ 2
÷ 2
÷ 2
÷ 2
÷ 2
÷ 2
÷ 4
÷ 4
÷ 4
÷ 6
÷ 6
÷ 8
÷ 2
÷ 2
÷ 4
÷ 2
÷ 6
÷ 4
÷ 4
÷ 6
÷ 2
÷ 8
÷ 4
÷ 6
÷ 6
÷ 6
÷ 8
÷ 8
÷ 2
÷ 4
÷ 4
÷ 6
÷ 6
÷ 6
÷ 8
÷ 8
÷ 8
÷ 8
÷ 6
÷ 6
÷ 8
÷ 8
÷ 8
÷ 8
÷4
÷6
÷8
÷8
÷16
÷24
÷32
TABLE 3C. INPUT CONTROL FUNCTION TABLE
Control Input Pin
PLL_EN
Logic 0
Enables PLL
fVCO
Logic 1
Bypasses PLL
fVCO/2
VCO_SEL
REF_SEL
MR
Selects PCLK/nPCLK
---
Selects REF_CLK
Resets outputs
Match QC Outputs
SYNC_SEL
Selects outputs
IDT™ / ICS™ LVPECL/ECL CLOCK GENERATOR
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LOW VOLTAGE, LVCMOS/LVPECL-TO-LVPECL/ECL CLOCK GENERATOR
PRELIMINARY
1:1 Mode
QA
QC
SYNC (QD)
2:1 Mode
QA
QC
SYNC (QD)
3:1 Mode
QA
QC
SYNC (QD)
3:2 Mode
QA
QC
SYNC (QD)
4:3 Mode
QA
QC
SYNC (QD)
FIGURE 1. TIMING DIAGRAMS
IDT™ / ICS™ LVPECL/ECL CLOCK GENERATOR
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LOW VOLTAGE, LVCMOS/LVPECL-TO-LVPECL/ECL CLOCK GENERATOR
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
NOTE: Stresses beyond those listed under Absolute Maximum
Ratings may cause permanent damage to the device. These rat-
ings are stress specifications only. Functional operation of prod-
uct at these conditions or any conditions beyond those listed in
the DC Characteristics or AC Characteristics is not implied. Ex-
posure to absolute maxi-mum rating conditions for extended pe-
riods may affect product reliability.
Supply Voltage% V
4.6V
CC
Inputs% V
-0.ꢀV to VCC + 0.ꢀ V
I
Outputs% IO
Continuous Current
Surge Current
ꢀ0mA
100mA
Package Thermal Impedance% θ
63.7°C/W (0 mps)
-6ꢀ°C to 1ꢀ0°C
JA
Storage Temperature% T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V ꢀ5% VEE = 0V% TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
3.13ꢀ
Typical
3.3
Maximum Units
VCC
VCCA
VCCO
ICC
Core Supply Voltage
3.46ꢀ
3.46ꢀ
3.46ꢀ
1ꢀ0
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
3.13ꢀ
3.3
3.13ꢀ
3.3
V
mA
mA
mA
ICCA
ICCO
1ꢀ
9ꢀ
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V ꢀ5% VEE = 0V% TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
PLL_EN% VCO_SEL%
REF_SEL% SYNC_SEL%
FSEL_FB0:FSEL_FB2%
FSEL0:FSEL3% MR
2
2
V
CC + 0.3
V
V
V
VIH
Input High Voltage
REF_CLK
VCC + 0.3
0.8
PLL_EN% VCO_SEL%
REF_SEL% SYNC_SEL%
FSEL_FB0:FSEL_FB2%
FSEL0:FSEL3% MR
-0.3
-0.3
-ꢀ
VIL
Input Low Voltage
REF_CLK
1.3
V
IIH
IIL
Input High Current
Input Low Current
VCC = VIN = 3.46ꢀV
1ꢀ0
µA
µA
VIN = 0V% VCC = 3.46ꢀV
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V ꢀ5% VEE = 0V% TA = 0°C TO 70°C
Symbol Parameter
IIH Input High Current
Test Conditions
Minimum Typical Maximum Units
PCLK
VCC = VIN = 3.46ꢀV
1ꢀ0
ꢀ
µA
µA
µA
µA
V
nPCLK
PCLK
V
CC = VIN = 3.46ꢀV
VCC = 3.46ꢀV% VIN = 0V
CC = 3.46ꢀV% VIN = 0V
-ꢀ
-1ꢀ0
IIL
Input Low Current
nPCLK
V
VPP
Peak-to-Peak Input Voltage
0.3
1
VCC
VCMR
VOH
Common Mode Input Voltage; NOTE 1
Output High Voltage; NOTE 2
Output Low Voltage; NOTE 2
VEE + 1.ꢀ
VCC - 1.4
VCC - 2.0
0.6
V
VCC - 0.9
VCC - 1.7
1
V
VOL
V
VSWING
Peak-to-Peak Output Voltage Swing
V
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: Outputs terminated with ꢀ0Ω to VCCO - 2V. .
IDT™ / ICS™ LVPECL/ECL CLOCK GENERATOR
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LOW VOLTAGE, LVCMOS/LVPECL-TO-LVPECL/ECL CLOCK GENERATOR
PRELIMINARY
TABLE 5. PLL INPUT REFERENCE CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
tR / tR Input Rise/Fall Time
Test Conditions
Minimum Typical Maximum Units
REF_CLK
3
ns
Feedback ÷ 6
Feedback ÷ 8
Feedback ÷ 16
Feedback ÷ 24
Feedback ÷ 32
Feedback ÷ 4
Feedback ÷ 6
Feedback ÷ 8
Feedback ÷ 16
Feedback ÷ 24
Feedback ÷ 32
66.66
50
166.67
125
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ꢀ
Reference Frequency
VCO_SEL = 0
25
62.5
41.67
31.25
100
16.66
12.5
50
fREF
33.33
25
66.66
50
Reference Frequency
VCO_SEL = 1
12.5
8.33
6.25
25
25
16.66
12.5
75
fREFDC
Reference Input Duty Cycle
NOTE: These parameters are guaranteed by design, but are not tested in production.
TABLE 6. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
QA, QB, QC
QD
500
400
200
MHz
MHz
MHz
fMAX
Output Frequency
SYNC_SEL = 1
SYNC_SEL = 0
QD; NOTE 1
Static Phase Offset;
NOTE 2, 3
t(Ø)
PCLK, nPCLK
170
ps
tsk(o)
tsk(w)
tjit(cc)
Output Skew; NOTE 4, 5
70
TBD
35
ps
ps
Multiple Frequency Skew; NOTE 5, 6
Cycle-to-Cycle Jitter; NOTE 5
ps
PLL_SEL = 0
PLL_SEL = 1
0.4
1.0
480
10
GHz
MHz
ms
ns
fVCO
PLL VCO Lock Range; NOTE 7
200
tLOCK
tR / tF
odc
PLL Lock Time
Output Rise/Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ
0.5
50
ꢀ
All parameters measured at fMAX unless noted otherwise.
NOTE 1: SYNC output (QD when SYNC_SEL = 0) operation guaranteed to 800MHz maximum VCO frequency.
NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal
when the PLL is locked and the input reference frequency is stable.
NOTE 3: Static phase offset is specified for an input frequency of 50MHz with feedback in ÷8.
NOTE 4: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: Defined as skew across banks of outputs switching in the same direction operating at different frequencies
with the same supply voltages and equal load conditions. Measured at VCCO/2.
NOTE 7: When VCO_SEL = 0, the PLL will be unstable with feedback configurations of ÷2, ÷4 and some ÷6.
When VCO_SEL = 1, the PLL will be unstable with a feedback configuration of ÷2.
IDT™ / ICS™ LVPECL/ECL CLOCK GENERATOR
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LOW VOLTAGE, LVCMOS/LVPECL-TO-LVPECL/ECL CLOCK GENERATOR
PRELIMINARY
PARAMETER MEASUREMENT INFORMATION
2V
VCC
SCOPE
Qx
VCC
,
VCCA, VCCO
nPCLK
PCLK
LVPECL
VPP
VCMR
Cross Points
nQx
VEE
-1.3V -0.165V
VEE
OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVELS
nQx
Qx
nQFB,
nQAx:nQDx
QFB,
QAx:QDx
nQy
➤
➤
tcycle n
tcycle n+1
➤
➤
Qy
tjit(cc) = tcycle n – tcycle n+1
1000 Cycles
tsk(o)
CYCLE-TO-CYCLE JITTER
OUTPUT SKEW
nPCLK
PCLK
VOH
VOL
nQxx
Qxx
nQFB,
nQAx:nQDx
VOH
VOL
nQyy
Qyy
QFB,
QAx:QDx
➤
t(Ø)
➤
tsk(ω)
MULTIPLE FREQUENCY SKEW
STATIC PHASE OFFSET
nQFB,
nQAx:nQDx
80ꢀ
80ꢀ
QFB,
QAx:QDx
VSWING
20ꢀ
tPW
tPERIOD
Clock
20ꢀ
Outputs
tF
tR
tPW
odc =
x 100ꢀ
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
OUTPUT RISE/FALL TIME
IDT™ / ICS™ LVPECL/ECL CLOCK GENERATOR
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LOW VOLTAGE, LVCMOS/LVPECL-TO-LVPECL/ECL CLOCK GENERATOR
PRELIMINARY
APPLICATIONS INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS873991-147 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VCC, VCCA and VCCO
should be individually connected to the power supply plane
through vias, and bypass capacitors should be used for each
pin. To achieve optimum jitter performance, power supply iso-
lation is required. Figure 2 illustrates how a 10Ω resistor along
with a 10μF and a 0.01μF bypass capacitor should be con-
nected to each VCCA pin.
3.3V
VCC
.01μF
10Ω
VCCA
.01μF
10μF
FIGURE 2. POWER SUPPLY FILTERING
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 3 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V /2 is
generated by the bias resistors R1, R2 and C1. This bias CcCircuit
should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V = 3.3V, V_REF should be 1.25V
CC
and R2/R1 = 0.609.
VCC
R1
1K
Single Ended Clock Input
V_REF
PCLK
nPCLK
C1
0.1u
R2
1K
FIGURE 3. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
IDT™ / ICS™ LVPECL/ECL CLOCK GENERATOR
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LOW VOLTAGE, LVCMOS/LVPECL-TO-LVPECL/ECL CLOCK GENERATOR
PRELIMINARY
LVPECL CLOCK INPUT INTERFACE
The PCLK/nPCLK accepts LVPECL, CML, SSTL and other
differential signals. Both VSWING and VOH must meet the VPP and
VCMR input requirements. Figures 4A to 4E show interface
examples for the HiPerClockS PCLK/nPCLK input driven by
the most common driver types. The input interfaces suggested
here are examples only. If the driver is from another vendor,
use their termination recommendation. Please consult with the
vendor of the driver component to confirm the driver termination
requirements.
3.3V
3.3V
3.3V
3.3V
3.3V
R1
50
R2
50
Zo = 50 Ohm
CML
Zo = 50 Ohm
Zo = 50 Ohm
PCLK
PCLK
R1
100
nPCLK
nPCLK
Zo = 50 Ohm
HiPerClockS
HiPerClockS
PCLK/nPCLK
PCLK/nPCLK
CML Built-In Pullup
FIGURE 4A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY AN OPEN COLLECTOR CML DRIVER
FIGURE 4B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A BUILT-IN PULLUP CML DRIVER
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
R3
125
R4
125
R3
84
R4
84
C1
C2
Zo = 50 Ohm
Zo = 50 Ohm
3.3V LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
PCLK
PCLK
nPCLK
HiPerClockS
PCLK/nPCLK
nPCLK
HiPerClockS
Input
LVPECL
R5
100 - 200
R6
100 - 200
R1
125
R2
125
R1
84
R2
84
FIGURE 4C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER
FIGURE 4D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER WITH AC COUPLE
3.3V
3.3V
3.3V
Zo = 50 Ohm
R3
1K
R4
1K
C1
C2
LVDS
PCLK
R5
100
nPCLK
Zo = 50 Ohm
HiPerClockS
PCLK/nPCLK
R1
1K
R2
1K
FIGURE 4E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVDS DRIVER
IDT™ / ICS™ LVPECL/ECL CLOCK GENERATOR
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PRELIMINARY
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
PCLK/nPCLK INPUTS
OUTPUTS:
LVPECL OUTPUTS
For applications not requiring the use of a differential input, both
the PCLK and nPCLK pins can be left floating. Though not
required, but for additional protection, a 1kΩ resistor can be tied
from PCLK to ground.
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
LVCMOS CONTROL PINS
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
drive 50Ω transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion. Figures 5A and 5B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, termi-
nating resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
3.3V
Zo = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
((VOH + VOL) / (VCC – 2)) – 2
84Ω
84Ω
FIGURE 5A. LVPECL OUTPUT TERMINATION
FIGURE 5B. LVPECL OUTPUT TERMINATION
IDT™ / ICS™ LVPECL/ECL CLOCK GENERATOR
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PRELIMINARY
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS873991-147.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS873991-147 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V = 3.3V + 5% = 3.465V, which gives worst case results.
CC
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core) = V
* I
= 3.465V * 150mA = 519.75mW
EE_MAX
MAX
CC_MAX
Power (outputs) = 30mW/Loaded Output pair
MAX
If all outputs are loaded, the total power is 14 * 30mW = 420mW
Total Power
(3.465V, with all outputs switching) = 519.75mW + 420mW = 939.75mW
_MAX
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
TM
device. The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 55.5°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.940W * 55.5°C/W = 122.2°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 7. THERMAL RESISTANCE θ FOR 52-PIN LQFP FORCED CONVECTION
JA
θ by Velocity (Meters per Second)
JA
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
63.7°C/W
55.5°C/W
52.4°C/W
IDT™ / ICS™ LVPECL/ECL CLOCK GENERATOR
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PRELIMINARY
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 6.
VCCO
Q1
VOUT
R L
50
VCCO - 2V
FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CCO
•
•
For logic high, V = V
= V
– 0.9V
OUT
OH_MAX
CCO_MAX
)
= 0.9V
OH_MAX
(V
- V
CCO_MAX
For logic low, V = V
= V
– 1.7V
OUT
OL_MAX
CCO_MAX
)
= 1.7V
OL_MAX
(V
- V
CCO_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
- V
/R ] * (V
- V
) =
OH_MAX
CCO_MAX
CCO_MAX
OH_MAX
CCO_MAX
OH_MAX
CCO_MAX
OH_MAX
L
L
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
/R ] * (V
- V
) =
OL_MAX
CCO_MAX
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
L
L
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
IDT™ / ICS™ LVPECL/ECL CLOCK GENERATOR
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PRELIMINARY
RELIABILITY INFORMATION
TABLE 8. θ VS. AIR FLOW TABLE FOR 52 LEAD LQFP
JA
θ by Velocity (Meters per Second)
JA
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
63.7°C/W
55.5°C/W
52.4°C/W
TRANSISTOR COUNT
The transistor count for ICS873991-147 is: 5969
IDT™ / ICS™ LVPECL/ECL CLOCK GENERATOR
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PRELIMINARY
PACKAGE OUTLINE - Y SUFFIX FOR 52 LEAD LQFP
TABLE 9. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BCC
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
52
--
--
1.60
0.15
1.45
0.38
0.20
A1
A2
b
0.05
1.35
0.22
0.09
--
1.40
0.32
c
--
D
12.00 BASIC
10.00 BASIC
7.80 Ref.
12.00 BASIC
10.00 BASIC
7.80 Ref.
0.65 BASIC
--
D1
D2
E
E1
E2
e
L
0.45
0.75
θ
--
0°
7°
ccc
--
--
0.10
Reference Document: JEDEC Publication 95, MS-026
IDT™ / ICS™ LVPECL/ECL CLOCK GENERATOR
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PRELIMINARY
TABLE 10. ORDERING INFORMATION
Part/Order Number
873991AY-147LF
873991AY-147LFT
Marking
Package
Shipping Packaging Temperature
ICS873991A147L
ICS873991A147L
52 Lead "Lead-Free" LQFP
52 Lead "Lead-Free" LQFP
tray
0°C to 70°C
0°C to 70°C
500 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional
processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical
instruments.
IDT™ / ICS™ LVPECL/ECL CLOCK GENERATOR
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ICS873991-147
LOW VOLTAGE, LVCMOS/LVPECL-TO-LVPECL/ECL CLOCK GENERATOR
PRELIMINARY
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
800-345-7015
408-284-8200
Fax: 408-284-2775
For Tech Support
netcom@idt.com
480-763-2056
Corporate Headquarters
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
Asia Pacific and Japan
Integrated Device Technology
Singapore (1997) Pte. Ltd.
Reg. No. 199707558G
435 Orchard Road
Europe
IDT Europe, Limited
321 Kingston Road
Leatherhead, Surrey
KT22 7TU
United States
800 345 7015
#20-03 Wisma Atria
England
+408 284 8200 (outside U.S.)
Singapore 238877
+44 (0) 1372 363 339
Fax: +44 (0) 1372 378851
+65 6 887 5505
© 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks
of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be
trademarks or registered trademarks used to identify products or services of their respective owners.
Printed in USA
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