ICS874001AGI-02T [IDT]
PLL Based Clock Driver, 874001 Series, 1 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 0.92 MM HEIGHT, MO-153, TSSOP-20;
| 型号： | ICS874001AGI-02T |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PLL Based Clock Driver, 874001 Series, 1 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 0.92 MM HEIGHT, MO-153, TSSOP-20 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总13页 (文件大小：1099K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
PCI EXPRESS/JITTER ATTENUATOR
ICS874001I-02
GENERAL DESCRIPTION
FEATURES
The ICS874001I-02 is a high performance Jitter
• One differential LVDS output pair
ICS
HiPerClockS™
Attenuator designed for use in PCI Express™ sys-
tems. In some PCI Express systems, such as those
found in desktop PCs, the PCI Express clocks are
generated from a low bandwidth, high phase noise
PLL frequency synthesizer. In these systems, a jitter
• One differential clock input
• CLK and nCLK supports the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
• Output frequency range: 98MHz - 640MHz
• Input frequency range: 98MHz - 128MHz
• VCO range: 490MHz - 640MHz
attenuator may be required to attenuate high frequency random
and deterministic jitter components from the PLL synthesizer
and from the system board. The ICS874001I-02 has 2 PLL
bandwidth modes: 2.2MHz and 3MHz. The 2.2MHz mode will
provide maximum jitter attenuation, but with higher PLL tracking
skew and spread spectrum modulation from the motherboard
synthesizer may be attenuated. The 3MHz bandwidth provides
the best track-ing skew and will pass most spread profiles, but
the jitter attenuation will not be as good as the lower bandwidth
modes. The 874001I-02 can be set for different modes using the
F_SELx pins, as shown in Table 3C.
• Cycle-to-cycle jitter: 50ps (maximum) design target
• 3.3V or 2.5V operating supply
• Two bandwidth modes allow the system designer to make
jitter attenuation/tracking skew design trade-offs
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
The ICS874001I-02 uses IDT’s 3rd Generation FemtoClockTM
PLL technology to achive the lowest possible phase noise.
The device is packaged in a small 20-pin TSSOP package,
making it ideal for use in space constrained applications such as
PCI Express add-in cards.
packages
nc
PLL_SEL
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
PIN ASSIGNMENT
nc
nc
nc
VDDO
Q
nQ
MR
BW_SEL
F_SEL1
VDDA
F_SEL0
nc
nc
GND
nCLK
CLK
OE
PLL _SEL CONTROL TABLE
PLL BANDWIDTH CONTROL TABLE
BW_SEL
0 = Bypass
0 = PLL Bandwidth: 2.2MHz (default)
1 = PLL Bandwidth: 3MHz
1 = VCO (default)
VDD
ICS874001I-02
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm package body
G Package
BLOCK DIAGRAM
Pullup
PLL_SEL
Pulldown
BW_SEL
0 = 2.2MHz
1 = 3MHz
Top View
0
1
Output Divider
0 0 ÷5
0 1 ÷4
1 0 ÷2 (default)
1 1 ÷1
Q
Pulldown
CLK
nQ
Pullup
VCO
490 - 640MHz
nCLK
Phase
Detector
Internal Feedback
÷5
2
Pullup/Pulldown
F_SEL[1:0]
MR
Pulldown
Pullup
OE
The Preliminary Information presented herein represents a product in pre-production.The noted characteristics are based on initial product characterization
and/or qualification.Integrated DeviceTechnology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT™ / ICS™ PCI EXPRESS/JITTER ATTENUATOR
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ICS874001I-02
PCI EXPRESS/JITTER ATTENUATOR
PRELIMINARY
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
PLL select pin. When LOW, bypasses or selects VCO. When HIGH
selects VCO. LVCMOS/LVTTL interface levels.
1
PLL_SEL
Input
Pullup
2, 3, 4, 15,
16, 20
nc
MR
Unused
Input
No connect.
Active High Master Reset. When logic HIGH, the internal dividers are
reset causing the true output Q to go LOW and the inverted output
nQ to go HIGH. When logic LOW, the internal dividers and the
outputs are enabled. LVCMOS/LVTTL interface levels.
Selects PLL Bandwidth input. LVCMOS/LVTTL interface levels.
See Table 3B.
5
Pulldown
Pulldown
6
BW_SEL
Input
7
8
F_SEL1
VDDA
Input
Power
Input
Pullup Frequency select pin. LVCMOS/LVTTL interface levels. See Table 3C.
Analog supply pin.
9
F_SEL0
VDD
Pulldown Frequency select pin. LVCMOS/LVTTL interface levels. See Table 3C.
Core supply pin.
10
Power
Output enable. When HIGH, outputs are enabled. When LOW, forces
Pullup
11
OE
Input
outputs to HiZ state. LVCMOS/LVTTL interface levels. See Table 3A.
12
13
CLK
nCLK
GND
nQ, Q
VDDO
Input
Input
Pulldown Non-inverting differential clock input.
Pullup Inverting differential clock input.
Power supply ground.
14
Power
Output
Power
17, 18
19
Differential output pair. LVDS interface levels.
Output supply pin.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum Typical
Maximum Units
Input Capacitance
Input Pullup Resistor
4
pF
kΩ
kΩ
RPULLUP
51
51
RPULLDOWN Input Pulldown Resistor
TABLE 3B. PLL BANDWIDTH CONTROL TABLE
Input
TABLE 3A. OUTPUT ENABLE FUNCTION TABLE
Inputs
Outputs
Q/nQ
BW_SEL
PLL Bandwidth
OE
0
0
2.2MHz (default)
HiZ
1
3MHz
1
Enabled
TABLE 3C. F_SELX FUNCTION TABLE
Input Frequency
Inputs
Output Frequency
(MHz)
(MHz)
F_SEL1
F_SEL0
Divider
100
0
0
5
100
125
100
100
100
0
1
1
1
0
1
4
2
1
250 (default)
500
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PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
DD
Inputs, V
-0.5V to VDD + 0.5 V
-0.5V to VDD + 0.5V
I
Outputs, VO
Package Thermal Impedance, θJA 73.2°C/W (0 lfpm)
Storage Temperature, T -65°C to 150°C
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VDD
VDDA
VDDO
IDD
Core Supply Voltage
3.465
VDD
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
VDD – 0.10
3.135
3.3
3.3
3.465
V
60
mA
mA
mA
IDDA
IDDO
10
20
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
2.375
Typical Maximum Units
VDD
VDDA
VDDO
IDD
Core Supply Voltage
2.5
2.5
2.5
60
2.625
VDD
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
VDD – 0.10
2.375
2.625
V
mA
mA
mA
IDDA
IDDO
10
20
TABLE 4C. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5ꢀ OR 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VDD = 3.465V
2
VDD + 0.3
VDD + 0.3
0.8
V
V
V
V
VIH
VIL
Input High Voltage
VDD = 2.625V
VDD = 3.465V
VDD = 2.625V
1.7
-0.3
-0.3
Input Low Voltage
F_SEL1,
0.7
V
DD = VIN = 3.465V or 2.625V
5
µA
µA
µA
µA
OE, PLL_SEL
Input
IIH
High Current
F_SEL0,
VDD = VIN = 3.465V or 2.625V
VDD = 3.465V or 2.625V, VIN = 0V
VDD = 3.465V or 2.625V, VIN = 0V
150
MR, BW_SEL
F_SEL1,
-150
-5
OE, PLL_SEL
Input
IIL
Low Current
F_SEL0,
MR, BW_SEL
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PRELIMINARY
TABLE 4D. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±±5 OR 2.±V±±5% TA = -40°C TO 8±°C
Symbol Parameter
IIH Input High Current
Test Conditions
Minimum Typical Maximum Units
CLK
V
DD = VIN = 3.46±V or 2.62±V
1±0
µA
µA
µA
µA
V
nCLK
CLK
VDD = VIN = 3.46±V or 2.62±V
VDD = VIN = 3.46±V or 2.62±V
VDD = VIN = 3.46±V or 2.62±V
±
1±0
IIL
Input Low Current
nCLK
-1±0
0.1±
VPP
Peak-to-Peak Input Voltage
1.3
Common Mode Input Voltage;
NOTE 1% 2
VCMR
GND + 0.±
VDD - 0.8±
V
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications% the maximum input voltage for CLK% nCLK is VDD + 0.3V.
TABLE 4E. LVDS DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±±5% TA = -40°C TO 8±°C
Symbol Parameter
Test Conditions
Minimum
Typical
42±
±0
Maximum Units
VOD
Differential Output Voltage
mV
mV
V
∆ VOD
VOS
VOD Magnitude Change
Offset Voltage
1.4
∆ VOS
VOS Magnitude Change
±0
mV
TABLE 4F. LVDS DC CHARACTERISTICS, VDD = VDDA = VDDO = 2.±V±±5% TA = -40°C TO 8±°C
Symbol Parameter Test Conditions Minimum
Typical
390
±0
Maximum Units
VOD
Differential Output Voltage
mV
mV
V
∆ VOD
VOS
VOD Magnitude Change
Offset Voltage
1.2
∆ VOS
VOS Magnitude Change
±0
mV
TABLE 5A. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±±5% TA = -40°C TO 8±°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
fMAX
Output Frequency
98
640
±0
MHz
ps
tjit(cc)
tR / tF
odc
Cycle-to-Cycle Jitter% NOTE 1
Output Rise/Fall Time
Output Duty Cycle
205 to 805
3±0
±0
ps
5
Minimum and maximum values are design target specs.
NOTE 1: This parameter is defined in accordance with JEDEC Standard 6±.
TABLE 5B. AC CHARACTERISTICS, VDD = VDDA = VDDO = 2.±V±±5% TA = -40°C TO 8±°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
fMAX
Output Frequency
98
640
±0
MHz
ps
tjit(cc)
tR / tF
odc
Cycle-to-Cycle Jitter% NOTE 1
Output Rise/Fall Time
Output Duty Cycle
205 to 805
3±±
±0
ps
5
Minimum and maximum values are design target specs.
NOTE 1: This parameter is defined in accordance with JEDEC Standard 6±.
IDT™ / ICS™ PCI EXPRESS/JITTER ATTENUATOR
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PCI EXPRESS/JITTER ATTENUATOR
PRELIMINARY
PARAMETER MEASUREMENT INFORMATION
SCOPE
SCOPE
VDD%
VDDO
VDD%
VDDO
Qx
Qx
2.±V±±5
POWER SUPPLY
3.3V±±5
POWER SUPPLY
VDDA
VDDA
+
Float GND –
+
Float GND –
LVDS
LVDS
nQx
nQx
3.3V LVDS OUTPUT LOAD AC TEST CIRCUIT
2.5V LVDS OUTPUT LOAD AC TEST CIRCUIT
VDD
nQ
Q
nCLK
➤
➤
tcycle n
tcycle n+1
➤
➤
VPP
VCMR
Cross Points
tjit(cc) = tcycle n – tcycle n+1
1000 Cycles
CLK
GND
DIFFERENTIAL INPUT LEVEL
CYCLE-TO-CYCLE JITTER
nQ
805
805
tR
Q
VOD
tPW
Clock
Outputs
205
205
tPERIOD
tF
tPW
odc =
x 1005
tPERIOD
OUTPUT RISE/FALL TIME
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
VDD
VDD
out
➤
out
➤
DC Input
LVDS
LVDS
DC Input
100
V
OD/∆ VOD
➤
out
VOS/∆ VOS
out
➤
DIFFERENTIAL OUTPUT VOLTAGE SETUP
OFFSET VOLTAGE SETUP
IDT™ / ICS™ PCI EXPRESS/JITTER ATTENUATOR
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ICS874001AGI-02 REV. A JANUARY 3, 2007
ICS874001I-02
PCI EXPRESS/JITTER ATTENUATOR
PRELIMINARY
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS874001I-02
provides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VDD, VDDA, and VDDO
should be individually connected to the power supply plane
through vias, and bypass capacitors should be used for each
pin. To achieve optimum jitter performance, power supply iso-
lation is required. Figure 1 illustrates how a 10Ω resistor along
with a 10µF and a .01µF bypass capacitor should be con-
nected to each VCCA pin.
3.3V, 2,5V
VDD
.01µF
.01µF
10Ω
VDDA
10µF
FIGURE 1. POWER SUPPLY FILTERING
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired
to accept single ended levels. The reference voltage
the input pin. The ratio of R1 and R2 might need to be adjusted
to position the V_REF in the center of the input voltage swing.
V_REF = V /2 is generated by the bias resistors R1, R2 and
C1. This bias circuit should be located as close as possible to
For example, if the input clock swing is only 2.5V and V
3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
=
DD
DD
VDD
R1
1K
Single Ended Clock Input
V_REF
CLK
nCLK
C1
0.1u
R2
1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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PRELIMINARY
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both VSWING and VOH must meet the
VPP and VCMR input requirements. Figures 3A to 3D show interface
examples for the HiPerClockS CLK/nCLK input driven by the
most common driver types. The input interfaces suggested here
are examples only. Please consult with the vendor of the driver
component to confirm the driver termination requirements. For
example in Figure 3A, the input termination applies for IDT
HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
HiPerClockS
LVPECL
Input
nCLK
HiPerClockS
LVHSTL
Input
R1
50
R2
50
ICS
R1
50
R2
50
HiPerClockS
LVHSTL Driver
R3
50
FIGURE 3A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
IDT HIPERCLOCKS LVHSTL DRIVER
FIGURE 3B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
3.3V
R3
125
R4
125
LVDS_Driver
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
R1
100
nCLK
Receiv er
nCLK
HiPerClockS
Input
Zo = 50 Ohm
LVPECL
R1
84
R2
84
FIGURE 3C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
RECOMMENDATIONS FOR UNUSED INPUT PINS
INPUTS:
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
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PRELIMINARY
3.3V, 2.5V LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 4. In a 100Ω
differential transmission line environment, LVDS drivers
require a matched load termination of 100Ω across near
the receiver input. For a multiple LVDS outputs buffer, if only
partial outputs are used, it is recommended to terminate the
unused outputs.
3.3V or 2.5V
VDD
LVDS
+
R1
100
-
100 Ω Differential Transmission
FIGURE 4. TYPICAL LVDS DRIVER TERMINATION
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PRELIMINARY
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS874001I-02.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS874001I-02 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V = 3.3V + 5ꢀ = 3.465V, which gives worst case results.
DD
•
•
Power (core) = V
* (I
+ I
) = 3.465V * (60mA + 10mA) = 242.55mW
DDA_MAX
MAX
DD_MAX
DD_MAX
Power (outputs) = V
* I
= 3.465V * 20mA = 69.3mW
DDO_MAX
MAX
DDO_MAX
Total Power
= 242.55mW + 69.3mW = 311.85mW
_MAX
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
TM
device. The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.312W * 66.6°C/W = 105.8°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and
the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θ FOR 20-LEAD TSSOP, FORCED CONVECTION
JA
θ by Velocity (Linear Feet per Minute)
JA
0
200
98.0°C/W
66.6°C/W
500
88.0°C/W
63.5°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
73.2°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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PRELIMINARY
RELIABILITY INFORMATION
TABLE 7. θ VS. AIR FLOW TABLE FOR 20 LEAD TSSOP
JA
θ by Velocity (Linear Feet per Minute)
JA
0
200
98.0°C/W
66.6°C/W
500
88.0°C/W
63.5°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
73.2°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS874001I-02 is: 1608
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PRELIMINARY
PACKAGE OUTLINE - G SUFFIX FOR 20 LEAD TSSOP
TABLE 8. PACKAGE DIMENSIONS
Millimeters
SYMBOL
MIN
MAX
N
A
20
--
1.20
0.15
1.05
0.30
0.20
6.60
A1
A2
b
0.05
0.80
0.19
0.09
6.40
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
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PRELIMINARY
TABLE 9. ORDERING INFORMATION
Part/Order Number
ICS874001AGI-02
Marking
TBD
Package
Shipping Packaging
tube
Temperature
20 Lead TSSOP
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
ICS874001AGI-02T
ICS874001AGI-02LF
ICS874001AGI-02LFT
TBD
20 Lead TSSSOP
2500 tape & reel
tube
ICS4001AI02L
ICS4001AI02L
20 Lead "Lead-Free" TSSOP
20 Lead "Lead-Free" TSSOP
2500 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and
industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT
reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT™ / ICS™ PCI EXPRESS/JITTER ATTENUATOR
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PRELIMINARY
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
800-345-7015
408-284-8200
Fax: 408-284-2775
For Tech Support
netcom@idt.com
480-763-2056
Corporate Headquarters
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
Asia Pacific and Japan
Integrated Device Technology
Singapore (1997) Pte. Ltd.
Reg. No. 199707558G
435 Orchard Road
Europe
IDT Europe, Limited
321 Kingston Road
Leatherhead, Surrey
KT22 7TU
United States
800 345 7015
#20-03 Wisma Atria
England
+408 284 8200 (outside U.S.)
Singapore 238877
+44 (0) 1372 363 339
Fax: +44 (0) 1372 378851
+65 6 887 5505
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks
of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be
trademarks or registered trademarks used to identify products or services of their respective owners.
Printed in USA
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