ICS8741004AGILF [IDT]
PLL Based Clock Driver, 8741004 Series, 4 True Output(s), 0 Inverted Output(s), PDSO24, 4.40 X 7.80 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-24;
| 型号： | ICS8741004AGILF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PLL Based Clock Driver, 8741004 Series, 4 True Output(s), 0 Inverted Output(s), PDSO24, 4.40 X 7.80 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-24 光电二极管 |
| 文件： | 总12页 (文件大小：333K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS8741004I
PCI EXPRESS™
JITTER ATTENUATOR
Integrated
Circuit
Systems, Inc.
GENERAL DESCRIPTION
FEATURES
The ICS8741004I is a high performance • Two differential LVDS and two HCSL output pairs
ICS
HiPerClockS™
Differential-to-LVDS/HCSL Jitter Attenuator
• One differential clock input
designed for use in PCI Express™ systems. In
some PCI Express systems, such as those found
in desktop PCs, the PCI Express clocks are
• CLK and nCLK supports the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
generated from a low bandwidth, high phase noise PLL
frequency synthesizer. In these systems, a jitter attenuator
may be required to attenuate high frequency random and
deterministic jitter components from the PLL synthesizer
and from the system board. The ICS8741004I has 3 PLL
bandwidth modes: 200kHz, 400kHz, and 800kHz. The
200kHz mode will provide maximum jitter attenuation, but
with higher PLL tracking skew and spread spectrum
modulation from the motherboard synthesizer may be
attenuated. 400kHz provides an intermediate bandwidth
that can easily track triangular spread profiles, while provid-
ing good jitter attenuation. 800kHz bandwidth provides the
best tracking skew and will pass most spread profiles, but
the jitter attenuation will not be as good as the lower band-
width modes. Because some 2.5Gb serdes have x20
multipliers while others have x25 multipliers, the 8741004I
can be set for 1:1 mode or 5/4 multiplication mode
(i.e. 100MHz input/125MHz output) using the FSEL pins.
• Output frequency range: 98MHz - 160MHz
• Input frequency range: 98MHz - 128MHz
• VCO range: 490MHz - 640MHz
• Cycle-to-cycle jitter: 15ps (typical)
• 3.3V operating supply
• Three bandwidth modes allow the system designer to
make jitter attenuation/tracking skew design trade-offs
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS-compliant
packages
PLL BANDWIDTH
The ICS8741004I uses ICS 3rd Generation FemtoClockTM
PLL technology to achive the lowest possible phase noise.
The device is packaged in a 24 Lead TSSOP package,
making it ideal for use in space constrained applications such
as PCI Express add-in cards.
BW_SEL
0 = PLL Bandwidth: ~200kHz
Float = PLL Bandwidth: ~400kHz (Default)
1 = PLL Bandwidth: ~800kHz
BLOCK DIAGRAM
PIN ASSIGNMENT
PU
OEA
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
nQB1
QB1
VDDO
QB0
nQA1
QA1
VDDO
F_SELA
PD
QA0
Float
QA0
BW_SEL
0 = ~200kHz
F_SELA
nQA0
MR
BW_SEL
nc
nQB0
IREF
F_SELB
OEB
0
1
÷5 (default)
÷4
nQA0
QA1
Float = ~400kHz
1 = ~800kHz
PD
PU
CLK
17
16
15
14
13
9
VDDA
Phase
VCO
GND
nQA1
QB0
490 - 640 MHz
nCLK
10
11
12
Detector
F_SELA
VDD
GND
nCLK
OEA
CLK
F_SELB
0
1
÷5 (default)
÷4
nQB0
QB1
ICS8741004I
24-LeadTSSOP
M = ÷5 (fixed)
4.40mm x 7.8mm x 0.92mm
package body
nQB1
PD
PD
F_SELB
MR
G Package
TopView
IREF
OEB
Current Set
PU
The Preliminary Information presented herein represents a product in prototyping or pre-production.The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
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REV.A MAY 31, 2006
1
PRELIMINARY
ICS8741004I
PCI EXPRESS™
JITTER ATTENUATOR
Integrated
Circuit
Systems, Inc.
TABLE 1. PIN DESCRIPTIONS
Number
1, 2
Name
nQA1, QA1
VDDO
Type
Description
Output
Power
Output
Differential output pair. LVDS interface levels.
Output supply pins.
3, 22
4, 5
QA0, nQA0
Differential output pair. LVDS interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs (Qx) to go low and the inverted outputs
(nQx) to go high. When logic LOW, the internal dividers and the outputs
are enabled. LVCMOS/LVTTL interface levels.
6
MR
Input
Pulldown
Pullup/
Pulldown
7
BW_SEL
Input
Selects PLL Bandwidth input. LVCMOS/LVTTL interface levels.
8
9
nc
Unused
Power
No connect
VDDA
Analog supply pin.
Frequency select pin for QAx/nQAx outputs.
LVCMOS/LVTTL interface levels.
10
11
F_SELA
VDD
Input
Pulldown
Pullup
Power
Core supply pin.
Output enable pin for QA pins. When HIGH, the QAx/nQAx outputs are
active. When LOW, the QAx/nQAx outputs are in a high impedance
state. LVCMOS/LVTTL interface levels.
12
OEA
Input
13
14
CLK
nCLK
GND
Input
Input
Pulldown Non-inverting differential clock input.
Pullup
Inverting differential clock input.
Power supply ground.
15, 16
Power
Output enable pin for QB pins. When HIGH, the QBx/nQBx outputs are
active. When LOW, the QBx/nQBx outputs are in a high impedance
state. LVCMOS/LVTTL interface levels.
Frequency select pin for QBx/nQBx outputs.
LVCMOS/LVTTL interface levels.
A fixed precision resistor (RREF = 475Ω) from this pin to ground
provides a reference current used for differential current-mode
QB0/nQB0 clock outputs.
17
18
19
OEB
F_SELB
IREF
Input
Input
Input
Pullup
Pulldown
20, 21
23, 24
nQB0, QB0
QB1, nQB1
Output
Output
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
CIN
Input Capacitance
Input Pullup Resistor
4
pF
kΩ
kΩ
RPULLUP
51
51
RPULLDOWN Input Pulldown Resistor
TABLE 3A. OUTPUT ENABLE FUNCTION TABLE
TABLE 3B. PLL BANDWIDTH/PLL BYPASS CONTROL
Inputs
Outputs
Inputs
PLL
Bandwidth
OEA
OEB QAx/nQAx QBx/nQBx
PLL_BW
0
1
~200kHz
~800kHz
~400kHz
0
1
0
1
HiZ
HiZ
Enabled
Enabled
Float
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PRELIMINARY
ICS8741004I
PCI EXPRESS™
JITTER ATTENUATOR
Integrated
Circuit
Systems, Inc.
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
DD
Inputs, V
-0.5V to VDD + 0.5 V
-0.5V to VDDO + 0.5V
70°C/W (0 lfpm)
-65°C to 150°C
I
Outputs, VO
PackageThermal Impedance, θ
JA
StorageTemperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD =VDDA =VDDO = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD
VDDA
VDDO
IDD
Core Supply Voltage
3.135
3.135
3.135
3.3
3.3
3.3
25
8
3.465
3.465
3.465
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
V
mA
mA
mA
IDDA
IDDO
65
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
F_SELA, FESL_B,
MR, OEA, OEB
2
VDD + 0.3
VDD + 0.3
0.8
V
V
V
VIH
VIL
IIH
Input High Voltage
BW_SEL
V
DD - 0.3
-0.3
F_SELA, FESL_B,
MR, OEA, OEB
Input Low Voltage
Input High Current
BW_SEL
-0.3
+0.3
5
V
OEA, OEB
VDD = VIN = 3.465V
µA
BW_SEL, MR,
F_SELA, FESL_B
BW_SEL,
OEA, OEB,
MR, F_SELA,
FESL_B
V
DD = VIN = 3.465V
DD = 3.465V, VIN = 0V
VDD = 3.465V, VIN = 0V
150
µA
µA
µA
V
-150
-5
IIL
Input Low Current
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD =VDDA =VDDO = 3.3V 5ꢀ,TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
CLK
V
DD = VIN = 3.465V
VDD = VIN = 3.465V
VDD = VIN = 3.465V
VDD = VIN = 3.465V
150
µA
µA
µA
µA
V
IIH
Input High Current
nCLK
CLK
5
150
IIL
Input Low Current
nCLK
-150
0.15
VPP
Peak-to-Peak Input Voltage
1.3
VCMR
Common Mode Input Voltage; NOTE 1, 2
GND + 0.5
VDD - 0.85
V
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V.
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REV.A MAY 31, 2006
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PRELIMINARY
ICS8741004I
PCI EXPRESS™
JITTER ATTENUATOR
Integrated
Circuit
Systems, Inc.
TABLE 4D. LVDS DC CHARACTERISTICS, VDD =VDDA = VDDO = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum
Typical
Maximum Units
VOD
Differential Output Voltage
350
50
mV
mV
V
Δ VOD
VOS
VOD Magnitude Change
Offset Voltage
1.3
40
Δ VOS
VOS Magnitude Change
mV
TABLE 4E. HCSL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5ꢀ OR 2.5V 5ꢀ, TA = -40°C TO 85°C, RREF = 475Ω
Symbol Parameter
Test Conditions
Minimum
Typical
13.89
0.73
Maximum Units
IOH
Output Current
mA
V
VOH
VOL
IOZ
Output High Voltage
Output Low Voltage
0.03
V
High Impedance Leakage Current
Output Crossover Voltage
-10
10
µA
VOX
250
550
mV
TABLE 5. AC CHARACTERISTICS, VDD =VDDA =VDDO = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fMAX
Output Frequency
98
160
MHz
ps
tjit(cc)
tR / tF
odc
Cycle-to-Cycle Jitter, NOTE 1
Output Rise/Fall Time
Output Duty Cycle
15
400
50
20ꢀ to 80ꢀ
ps
ꢀ
NOTE 1: This parameter is defined in accordance with JEDEC Standard 65.
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REV.A MAY 31, 2006
4
PRELIMINARY
ICS8741004I
PCI EXPRESS™
JITTER ATTENUATOR
Integrated
Circuit
Systems, Inc.
PARAMETER MEASUREMENT INFORMATION
3.3V 5ꢀ
3.3V 5ꢀ
SCOPE
VDD
SCOPE
Qx
3.3V 5ꢀ
Qx
POWER SUPPLY
+
HCSL
LVDS
Float GND
-
nQx
GND
0V
3.3V LVDS OUTPUT LOAD AC TEST CIRCUIT
3.3V HCSL OUTPUT LOAD AC TEST CIRCUIT
nQAx,
nQBx
VDD
QAx,
QBx
tPW
nCLK
tPERIOD
VPP
VCMR
Cross Points
tPW
tPERIOD
CLK
odc =
x 100ꢀ
GND
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
DIFFERENTIAL INPUT LEVEL
nQAx,
nQBx
80ꢀ
tF
80ꢀ
tR
QAx,
QBx
VSWING
20ꢀ
➤
➤
tcycle n
tcycle n+1
➤
➤
Clock
Outputs
20ꢀ
tjit(cc) = tcycle n –tcycle n+1
1000 Cycles
OUTPUT RISE/FALL TIME
CYCLE-TO-CYCLE JITTER
VDD
VDD
out
➤
out
out
➤
DC Input
LVDS
LVDS
DC Input
100
V
OD/Δ VOD
➤
out
VOS/Δ VOS
➤
DIFFERENTIAL OUTPUT VOLTAGE SETUP
OFFSET VOLTAGE SETUP
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REV.A MAY 31, 2006
5
PRELIMINARY
ICS8741004I
PCI EXPRESS™
JITTER ATTENUATOR
Integrated
Circuit
Systems, Inc.
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS8741004I provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL.VDD, VDDA, and VDDO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10μF and a .01μF bypass
capacitor should be connected to each VDDA pin. The 10Ω
resistor can also be replaced by a ferrite bead.
3.3V
VDD
.01μF
10Ω
VDDA
.01μF
10μF
FIGURE 1. POWER SUPPLY FILTERING
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept of R1 and R2 might need to be adjusted to position theV_REF in
single ended levels. The reference voltage V_REF = VDD/2 is the center of the input voltage swing. For example, if the input
generated by the bias resistors R1, R2 and C1.This bias circuit clock swing is only 2.5V andVDD = 3.3V,V_REF should be 1.25V
should be located as close as possible to the input pin.The ratio and R2/R1 = 0.609.
VDD
R1
1K
Single Ended Clock Input
CLK
V_REF
nCLK
C1
0.1u
R2
1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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PRELIMINARY
ICS8741004I
PCI EXPRESS™
JITTER ATTENUATOR
Integrated
Circuit
Systems, Inc.
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL here are examples only. Please consult with the vendor of the
and other differential signals.BothVSWING andVOH must meet the driver component to confirm the driver termination requirements.
VPP and VCMR input requirements. Figures 3A to 3D show inter- For example in Figure 3A, the input termination applies for ICS
face examples for the HiPerClockS CLK/nCLK input driven by HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
the most common driver types.The input interfaces suggested from another vendor, use their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
HiPerClockS
Input
LVPECL
nCLK
HiPerClockS
Input
LVHSTL
R1
50
R2
50
ICS
HiPerClockS
R1
50
R2
50
LVHSTL Driver
R3
50
FIGURE 3A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
ICS HIPERCLOCKS LVHSTL DRIVER
FIGURE 3B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
3.3V
R3
125
R4
125
LVDS_Driver
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
R1
100
nCLK
Receiv er
nCLK
HiPerClockS
Input
Zo = 50 Ohm
LVPECL
R1
84
R2
84
FIGURE 3C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
LVCMOS CONTROL PINS:
LVDS OUTPUT
All control pins have internal pull-ups or pull-downs; additional All unused LVDS output pairs can be either left floating or
resistance is not required but can be added for additional terminated with 100Ω across. If they are left floating, there
protection. A 1kΩ resistor can be used.
should be no trace attached.
HCSL OUTPUT
All unused HCSL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential
output pair should either be left floating or terminated.
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REV.A MAY 31, 2006
7
PRELIMINARY
ICS8741004I
PCI EXPRESS™
JITTER ATTENUATOR
Integrated
Circuit
Systems, Inc.
LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 4. In a 100Ω
differential transmission line environment, LVDS drivers
require a matched load termination of 100Ω across near
the receiver input. For a multiple LVDS outputs buffer, if only
partial outputs are used, it is recommended to terminate the
un-used outputs.
3.3V
3.3V
LVDS_Driver
+
R1
100
-
100 Ohm Differiential Transmission Line
FIGURE 4. TYPICAL LVDS DRIVERT ERMINATION
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REV.A MAY 31, 2006
8
PRELIMINARY
ICS8741004I
PCI EXPRESS™
JITTER ATTENUATOR
Integrated
Circuit
Systems, Inc.
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8741004I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8741004I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5ꢀ = 3.465V, which gives worst case results.
•
•
Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (25mA + 8mA) = 114.34mW
Power (outputs)MAX = VDDO_MAX * IDDO_MAX = 3.465V * 65mA = 225.22mW
Total Power_MAX = 294.52mW + 381.15mW = 339.56mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of
the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used.
Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 63°C/W per
Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.340W * 63°C/W = 106.4°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air
flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θJA FOR 24-LEADTSSOP, FORCED CONVECTION
θ
JA by Velocity (Linear Feet per Minute)
0
200
500
Multi-Layer PCB, JEDEC Standard Test Boards
70°C/W
63°C/W
60°C/W
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REV.A MAY 31, 2006
9
PRELIMINARY
ICS8741004I
PCI EXPRESS™
JITTER ATTENUATOR
Integrated
Circuit
Systems, Inc.
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOWT ABLE FOR 24 LEAD TSSOP
θJA byVelocity (Linear Feet per Minute)
0
200
500
Multi-Layer PCB, JEDEC Standard Test Boards
70°C/W
63°C/W
60°C/W
TRANSISTOR COUNT
The transistor count for ICS8741004I is: 1318
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10
PRELIMINARY
ICS8741004I
PCI EXPRESS™
JITTER ATTENUATOR
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - G SUFFIX FOR 24 LEAD TSSOP
TABLE 8. PACKAGE DIMENSIONS
Millimeters
Minimum Maximum
SYMBOL
N
A
24
--
1.20
0.15
1.05
0.30
0.20
7.90
A1
A2
b
0.05
0.80
0.19
0.09
7.70
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
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REV.A MAY 31, 2006
11
PRELIMINARY
ICS8741004I
PCI EXPRESS™
JITTER ATTENUATOR
Integrated
Circuit
Systems, Inc.
TABLE 9.ORDERING INFORMATION
Part/Order Number
ICS8741004AGI
Marking
Package
Shipping Packaging Temperature
ICS8741004AGI
ICS8741004AGI
ICS8741004AIL
ICS8741004AIL
24 Lead TSSOP
24 Lead TSSOP
tube
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
ICS8741004AGIT
ICS8741004AGILF
ICS8741004AGILFT
2500 tape & reel
tube
24 Lead "Lead-Free" TSSOP
24 Lead "Lead-Free" TSSOP
2500 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
The ICS logo is a registered trademark, and HiPerClockS is a trademark of Integrated Circuit Systems, Inc. All other trademarks are the property of their respective owners and
may be registered in certain jurisdictions.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
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REV.A MAY 31, 2006
12
相关型号：
ICS8741004AGIT
PLL Based Clock Driver, 8741004 Series, 4 True Output(s), 0 Inverted Output(s), PDSO24, 4.40 X 7.80 MM, 0.92 MM HEIGHT, MO-153, TSSOP-24
IDT
ICS8741004AGT
PLL Based Clock Driver, 8741004 Series, 4 True Output(s), 0 Inverted Output(s), PDSO24, 4 40 X 7.80 MM, 0.92 MM HEIGHT, MO-153, TSSOP-24
IDT
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PLL Based Clock Driver, 8741004 Series, 4 True Output(s), 0 Inverted Output(s), PDSO24, 4.40 X 7.80 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, TSSOP-24
IDT
ICS8741004BGIT
PLL Based Clock Driver, 8741004 Series, 4 True Output(s), 0 Inverted Output(s), PDSO24, 4.40 X 7.80 MM, 0.925 MM HEIGHT, TSSOP-24
IDT
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