ICS87946AYI-147LF [IDT]
Low Skew Clock Driver, 10 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, LQFP-32;
| 型号： | ICS87946AYI-147LF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew Clock Driver, 10 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, LQFP-32 驱动 逻辑集成电路 |
| 文件： | 总14页 (文件大小：253K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Skew, ÷1, ÷2 LVCMOS/LVTTL
Clock Generator
ICS87946I-147
DATASHEET
General Description
Features
The ICS87946I-147 is a low skew, ÷1, ÷2 LVCMOS/LVTTL Clock
Generator. The ICS87946I-147 has two selectable single ended
clock inputs. The single ended clock inputs accept LVCMOS or
LVTTL input levels. The low impedance LVCMOS/LVTTL outputs are
designed to drive 50 series or parallel terminated transmission
lines. The effective fanout can be increased from 10 to 20 by utilizing
the ability of the outputs to drive two series terminated lines.
• Ten single ended LVCMOS/LVTTL outputs,
7 typical output impedance
• Selectable LVCMOS/LVTTL CLK0 and CLK1 inputs
• CLK0 and CLK1 can accept the following input levels:
LVCMOS and LVTTL
• Maximum input frequency: 250MHz
• Bank skew: 30ps (maximum)
The divide select inputs, DIV_SELx, control the output frequency of
each bank. The outputs can be utilized in the ÷1, ÷2 or a
combination of ÷1 and ÷2 modes. The master reset input, MR/nOE,
resets the internal frequency dividers and also controls the active
and high impedance states of all outputs.
• Output skew: 175ps (maximum)
• Part-to-part skew: 850ps (maximum)
• Multiple frequency skew: 200ps (maximum)
• 3.3V core, 3.3V or 2.5V output supply modes
• -40°C to 85°C ambient operating temperature
• Lead-free packaging
The ICS87946I-147 is characterized at full 3.3V for input VDD, and
mixed 3.3V and 2.5V for output operating supply mode. Guaranteed
bank, output and part-to-part skew characteristics make the
ICS87946I-147 ideal for those clock distribution applications
demanding well defined performance and repeatability.
Block Diagram
Pin Assignment
Pulldown
CLK_SEL
Pullup
CLK0
CLK1
0
1
0
1
÷1
÷2
3
3
QA[0:2]
QB[0:2]
32 31 30 29 28 27 26 25
Pullup
Pullup
1
2
3
4
5
6
7
8
CLK_SEL
GND
24
23
22
21
20
VDD
QB0
VDDB
QB1
GND
Pulldown
DIV_SELA
CLK0
0
1
CLK1
DIV_SELA
DIV_SELB
DIV_SELC
GND
QB2
VDDB
VDDC
19
18
17
Pulldown
DIV_SELB
9
10 11 12 13 14 15 16
0
1
4
QC[0:3]
Pulldown
Pulldown
ICS87946I-147
32-Lead LQFP
DIV_SELC
MR/nOE
7mm x 7mm x 1.4mm package body
Y Package
Top View
ICS87946AYI-147 REVISION A APRIL 30, 2014
1
©2014 Integrated Device Technology, Inc.
ICS87946I-147 Data Sheet
LOW SKEW, ÷1, ÷2 LVCMOS/LVTTL CLOCK GENERATOR
Pin Descriptions and Characteristics
Table 1. Pin Descriptions
Number
Name
Type
Description
Clock select input. When HIGH, selects CLK1.
When LOW, selects CLK0. LVCMOS / LVTTL interface levels.
1
CLK_SEL
Input
Pulldown
2
VDD
Power
Input
Positive supply pin.
3, 4
CLK0, CLK1
Pullup
Single-ended clock inputs. LVCMOS/LVTTL interface levels.
Controls frequency division for Bank A outputs. See Table 3
LVCMOS/LVTTL interface levels.
5
6
7
DIV_SELA
DIV_SELB
DIV_SELC
Input
Input
Input
Pulldown
Controls frequency division for Bank B outputs. See Table 3.
LVCMOS/LVTTL interface levels.
Pulldown
Pulldown
Controls frequency division for Bank C outputs. See Table 3.
LVCMOS/LVTTL interface levels.
8, 11, 15, 20,
24, 27, 31
GND
VDDC
Power
Power
Output
Power
Output
Power
Output
Power supply ground.
9, 13, 17
Output supply pins for Bank C outputs.
10, 12,
14, 16
QC0, QC1,
QC2, QC3
Single-ended Bank C clock outputs. LVCMOS/LVTTL interface levels.
7 typical output impedance.
18, 22
VDDB
Output supply pins for Bank B outputs.
19,
21, 23
QB2,
QB1, QB0
Single-ended Bank B clock outputs. LVCMOS/LVTTL interface levels.
7 typical output impedance.
25, 29
VDDA
Output supply pins for Bank A outputs.
26,
28, 30
QA2,
QA1, QA0
Single-ended Bank A clock outputs. LVCMOS/LVTTL interface levels.
7 typical output impedance.
Active HIGH Master Reset. Active LOW Output Enable. When logic HIGH,
the internal dividers are reset and the outputs are (High-Impedance). When
logic LOW, the internal dividers and the outputs are enabled. See Table 3.
LVCMOS/LVTTL interface levels.
32
MR/nOE
Input
Pulldown
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
Input Capacitance
4
CPD
Power Dissipation Capacitance VDD = VDDA = VDDB = VDDC = 3.6V
Input Pullup Resistor
25
51
51
7
pF
RPULLUP
RPULLDOWN
ROUT
k
k
Input Pulldown Resistor
Output Impedance
ICS87946AYI-147 REVISION A APRIL 30, 2014
2
©2014 Integrated Device Technology, Inc.
ICS87946I-147 Data Sheet
LOW SKEW, ÷1, ÷2 LVCMOS/LVTTL CLOCK GENERATOR
Function Tables
Table 3. Clock Input Function Table
Inputs
Outputs
MR/nOE
DIV_SELA
DIV_SELB
DIV_SELC
QA0:QA2
High-Impedance
fIN/1
QB0:QB2
High-Impedance
Active
QC0:QC3
High-Impedance
Active
1
0
0
0
0
0
0
X
0
X
X
X
0
X
X
X
X
X
0
1
fIN/2
Active
Active
X
X
X
X
Active
fIN/1
Active
1
Active
fIN/2
Active
X
X
Active
Active
fIN/1
1
Active
Active
fIN/2
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the DC Characteristics or
AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
Inputs, VI
4.6V
-0.5V to VDD + 0.5V
-0.5V to VDDX+ 0.5V
47.9C/W (0 lfpm)
-65C to 150C
Outputs, VO
Package Thermal Impedance, JA
Storage Temperature, TSTG
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, V = V
= V
= V
= 3.3V 0.3V, T = -40°C to 85°C
DDC A
DD
DDA
DDB
Symbol
Parameter
Test Conditions
Minimum
3.0
Typical
3.3
Maximum
Units
V
VDD
Positive Supply Voltage
3.6
3.6
55
VDDA, VDDB, VDDC Output Supply Voltage
3.0
3.3
V
IDD
Power Supply Current
Output Supply Current
mA
mA
IDDA, IDDB, IDDC
23
ICS87946AYI-147 REVISION A APRIL 30, 2014
3
©2014 Integrated Device Technology, Inc.
ICS87946I-147 Data Sheet
LOW SKEW, ÷1, ÷2 LVCMOS/LVTTL CLOCK GENERATOR
Table 4B. Power Supply DC Characteristics, V = 3.3V 5%, V
= V
= V
= 2.5V 5%, T = -40°C to 85°C
DDC A
DD
DDA
DDB
Symbol
Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
2.625
55
Units
V
VDD
Positive Supply Voltage
VDDA, VDDB, VDDC Output Supply Voltage
2.375
2.5
V
IDD
Power Supply Current
Output Supply Current
mA
mA
IDDA, IDDB, IDDC
22
Table 4C. LVCMOS/LVTTL DC Characteristics, V = V
= V
= V
= 3.3V 0.3V, T = -40°C to 85°C
DDC A
DD
DDA
DDB
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VIH
VIL
Input High Voltage
2
VDD + 0.3
V
MR/nOE,
DIV_SELA, DIV_SELB,
DIV_SELC, CLK_SEL
Input
Low
Voltage
-0.3
-0.3
0.8
1.3
150
5
V
CLK0, CLK1
V
MR/nOE,
DIV_SELA, DIV_SELB,
DIV_SELC, CLK_SEL
Input
High
Current
V
DD = VIN = 3.6V
DD = VIN = 3.6V
µA
µA
µA
IIH
CLK0, CLK1
V
MR/nOE,
DIV_SELA, DIV_SELB,
DIV_SELC, CLK_SEL
Input
Low
Current
VDD = 3.6V, VIN = 0V
VDD = 3.6V, VIN = 0V
-5
IIL
CLK0, CLK1
-150
2.6
µA
V
VOH
VOL
IOZL
IOZH
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Output Hi-Z Current Low
VDDA = VDDB = VDDC = 3.6V
VDDA = VDDB = VDDC = 3.63V
VDDA = VDDB = VDDC = 3.63V
VDDA = VDDB = VDDC = 3.63V
0.5
5
V
-5
µA
µA
Output Hi-Z Current High
NOTE 1: Outputs terminated with 50 to VDDx/2. See Parameter Measurement Information section. Load Test Circuit diagrams.
ICS87946AYI-147 REVISION A APRIL 30, 2014
4
©2014 Integrated Device Technology, Inc.
ICS87946I-147 Data Sheet
LOW SKEW, ÷1, ÷2 LVCMOS/LVTTL CLOCK GENERATOR
Table 4D. LVCMOS/LVTTL DC Characteristics, V = 3.3V 5%, V
= V
= V
= 2.5V 5%, T = -40°C to 85°C
DDC A
DD
DDA
DDB
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VIH
VIL
Input High Voltage
2
VDD + 0.3
V
MR/nOE,
DIV_SELA, DIV_SELB,
DIV_SELC, CLK_SEL
Input
Low
Voltage
-0.3
-0.3
0.8
1.3
150
5
V
CLK0, CLK1
V
MR/nOE,
DIV_SELA, DIV_SELB,
DIV_SELC, CLK_SEL
Input
High
Current
V
DD = VIN = 3.465V
µA
µA
µA
IIH
CLK0, CLK1
VDD = VIN = 3.465V
MR/nOE,
DIV_SELA, DIV_SELB,
DIV_SELC, CLK_SEL
Input
Low
Current
VDD = 3.465V, VIN = 0V
-5
IIL
CLK0, CLK1
VDD = 3.465V, VIN = 0V
-150
1.8
µA
V
Output High Voltage;
NOTE 1
VOH
VDDA = VDDB = VDDC = 2.625V
VOL
IOZL
IOZH
Output Low Voltage; NOTE 1
Output Hi-Z Current Low
Output Hi-Z Current High
VDDA = VDDB = VDDC = 2.625V
VDDA = VDDB = VDDC = 2.625V
VDDA = VDDB = VDDC = 2.625V
0.5
5
V
-5
µA
µA
NOTE 1: Outputs terminated with 50 to VDDx/2. See Parameter Measurement Information section. Load Test Circuit diagrams.
ICS87946AYI-147 REVISION A APRIL 30, 2014
5
©2014 Integrated Device Technology, Inc.
ICS87946I-147 Data Sheet
LOW SKEW, ÷1, ÷2 LVCMOS/LVTTL CLOCK GENERATOR
AC Electrical Characteristics
Table 5A. AC Characteristics, V = V
= V
= V
= 3.3V 0.3V, T = -40°C to 85°C
DDC A
DD
DDA
DDB
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
fMAX
Output Frequency
250
MHz
Propagation Delay;
NOTE 1
tPD
ƒ 250MHz
2
5
ns
tsk(b)
tsk(o)
Bank Skew, NOTE 2, 7
Output Skew; NOTE 3, 7
Measured on rising edge at VDDX/2
Measured on rising edge at VDDX/2
30
ps
ps
175
Multiple Frequency Skew;
NOTE 4, 7
tsk(w)
Measured on rising edge at VDDX/2
275
850
ps
ps
Part-to-Part Skew;
NOTE 5, 7
tsk(pp)
Measured on rising edge at VDDX/2
20% to 80%
tR / tF
tPW
Output Rise/Fall Time; NOTE 6
Output Pulse Width
400
950
ps
%
tPERIOD/2 - 1
tPERIOD/2
tPERIOD/2 + 1
Output Enable Time;
NOTE 6
tEN
ƒ = 1 0 M H z
ƒ= 10MHz
3
3
n s
ns
tDIS
Output Disable Time; NOTE 6
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from VDD/2 of the input to VDDX/2 of the output.
NOTE 2: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions.
NOTE 3: Defined as skew across banks of outputs at the same supply voltage and with equal load conditions. Measured at VDDX/2.
NOTE 4: Defined as skew across banks of outputs operating at different frequencies with the same supply voltage and equal load conditions.
NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions. Using
the same type of inputs on each device, the outputs are measured at VDDX/2.
NOTE 6: These parameters are guaranteed by characterization. Not tested in production.
NOTE 7: This parameter is defined in accordance with JEDEC Standard 65.
ICS87946AYI-147 REVISION A APRIL 30, 2014
6
©2014 Integrated Device Technology, Inc.
ICS87946I-147 Data Sheet
LOW SKEW, ÷1, ÷2 LVCMOS/LVTTL CLOCK GENERATOR
Table 5B. AC Characteristics, V = 3.3V 5%, V
= V
= V
= 2.5V 5%, T = -40°C to 85°C
DDC A
DD
DDA
DDB
Symbol Parameter
fMAX Output Frequency
Test Conditions
Minimum
Typical
Maximum
Units
250
MHz
Propagation Delay;
NOTE 1
tPD
ƒ 250MHz
2
5
ns
tsk(b)
tsk(o)
Bank Skew, NOTE 2, 7
Output Skew; NOTE 3, 7
Measured on rising edge at VDDX/2
Measured on rising edge at VDDX/2
35
ps
ps
175
Multiple Frequency Skew;
NOTE 4, 7
tsk(w)
Measured on rising edge at VDDX/2
200
875
ps
ps
Part-to-Part Skew;
NOTE 5, 7
tsk(pp)
Measured on rising edge at VDDX/2
20% to 80%
tR / tF
tPW
Output Rise/Fall Time; NOTE 6
Output Pulse Width
400
950
ps
%
tPERIOD/2 - 1
tPERIOD/2
tPERIOD/2 + 1
Output Enable Time;
NOTE 6
tEN
ƒ = 1 0 M H z
ƒ= 10MHz
3
3
n s
ns
tDIS
Output Disable Time; NOTE 6
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from VDD/2 of the input to VDDX/2 of the output.
NOTE 2: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions.
NOTE 3: Defined as skew across banks of outputs at the same supply voltage and with equal load conditions. Measured at VDDX/2.
NOTE 4: Defined as skew across banks of outputs operating at different frequencies with the same supply voltage and equal load conditions.
NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions. Using
the same type of inputs on each device, the outputs are measured at VDDX/2.
NOTE 6: These parameters are guaranteed by characterization. Not tested in production.
NOTE 7: This parameter is defined in accordance with JEDEC Standard 65.
ICS87946AYI-147 REVISION A APRIL 30, 2014
7
©2014 Integrated Device Technology, Inc.
ICS87946I-147 Data Sheet
LOW SKEW, ÷1, ÷2 LVCMOS/LVTTL CLOCK GENERATOR
Parameter Measurement Information
2.05V 5%
1.65V 0.15V
1.25V 5%
SCOPE
SCOPE
V
V
DD
DD,
V
V
V
DDA,
DDB,
DDC
V
DDA,
Qx
Qx
V
V
DDB, DDC
GND
GND
-1.65V 0.15V
-1.25V 5%
3.3V Core/3.3V Output Load AC Test Circuit
3.3V Core/2.5V Output Load AC Test Circuit
Part 1
VDDO
VDDO
Qx
Qy
2
2
Qx
Qy
Part 2
VDDO
2
VDDO
2
tsk(o)
tsk(pp)
Output Skew
Part-to-Part Skew
VDDx
2
QBx, QCx
QAx
QX0:QXx
QX0:QXx
VDDx
2
tsk(ω)
tsk(b)
Where X = Bank A, B or C
Bank Skew
Multiple Frequency Skew
ICS87946AYI-147 REVISION A APRIL 30, 2014
8
©2014 Integrated Device Technology, Inc.
ICS87946I-147 Data Sheet
LOW SKEW, ÷1, ÷2 LVCMOS/LVTTL CLOCK GENERATOR
Parameter Measurement Information, continued
VDDx
2
VDDx
2
VDDx
2
VDDx
2
QAx,
QBx, QCx
CLK0, CLK1
tPW
tPERIOD
VDDx
2
QAx,
QBx, QCx
tPW
odc =
t
PD
tPERIOD
tPW & tPERIOD
Propagation Delay
80%
tF
80%
tR
20%
20%
QAx,
QBx, QCx
Output Rise/Fall Time
ICS87946AYI-147 REVISION A APRIL 30, 2014
9
©2014 Integrated Device Technology, Inc.
ICS87946I-147 Data Sheet
LOW SKEW, ÷1, ÷2 LVCMOS/LVTTL CLOCK GENERATOR
Application Information
Recommendations for Unused Input and Output Pins
Inputs:
OUTputs:
LVCMOS Control Pins
LVCMOS Outputs
All control pins have internal pulldowns; additional resistance is not
required but can be added for additional protection. A 1k resistor
can be used.
All unused LVCMOS output can be left floating. There should be no
trace attached.
CLK Inputs
For applications not requiring the use of a clock input, it can be left
floating. Though not required, but for additional protection, a 1k
resistor can be tied from the CLK input to ground.
Reliability Information
Table 6. vs. Air Flow Table for a 32-Lead LQFP
JA
JA vs. Air Flow
Linear Feet per Minute
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
55.9°C/W
42.1°C/W
50.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
Transistor Count
The transistor count for ICS87946I-147 is: 1204
Pin compatible to the MPC9446 and MPC946
ICS87946AYI-147 REVISION A APRIL 30, 2014
10
©2014 Integrated Device Technology, Inc.
ICS87946I-147 Data Sheet
LOW SKEW, ÷1, ÷2 LVCMOS/LVTTL CLOCK GENERATOR
Package Outline and Package Dimensions
Package Outline - Y Suffix for 32-Lead LQFP
Table 7. Package Dimensions for 32-Lead LQFP
JEDEC Variation: BBC - HD
All Dimensions in Millimeters
Symbol
Minimum
Nominal
Maximum
N
32
A
1.60
0.15
1.45
0.45
0.20
A1
0.05
1.35
0.30
0.09
0.10
1.40
0.37
A2
b
c
D & E
D1 & E1
D2 & E2
e
9.00 Basic
7.00 Basic
5.60 Ref.
0.80 Basic
0.60
L
0.45
0°
0.75
7°
ccc
0.10
Reference Document: JEDEC Publication 95, MS-026
ICS87946AYI-147 REVISION A APRIL 30, 2014
11
©2014 Integrated Device Technology, Inc.
ICS87946I-147 Data Sheet
LOW SKEW, ÷1, ÷2 LVCMOS/LVTTL CLOCK GENERATOR
Ordering Information
Table 8. Ordering Information
Part/Order Number
87946AYI-147LF
87946AYI-147LFT
Marking
ICS7946AI147L
ICS7946AI147L
Package
“Lead-Free” 32-Lead LQFP
“Lead-Free” 32-Lead LQFP
Shipping Packaging
Tray
Temperature
-40C to 85C
-40C to 85C
Tape & Reel
Tape & Reel,
Pin1 Orientation: EIA-481-D
87946AYI-147LF/W
ICS7946AI147L
“Lead-Free” 32-Lead LQFP
-40C to 85C
ICS87946AYI-147 REVISION A APRIL 30, 2014
12
©2014 Integrated Device Technology, Inc.
ICS87946I-147 Data Sheet
LOW SKEW, ÷1, ÷2 LVCMOS/LVTTL CLOCK GENERATOR
Revision History Sheet
Rev
Table
Page
Description of Change
Date
1
2
8
Features section added Lead-Free bullet.
Pin Description Table - corrected description for VDDA, VDDB and VDDC.
Parameter Measurement Information Section - added part-to-part skew, bank
skew, and multiple frequency skew diagrams.
T2
A
7/22/08
10
12
Application Section - added Recommendations for Unused Input and Output Pins.
Ordering Information Table - added lead-free marking.
T8
Updated format throughout the datasheet.
T5A - T5B
T8
6 - 7
12
AC Tables - added thermal note.
Ordering Information Table - corrected the Part/Order Numbers and corrected the
non-LF marking.
A
8/7/09
Updated Header/Footer of the datasheet.
A
A
T8
T8
12
Removed leaded orderable parts from Ordering Information table
11/15/12
4/30/14
12
14
Ordering Information Table - Added 87946AYI-147LF/W Ordering option.
Updated Technical Support Contact Info to: clocks@idt.com
ICS87946AYI-147 REVISION A APRIL 30, 2014
13
©2014 Integrated Device Technology, Inc.
ICS87946I-147 Data Sheet
LOW SKEW, ÷1, ÷2 LVCMOS/LVTTL CLOCK GENERATOR
We’ve Got Your Timing Solution
6024 Silver Creek Valley Road Sales
Technical Support
800-345-7015 (inside USA)
clocks@idt.com
San Jose, California 95138
+408-284-8200 (outside USA) +480-763-2056
Fax: 408-284-2775
www.IDT.com/go/contactIDT
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document,
including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not
guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the
suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any
license under intellectual property rights of IDT or any third parties.
IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to signifi-
cantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third
party owners.
Copyright 2014. All rights reserved.
相关型号：
ICS87946AYI-147LFT
Low Skew Clock Driver, 10 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, LQFP-32
IDT
ICS87946AYI-147T
Low Skew Clock Driver, 10 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, LQFP-32
IDT
ICS87946AYILF
Low Skew Clock Driver, 10 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-32
IDT
ICS87946AYILFT
Low Skew Clock Driver, 10 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-32
IDT
ICS87949AY
Low Skew Clock Driver, 15 True Output(s), 0 Inverted Output(s), PQFP52, 10 X 10 MM, 1.40 MM HEIGHT, MS-026, LQFP-52
IDT
ICS87949AY-01
Low Skew Clock Driver, 15 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-48
IDT
ICS87949AY-01LF
Low Skew Clock Driver, 15 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-48
IDT
ICS87949AY-01T
Low Skew Clock Driver, 15 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-48
IDT
ICS87949AYI-01LF
Low Skew Clock Driver, 15 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-48
IDT
©2020 ICPDF网 联系我们和版权申明